| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/13.prim_present_test.4030803614 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1884574147 |
| /workspace/coverage/default/1.prim_present_test.993859066 |
| /workspace/coverage/default/10.prim_present_test.321485383 |
| /workspace/coverage/default/11.prim_present_test.4178889278 |
| /workspace/coverage/default/12.prim_present_test.3207060117 |
| /workspace/coverage/default/14.prim_present_test.1143315549 |
| /workspace/coverage/default/15.prim_present_test.650594032 |
| /workspace/coverage/default/16.prim_present_test.320092784 |
| /workspace/coverage/default/17.prim_present_test.2028185176 |
| /workspace/coverage/default/18.prim_present_test.1192135838 |
| /workspace/coverage/default/19.prim_present_test.1524292289 |
| /workspace/coverage/default/2.prim_present_test.1140158314 |
| /workspace/coverage/default/20.prim_present_test.3525061009 |
| /workspace/coverage/default/21.prim_present_test.2732439374 |
| /workspace/coverage/default/22.prim_present_test.1493512559 |
| /workspace/coverage/default/23.prim_present_test.1502466567 |
| /workspace/coverage/default/24.prim_present_test.3954538772 |
| /workspace/coverage/default/25.prim_present_test.4232565414 |
| /workspace/coverage/default/26.prim_present_test.1029244122 |
| /workspace/coverage/default/27.prim_present_test.2054820146 |
| /workspace/coverage/default/28.prim_present_test.2144477542 |
| /workspace/coverage/default/29.prim_present_test.2687516612 |
| /workspace/coverage/default/3.prim_present_test.474549881 |
| /workspace/coverage/default/30.prim_present_test.3505023526 |
| /workspace/coverage/default/31.prim_present_test.3159787661 |
| /workspace/coverage/default/32.prim_present_test.1228895417 |
| /workspace/coverage/default/33.prim_present_test.2260052467 |
| /workspace/coverage/default/34.prim_present_test.2479782648 |
| /workspace/coverage/default/35.prim_present_test.4289178193 |
| /workspace/coverage/default/36.prim_present_test.1805142594 |
| /workspace/coverage/default/37.prim_present_test.1772265192 |
| /workspace/coverage/default/38.prim_present_test.2216504420 |
| /workspace/coverage/default/39.prim_present_test.2370036083 |
| /workspace/coverage/default/4.prim_present_test.3013246711 |
| /workspace/coverage/default/40.prim_present_test.2358703095 |
| /workspace/coverage/default/41.prim_present_test.367332173 |
| /workspace/coverage/default/42.prim_present_test.2728931244 |
| /workspace/coverage/default/43.prim_present_test.2144361023 |
| /workspace/coverage/default/44.prim_present_test.472418268 |
| /workspace/coverage/default/45.prim_present_test.676707644 |
| /workspace/coverage/default/46.prim_present_test.1656860423 |
| /workspace/coverage/default/47.prim_present_test.1539973023 |
| /workspace/coverage/default/48.prim_present_test.3114642308 |
| /workspace/coverage/default/49.prim_present_test.3944002402 |
| /workspace/coverage/default/5.prim_present_test.1250159904 |
| /workspace/coverage/default/6.prim_present_test.1890935441 |
| /workspace/coverage/default/7.prim_present_test.1925419406 |
| /workspace/coverage/default/8.prim_present_test.2371263549 |
| /workspace/coverage/default/9.prim_present_test.1060270586 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/3.prim_present_test.474549881 | Jul 25 04:20:42 PM PDT 24 | Jul 25 04:21:20 PM PDT 24 | 5206760000 ps | ||
| T2 | /workspace/coverage/default/37.prim_present_test.1772265192 | Jul 25 04:24:12 PM PDT 24 | Jul 25 04:25:07 PM PDT 24 | 8889560000 ps | ||
| T3 | /workspace/coverage/default/35.prim_present_test.4289178193 | Jul 25 04:24:01 PM PDT 24 | Jul 25 04:24:40 PM PDT 24 | 6928500000 ps | ||
| T4 | /workspace/coverage/default/8.prim_present_test.2371263549 | Jul 25 04:20:42 PM PDT 24 | Jul 25 04:21:19 PM PDT 24 | 4764080000 ps | ||
| T5 | /workspace/coverage/default/26.prim_present_test.1029244122 | Jul 25 04:20:16 PM PDT 24 | Jul 25 04:21:11 PM PDT 24 | 9225600000 ps | ||
| T6 | /workspace/coverage/default/33.prim_present_test.2260052467 | Jul 25 04:20:32 PM PDT 24 | Jul 25 04:21:57 PM PDT 24 | 11633060000 ps | ||
| T7 | /workspace/coverage/default/2.prim_present_test.1140158314 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:20:27 PM PDT 24 | 8859800000 ps | ||
| T8 | /workspace/coverage/default/23.prim_present_test.1502466567 | Jul 25 04:21:09 PM PDT 24 | Jul 25 04:22:07 PM PDT 24 | 7604920000 ps | ||
| T9 | /workspace/coverage/default/24.prim_present_test.3954538772 | Jul 25 04:24:57 PM PDT 24 | Jul 25 04:26:00 PM PDT 24 | 11133340000 ps | ||
| T10 | /workspace/coverage/default/13.prim_present_test.4030803614 | Jul 25 04:20:44 PM PDT 24 | Jul 25 04:21:43 PM PDT 24 | 8566540000 ps | ||
| T11 | /workspace/coverage/default/18.prim_present_test.1192135838 | Jul 25 04:24:23 PM PDT 24 | Jul 25 04:24:47 PM PDT 24 | 3508580000 ps | ||
| T12 | /workspace/coverage/default/1.prim_present_test.993859066 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:20:30 PM PDT 24 | 8672560000 ps | ||
| T13 | /workspace/coverage/default/20.prim_present_test.3525061009 | Jul 25 04:20:44 PM PDT 24 | Jul 25 04:21:43 PM PDT 24 | 8396040000 ps | ||
| T14 | /workspace/coverage/default/31.prim_present_test.3159787661 | Jul 25 04:20:12 PM PDT 24 | Jul 25 04:20:37 PM PDT 24 | 3977300000 ps | ||
| T15 | /workspace/coverage/default/25.prim_present_test.4232565414 | Jul 25 04:24:58 PM PDT 24 | Jul 25 04:25:17 PM PDT 24 | 3299020000 ps | ||
| T16 | /workspace/coverage/default/40.prim_present_test.2358703095 | Jul 25 04:24:23 PM PDT 24 | Jul 25 04:25:46 PM PDT 24 | 15305940000 ps | ||
| T17 | /workspace/coverage/default/22.prim_present_test.1493512559 | Jul 25 04:24:58 PM PDT 24 | Jul 25 04:26:20 PM PDT 24 | 14542720000 ps | ||
| T18 | /workspace/coverage/default/16.prim_present_test.320092784 | Jul 25 04:24:24 PM PDT 24 | Jul 25 04:25:50 PM PDT 24 | 13357280000 ps | ||
| T19 | /workspace/coverage/default/6.prim_present_test.1890935441 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:21:04 PM PDT 24 | 14216600000 ps | ||
| T20 | /workspace/coverage/default/38.prim_present_test.2216504420 | Jul 25 04:24:12 PM PDT 24 | Jul 25 04:25:30 PM PDT 24 | 13402540000 ps | ||
| T21 | /workspace/coverage/default/45.prim_present_test.676707644 | Jul 25 04:20:23 PM PDT 24 | Jul 25 04:22:07 PM PDT 24 | 13526540000 ps | ||
| T22 | /workspace/coverage/default/41.prim_present_test.367332173 | Jul 25 04:21:10 PM PDT 24 | Jul 25 04:21:58 PM PDT 24 | 6774120000 ps | ||
| T23 | /workspace/coverage/default/9.prim_present_test.1060270586 | Jul 25 04:20:26 PM PDT 24 | Jul 25 04:21:36 PM PDT 24 | 10563560000 ps | ||
| T24 | /workspace/coverage/default/4.prim_present_test.3013246711 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:20:24 PM PDT 24 | 8803380000 ps | ||
| T25 | /workspace/coverage/default/7.prim_present_test.1925419406 | Jul 25 04:19:28 PM PDT 24 | Jul 25 04:20:59 PM PDT 24 | 13953720000 ps | ||
| T26 | /workspace/coverage/default/11.prim_present_test.4178889278 | Jul 25 04:19:59 PM PDT 24 | Jul 25 04:21:09 PM PDT 24 | 10669580000 ps | ||
| T27 | /workspace/coverage/default/42.prim_present_test.2728931244 | Jul 25 04:22:48 PM PDT 24 | Jul 25 04:23:37 PM PDT 24 | 6562080000 ps | ||
| T28 | /workspace/coverage/default/30.prim_present_test.3505023526 | Jul 25 04:24:02 PM PDT 24 | Jul 25 04:24:29 PM PDT 24 | 5076560000 ps | ||
| T29 | /workspace/coverage/default/32.prim_present_test.1228895417 | Jul 25 04:23:57 PM PDT 24 | Jul 25 04:24:54 PM PDT 24 | 9386180000 ps | ||
| T30 | /workspace/coverage/default/0.prim_present_test.1884574147 | Jul 25 04:19:30 PM PDT 24 | Jul 25 04:20:24 PM PDT 24 | 8343340000 ps | ||
| T31 | /workspace/coverage/default/34.prim_present_test.2479782648 | Jul 25 04:24:53 PM PDT 24 | Jul 25 04:26:06 PM PDT 24 | 14725000000 ps | ||
| T32 | /workspace/coverage/default/19.prim_present_test.1524292289 | Jul 25 04:20:44 PM PDT 24 | Jul 25 04:21:36 PM PDT 24 | 6864020000 ps | ||
| T33 | /workspace/coverage/default/27.prim_present_test.2054820146 | Jul 25 04:24:49 PM PDT 24 | Jul 25 04:25:53 PM PDT 24 | 11081260000 ps | ||
| T34 | /workspace/coverage/default/10.prim_present_test.321485383 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:20:01 PM PDT 24 | 4893040000 ps | ||
| T35 | /workspace/coverage/default/49.prim_present_test.3944002402 | Jul 25 04:24:13 PM PDT 24 | Jul 25 04:24:48 PM PDT 24 | 6554640000 ps | ||
| T36 | /workspace/coverage/default/43.prim_present_test.2144361023 | Jul 25 04:20:25 PM PDT 24 | Jul 25 04:22:08 PM PDT 24 | 14897360000 ps | ||
| T37 | /workspace/coverage/default/44.prim_present_test.472418268 | Jul 25 04:21:19 PM PDT 24 | Jul 25 04:21:43 PM PDT 24 | 3515400000 ps | ||
| T38 | /workspace/coverage/default/36.prim_present_test.1805142594 | Jul 25 04:24:31 PM PDT 24 | Jul 25 04:25:37 PM PDT 24 | 12332420000 ps | ||
| T39 | /workspace/coverage/default/39.prim_present_test.2370036083 | Jul 25 04:21:08 PM PDT 24 | Jul 25 04:22:05 PM PDT 24 | 8110840000 ps | ||
| T40 | /workspace/coverage/default/21.prim_present_test.2732439374 | Jul 25 04:20:44 PM PDT 24 | Jul 25 04:21:15 PM PDT 24 | 4430520000 ps | ||
| T41 | /workspace/coverage/default/46.prim_present_test.1656860423 | Jul 25 04:25:06 PM PDT 24 | Jul 25 04:26:12 PM PDT 24 | 10411040000 ps | ||
| T42 | /workspace/coverage/default/5.prim_present_test.1250159904 | Jul 25 04:19:28 PM PDT 24 | Jul 25 04:21:07 PM PDT 24 | 15093280000 ps | ||
| T43 | /workspace/coverage/default/12.prim_present_test.3207060117 | Jul 25 04:20:43 PM PDT 24 | Jul 25 04:21:34 PM PDT 24 | 7583220000 ps | ||
| T44 | /workspace/coverage/default/14.prim_present_test.1143315549 | Jul 25 04:20:07 PM PDT 24 | Jul 25 04:21:37 PM PDT 24 | 13499260000 ps | ||
| T45 | /workspace/coverage/default/17.prim_present_test.2028185176 | Jul 25 04:23:00 PM PDT 24 | Jul 25 04:23:34 PM PDT 24 | 4465860000 ps | ||
| T46 | /workspace/coverage/default/47.prim_present_test.1539973023 | Jul 25 04:24:30 PM PDT 24 | Jul 25 04:24:55 PM PDT 24 | 3971100000 ps | ||
| T47 | /workspace/coverage/default/15.prim_present_test.650594032 | Jul 25 04:20:28 PM PDT 24 | Jul 25 04:21:47 PM PDT 24 | 11130860000 ps | ||
| T48 | /workspace/coverage/default/29.prim_present_test.2687516612 | Jul 25 04:24:48 PM PDT 24 | Jul 25 04:25:46 PM PDT 24 | 9693700000 ps | ||
| T49 | /workspace/coverage/default/28.prim_present_test.2144477542 | Jul 25 04:24:23 PM PDT 24 | Jul 25 04:25:53 PM PDT 24 | 14362920000 ps | ||
| T50 | /workspace/coverage/default/48.prim_present_test.3114642308 | Jul 25 04:25:06 PM PDT 24 | Jul 25 04:26:16 PM PDT 24 | 10943620000 ps |
| Test location | /workspace/coverage/default/13.prim_present_test.4030803614 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8566540000 ps |
| CPU time | 31.18 seconds |
| Started | Jul 25 04:20:44 PM PDT 24 |
| Finished | Jul 25 04:21:43 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-d54f719b-d1e4-44f7-a5bb-c4c5279c1c8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030803614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.4030803614 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1884574147 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8343340000 ps |
| CPU time | 28.8 seconds |
| Started | Jul 25 04:19:30 PM PDT 24 |
| Finished | Jul 25 04:20:24 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-49b40f15-697d-44e8-98ec-1db904821772 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884574147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1884574147 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.993859066 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8672560000 ps |
| CPU time | 33.22 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:20:30 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-57fa7f4b-5f5b-47d2-a6f6-19df81d7cd98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993859066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.993859066 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.321485383 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4893040000 ps |
| CPU time | 18.37 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:20:01 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-f5687f89-6619-4a9f-ae35-a9a86abf04d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=321485383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.321485383 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.4178889278 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10669580000 ps |
| CPU time | 37.14 seconds |
| Started | Jul 25 04:19:59 PM PDT 24 |
| Finished | Jul 25 04:21:09 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-5ba8dae9-382d-4612-937c-e1be3187e035 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178889278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4178889278 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3207060117 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7583220000 ps |
| CPU time | 27.06 seconds |
| Started | Jul 25 04:20:43 PM PDT 24 |
| Finished | Jul 25 04:21:34 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-42cb4059-f824-4106-a153-d6814e373c08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207060117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3207060117 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1143315549 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13499260000 ps |
| CPU time | 47.02 seconds |
| Started | Jul 25 04:20:07 PM PDT 24 |
| Finished | Jul 25 04:21:37 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-91380d7a-bc53-4854-afdc-853929115b12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143315549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1143315549 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.650594032 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11130860000 ps |
| CPU time | 41.65 seconds |
| Started | Jul 25 04:20:28 PM PDT 24 |
| Finished | Jul 25 04:21:47 PM PDT 24 |
| Peak memory | 143628 kb |
| Host | smart-d40fbe2e-5c98-4e95-8cfa-b401928abb79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650594032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.650594032 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.320092784 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13357280000 ps |
| CPU time | 46.48 seconds |
| Started | Jul 25 04:24:24 PM PDT 24 |
| Finished | Jul 25 04:25:50 PM PDT 24 |
| Peak memory | 144596 kb |
| Host | smart-867edf42-714a-4d00-88c6-e785759fcace |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320092784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.320092784 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2028185176 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4465860000 ps |
| CPU time | 18.19 seconds |
| Started | Jul 25 04:23:00 PM PDT 24 |
| Finished | Jul 25 04:23:34 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-b67737ca-4285-4c7d-914c-bd3da5167a6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028185176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2028185176 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1192135838 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3508580000 ps |
| CPU time | 12.74 seconds |
| Started | Jul 25 04:24:23 PM PDT 24 |
| Finished | Jul 25 04:24:47 PM PDT 24 |
| Peak memory | 143940 kb |
| Host | smart-ea890bc7-503b-421c-8620-9e1e61587091 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192135838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1192135838 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1524292289 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6864020000 ps |
| CPU time | 27.83 seconds |
| Started | Jul 25 04:20:44 PM PDT 24 |
| Finished | Jul 25 04:21:36 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-9b9538c2-5bd2-4e9d-baa3-7f956c4e36d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524292289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1524292289 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1140158314 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8859800000 ps |
| CPU time | 31.82 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:20:27 PM PDT 24 |
| Peak memory | 144384 kb |
| Host | smart-d5dc3550-0ded-4f29-a861-0a817fe7ac41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1140158314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1140158314 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3525061009 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 8396040000 ps |
| CPU time | 31.4 seconds |
| Started | Jul 25 04:20:44 PM PDT 24 |
| Finished | Jul 25 04:21:43 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-2fe3810c-f15d-4bf4-8d6c-7209c5cb211c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3525061009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3525061009 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2732439374 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4430520000 ps |
| CPU time | 16.66 seconds |
| Started | Jul 25 04:20:44 PM PDT 24 |
| Finished | Jul 25 04:21:15 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-09020b6e-b325-4f38-86ad-cea86558af5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732439374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2732439374 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1493512559 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 14542720000 ps |
| CPU time | 44.94 seconds |
| Started | Jul 25 04:24:58 PM PDT 24 |
| Finished | Jul 25 04:26:20 PM PDT 24 |
| Peak memory | 144760 kb |
| Host | smart-8a35f055-05bc-468d-9e39-c0626c2a40e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493512559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1493512559 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1502466567 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7604920000 ps |
| CPU time | 30.8 seconds |
| Started | Jul 25 04:21:09 PM PDT 24 |
| Finished | Jul 25 04:22:07 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-55ecad69-a168-4660-b413-dc9560c71df3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502466567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1502466567 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3954538772 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11133340000 ps |
| CPU time | 33.8 seconds |
| Started | Jul 25 04:24:57 PM PDT 24 |
| Finished | Jul 25 04:26:00 PM PDT 24 |
| Peak memory | 144760 kb |
| Host | smart-31761c94-a31f-402f-bbcf-3e3bbf0983ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954538772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3954538772 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4232565414 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3299020000 ps |
| CPU time | 10.45 seconds |
| Started | Jul 25 04:24:58 PM PDT 24 |
| Finished | Jul 25 04:25:17 PM PDT 24 |
| Peak memory | 144612 kb |
| Host | smart-b976e9d7-0733-4853-a85a-08efa345059a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4232565414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4232565414 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1029244122 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 9225600000 ps |
| CPU time | 29.89 seconds |
| Started | Jul 25 04:20:16 PM PDT 24 |
| Finished | Jul 25 04:21:11 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-64a0eff9-6eb8-4106-ab2e-482109fccc34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1029244122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1029244122 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2054820146 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11081260000 ps |
| CPU time | 34.97 seconds |
| Started | Jul 25 04:24:49 PM PDT 24 |
| Finished | Jul 25 04:25:53 PM PDT 24 |
| Peak memory | 144004 kb |
| Host | smart-0045a2e9-15e5-42ae-9a5d-a6813c274e32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054820146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2054820146 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2144477542 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14362920000 ps |
| CPU time | 48.18 seconds |
| Started | Jul 25 04:24:23 PM PDT 24 |
| Finished | Jul 25 04:25:53 PM PDT 24 |
| Peak memory | 143648 kb |
| Host | smart-30bdceac-8597-467d-ad8e-a37c9fa19b38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144477542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2144477542 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2687516612 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9693700000 ps |
| CPU time | 31.28 seconds |
| Started | Jul 25 04:24:48 PM PDT 24 |
| Finished | Jul 25 04:25:46 PM PDT 24 |
| Peak memory | 143428 kb |
| Host | smart-8223b4dc-8b2e-4eca-ac26-f6f7adb60023 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687516612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2687516612 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.474549881 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5206760000 ps |
| CPU time | 20.24 seconds |
| Started | Jul 25 04:20:42 PM PDT 24 |
| Finished | Jul 25 04:21:20 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-26f25230-c59e-4d3c-bd6f-f51fbe976622 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474549881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.474549881 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3505023526 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5076560000 ps |
| CPU time | 15.27 seconds |
| Started | Jul 25 04:24:02 PM PDT 24 |
| Finished | Jul 25 04:24:29 PM PDT 24 |
| Peak memory | 144420 kb |
| Host | smart-608acb14-909f-4306-9955-fce02785f88f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3505023526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3505023526 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3159787661 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3977300000 ps |
| CPU time | 13.71 seconds |
| Started | Jul 25 04:20:12 PM PDT 24 |
| Finished | Jul 25 04:20:37 PM PDT 24 |
| Peak memory | 144860 kb |
| Host | smart-bab03a41-9c1f-486b-9ee6-ec5f02b43382 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159787661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3159787661 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1228895417 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9386180000 ps |
| CPU time | 30.18 seconds |
| Started | Jul 25 04:23:57 PM PDT 24 |
| Finished | Jul 25 04:24:54 PM PDT 24 |
| Peak memory | 144004 kb |
| Host | smart-59b8523b-a249-46b3-9332-84f7569b0cda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228895417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1228895417 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2260052467 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11633060000 ps |
| CPU time | 45.06 seconds |
| Started | Jul 25 04:20:32 PM PDT 24 |
| Finished | Jul 25 04:21:57 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-307028e1-4983-49dd-aa94-2c1f0c1a30b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260052467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2260052467 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2479782648 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14725000000 ps |
| CPU time | 39.67 seconds |
| Started | Jul 25 04:24:53 PM PDT 24 |
| Finished | Jul 25 04:26:06 PM PDT 24 |
| Peak memory | 144012 kb |
| Host | smart-0cbaa8a4-b8b6-4eb2-a041-7824700dbe40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479782648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2479782648 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4289178193 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6928500000 ps |
| CPU time | 20.94 seconds |
| Started | Jul 25 04:24:01 PM PDT 24 |
| Finished | Jul 25 04:24:40 PM PDT 24 |
| Peak memory | 143724 kb |
| Host | smart-396d28d8-200f-46ef-bfe4-d4f17546a1f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4289178193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4289178193 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1805142594 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12332420000 ps |
| CPU time | 35.9 seconds |
| Started | Jul 25 04:24:31 PM PDT 24 |
| Finished | Jul 25 04:25:37 PM PDT 24 |
| Peak memory | 144576 kb |
| Host | smart-12d6bf3b-28ef-4f24-8c3d-2ccfbfbf05c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805142594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1805142594 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1772265192 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8889560000 ps |
| CPU time | 29.55 seconds |
| Started | Jul 25 04:24:12 PM PDT 24 |
| Finished | Jul 25 04:25:07 PM PDT 24 |
| Peak memory | 143732 kb |
| Host | smart-2e294984-82f0-454b-af92-95d3a8dbf492 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772265192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1772265192 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2216504420 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 13402540000 ps |
| CPU time | 41.66 seconds |
| Started | Jul 25 04:24:12 PM PDT 24 |
| Finished | Jul 25 04:25:30 PM PDT 24 |
| Peak memory | 144064 kb |
| Host | smart-03a403c0-b480-48fb-bcf6-ea12144a04d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2216504420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2216504420 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2370036083 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8110840000 ps |
| CPU time | 29.52 seconds |
| Started | Jul 25 04:21:08 PM PDT 24 |
| Finished | Jul 25 04:22:05 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-05d11f12-a114-4978-ae07-b76d856c0d5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370036083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2370036083 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3013246711 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8803380000 ps |
| CPU time | 31.12 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:20:24 PM PDT 24 |
| Peak memory | 144860 kb |
| Host | smart-96b32dbd-f240-4d18-8a6c-187ef60a495a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013246711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3013246711 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2358703095 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 15305940000 ps |
| CPU time | 44.93 seconds |
| Started | Jul 25 04:24:23 PM PDT 24 |
| Finished | Jul 25 04:25:46 PM PDT 24 |
| Peak memory | 143800 kb |
| Host | smart-cee79158-023d-4271-8a3e-180c611cb6dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2358703095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2358703095 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.367332173 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6774120000 ps |
| CPU time | 25.33 seconds |
| Started | Jul 25 04:21:10 PM PDT 24 |
| Finished | Jul 25 04:21:58 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-26fd1581-dd49-4e2a-8c90-b4681fbfbb19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=367332173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.367332173 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2728931244 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6562080000 ps |
| CPU time | 25.58 seconds |
| Started | Jul 25 04:22:48 PM PDT 24 |
| Finished | Jul 25 04:23:37 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-d6122081-18b5-48dd-9a34-0449553c3d3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728931244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2728931244 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2144361023 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14897360000 ps |
| CPU time | 54.41 seconds |
| Started | Jul 25 04:20:25 PM PDT 24 |
| Finished | Jul 25 04:22:08 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-f3b3d1a5-f824-4f39-aede-d171cfd84218 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144361023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2144361023 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.472418268 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3515400000 ps |
| CPU time | 12.41 seconds |
| Started | Jul 25 04:21:19 PM PDT 24 |
| Finished | Jul 25 04:21:43 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-6a49f562-9c84-47b7-b1e6-233b5a7c0ff7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472418268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.472418268 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.676707644 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13526540000 ps |
| CPU time | 54.65 seconds |
| Started | Jul 25 04:20:23 PM PDT 24 |
| Finished | Jul 25 04:22:07 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-373f32c4-2e7d-44a5-b162-4328a8aa31f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676707644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.676707644 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1656860423 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10411040000 ps |
| CPU time | 34.69 seconds |
| Started | Jul 25 04:25:06 PM PDT 24 |
| Finished | Jul 25 04:26:12 PM PDT 24 |
| Peak memory | 144404 kb |
| Host | smart-05ff9e50-1d36-4d2e-abb8-9b504d107ce2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1656860423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1656860423 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1539973023 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3971100000 ps |
| CPU time | 13.45 seconds |
| Started | Jul 25 04:24:30 PM PDT 24 |
| Finished | Jul 25 04:24:55 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-5e0613fc-8b01-472e-981f-e146b799301a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539973023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1539973023 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3114642308 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10943620000 ps |
| CPU time | 36.55 seconds |
| Started | Jul 25 04:25:06 PM PDT 24 |
| Finished | Jul 25 04:26:16 PM PDT 24 |
| Peak memory | 143940 kb |
| Host | smart-ccd7f561-5cb8-4b82-a772-265415a9a05c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114642308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3114642308 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3944002402 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6554640000 ps |
| CPU time | 18.98 seconds |
| Started | Jul 25 04:24:13 PM PDT 24 |
| Finished | Jul 25 04:24:48 PM PDT 24 |
| Peak memory | 144032 kb |
| Host | smart-d3d83fa7-0805-4cd8-ada0-0619c50b8377 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944002402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3944002402 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1250159904 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 15093280000 ps |
| CPU time | 52.94 seconds |
| Started | Jul 25 04:19:28 PM PDT 24 |
| Finished | Jul 25 04:21:07 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-ba2186f7-43ba-4a9c-a004-560f9e7b750f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250159904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1250159904 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1890935441 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14216600000 ps |
| CPU time | 51.79 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:21:04 PM PDT 24 |
| Peak memory | 144448 kb |
| Host | smart-ba08fc64-60cc-4cce-8998-320297ef938a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1890935441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1890935441 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1925419406 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13953720000 ps |
| CPU time | 48.98 seconds |
| Started | Jul 25 04:19:28 PM PDT 24 |
| Finished | Jul 25 04:20:59 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-a1072845-3e77-4d06-816d-6af08ba4e5a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925419406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1925419406 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2371263549 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4764080000 ps |
| CPU time | 19.14 seconds |
| Started | Jul 25 04:20:42 PM PDT 24 |
| Finished | Jul 25 04:21:19 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-d3cf6c49-b994-4f1c-925f-b12554b429db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2371263549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2371263549 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1060270586 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10563560000 ps |
| CPU time | 37.8 seconds |
| Started | Jul 25 04:20:26 PM PDT 24 |
| Finished | Jul 25 04:21:36 PM PDT 24 |
| Peak memory | 143588 kb |
| Host | smart-c309b395-246f-4057-aa18-7800557a81d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060270586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1060270586 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |