| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.3200489805 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.78770647 |
| /workspace/coverage/default/10.prim_present_test.1382350032 |
| /workspace/coverage/default/11.prim_present_test.548451567 |
| /workspace/coverage/default/12.prim_present_test.3475153882 |
| /workspace/coverage/default/13.prim_present_test.381640452 |
| /workspace/coverage/default/14.prim_present_test.2521715947 |
| /workspace/coverage/default/15.prim_present_test.3312470909 |
| /workspace/coverage/default/16.prim_present_test.2604759423 |
| /workspace/coverage/default/17.prim_present_test.3611211749 |
| /workspace/coverage/default/18.prim_present_test.977917017 |
| /workspace/coverage/default/19.prim_present_test.2003032515 |
| /workspace/coverage/default/2.prim_present_test.2181962998 |
| /workspace/coverage/default/20.prim_present_test.3569731324 |
| /workspace/coverage/default/21.prim_present_test.1345273954 |
| /workspace/coverage/default/22.prim_present_test.660770799 |
| /workspace/coverage/default/23.prim_present_test.868559813 |
| /workspace/coverage/default/24.prim_present_test.3607527962 |
| /workspace/coverage/default/25.prim_present_test.1908422690 |
| /workspace/coverage/default/26.prim_present_test.1384290467 |
| /workspace/coverage/default/27.prim_present_test.1587771770 |
| /workspace/coverage/default/28.prim_present_test.3287815784 |
| /workspace/coverage/default/29.prim_present_test.3283529378 |
| /workspace/coverage/default/3.prim_present_test.3393623877 |
| /workspace/coverage/default/30.prim_present_test.3431712064 |
| /workspace/coverage/default/31.prim_present_test.1809553903 |
| /workspace/coverage/default/32.prim_present_test.1354232307 |
| /workspace/coverage/default/33.prim_present_test.3875610082 |
| /workspace/coverage/default/34.prim_present_test.25116623 |
| /workspace/coverage/default/35.prim_present_test.188803871 |
| /workspace/coverage/default/36.prim_present_test.589920829 |
| /workspace/coverage/default/37.prim_present_test.210611367 |
| /workspace/coverage/default/38.prim_present_test.730979462 |
| /workspace/coverage/default/39.prim_present_test.3548253684 |
| /workspace/coverage/default/4.prim_present_test.3264218902 |
| /workspace/coverage/default/40.prim_present_test.3469971458 |
| /workspace/coverage/default/41.prim_present_test.1494124666 |
| /workspace/coverage/default/42.prim_present_test.2623189350 |
| /workspace/coverage/default/43.prim_present_test.2308999475 |
| /workspace/coverage/default/44.prim_present_test.3486093799 |
| /workspace/coverage/default/45.prim_present_test.2789122365 |
| /workspace/coverage/default/46.prim_present_test.2317073385 |
| /workspace/coverage/default/47.prim_present_test.3119314565 |
| /workspace/coverage/default/48.prim_present_test.559253164 |
| /workspace/coverage/default/49.prim_present_test.2725160476 |
| /workspace/coverage/default/5.prim_present_test.2420332483 |
| /workspace/coverage/default/6.prim_present_test.123370602 |
| /workspace/coverage/default/7.prim_present_test.2952870956 |
| /workspace/coverage/default/8.prim_present_test.4220162688 |
| /workspace/coverage/default/9.prim_present_test.2744440121 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/20.prim_present_test.3569731324 | Jul 26 04:22:21 PM PDT 24 | Jul 26 04:23:27 PM PDT 24 | 10114060000 ps | ||
| T2 | /workspace/coverage/default/4.prim_present_test.3264218902 | Jul 26 04:20:56 PM PDT 24 | Jul 26 04:22:01 PM PDT 24 | 8922420000 ps | ||
| T3 | /workspace/coverage/default/34.prim_present_test.25116623 | Jul 26 04:27:48 PM PDT 24 | Jul 26 04:28:32 PM PDT 24 | 6117540000 ps | ||
| T4 | /workspace/coverage/default/37.prim_present_test.210611367 | Jul 26 04:27:52 PM PDT 24 | Jul 26 04:28:51 PM PDT 24 | 10974620000 ps | ||
| T5 | /workspace/coverage/default/11.prim_present_test.548451567 | Jul 26 04:24:19 PM PDT 24 | Jul 26 04:25:29 PM PDT 24 | 10340980000 ps | ||
| T6 | /workspace/coverage/default/14.prim_present_test.2521715947 | Jul 26 04:24:35 PM PDT 24 | Jul 26 04:25:27 PM PDT 24 | 7570200000 ps | ||
| T7 | /workspace/coverage/default/49.prim_present_test.2725160476 | Jul 26 04:27:48 PM PDT 24 | Jul 26 04:29:25 PM PDT 24 | 13935120000 ps | ||
| T8 | /workspace/coverage/default/1.prim_present_test.3200489805 | Jul 26 04:25:52 PM PDT 24 | Jul 26 04:27:04 PM PDT 24 | 11835800000 ps | ||
| T9 | /workspace/coverage/default/25.prim_present_test.1908422690 | Jul 26 04:21:40 PM PDT 24 | Jul 26 04:23:27 PM PDT 24 | 12238800000 ps | ||
| T10 | /workspace/coverage/default/31.prim_present_test.1809553903 | Jul 26 04:27:48 PM PDT 24 | Jul 26 04:28:27 PM PDT 24 | 6541000000 ps | ||
| T11 | /workspace/coverage/default/46.prim_present_test.2317073385 | Jul 26 04:27:50 PM PDT 24 | Jul 26 04:29:23 PM PDT 24 | 14129800000 ps | ||
| T12 | /workspace/coverage/default/27.prim_present_test.1587771770 | Jul 26 04:24:38 PM PDT 24 | Jul 26 04:25:02 PM PDT 24 | 3493080000 ps | ||
| T13 | /workspace/coverage/default/7.prim_present_test.2952870956 | Jul 26 04:24:06 PM PDT 24 | Jul 26 04:24:52 PM PDT 24 | 6655700000 ps | ||
| T14 | /workspace/coverage/default/0.prim_present_test.78770647 | Jul 26 04:25:55 PM PDT 24 | Jul 26 04:26:57 PM PDT 24 | 10332300000 ps | ||
| T15 | /workspace/coverage/default/30.prim_present_test.3431712064 | Jul 26 04:27:54 PM PDT 24 | Jul 26 04:28:20 PM PDT 24 | 4022560000 ps | ||
| T16 | /workspace/coverage/default/17.prim_present_test.3611211749 | Jul 26 04:24:55 PM PDT 24 | Jul 26 04:25:29 PM PDT 24 | 5937740000 ps | ||
| T17 | /workspace/coverage/default/3.prim_present_test.3393623877 | Jul 26 04:25:25 PM PDT 24 | Jul 26 04:26:48 PM PDT 24 | 12475020000 ps | ||
| T18 | /workspace/coverage/default/29.prim_present_test.3283529378 | Jul 26 04:22:52 PM PDT 24 | Jul 26 04:24:49 PM PDT 24 | 15473960000 ps | ||
| T19 | /workspace/coverage/default/38.prim_present_test.730979462 | Jul 26 04:27:48 PM PDT 24 | Jul 26 04:28:16 PM PDT 24 | 4180660000 ps | ||
| T20 | /workspace/coverage/default/5.prim_present_test.2420332483 | Jul 26 04:26:07 PM PDT 24 | Jul 26 04:26:46 PM PDT 24 | 6456680000 ps | ||
| T21 | /workspace/coverage/default/15.prim_present_test.3312470909 | Jul 26 04:22:00 PM PDT 24 | Jul 26 04:22:41 PM PDT 24 | 6354380000 ps | ||
| T22 | /workspace/coverage/default/42.prim_present_test.2623189350 | Jul 26 04:27:58 PM PDT 24 | Jul 26 04:29:19 PM PDT 24 | 13589160000 ps | ||
| T23 | /workspace/coverage/default/9.prim_present_test.2744440121 | Jul 26 04:25:05 PM PDT 24 | Jul 26 04:26:18 PM PDT 24 | 11832080000 ps | ||
| T24 | /workspace/coverage/default/16.prim_present_test.2604759423 | Jul 26 04:24:19 PM PDT 24 | Jul 26 04:25:32 PM PDT 24 | 10947960000 ps | ||
| T25 | /workspace/coverage/default/47.prim_present_test.3119314565 | Jul 26 04:27:47 PM PDT 24 | Jul 26 04:28:17 PM PDT 24 | 4649380000 ps | ||
| T26 | /workspace/coverage/default/43.prim_present_test.2308999475 | Jul 26 04:27:51 PM PDT 24 | Jul 26 04:29:01 PM PDT 24 | 12237560000 ps | ||
| T27 | /workspace/coverage/default/18.prim_present_test.977917017 | Jul 26 04:20:36 PM PDT 24 | Jul 26 04:21:34 PM PDT 24 | 8624820000 ps | ||
| T28 | /workspace/coverage/default/35.prim_present_test.188803871 | Jul 26 04:27:54 PM PDT 24 | Jul 26 04:28:46 PM PDT 24 | 8247240000 ps | ||
| T29 | /workspace/coverage/default/39.prim_present_test.3548253684 | Jul 26 04:27:48 PM PDT 24 | Jul 26 04:28:27 PM PDT 24 | 6571380000 ps | ||
| T30 | /workspace/coverage/default/21.prim_present_test.1345273954 | Jul 26 04:24:32 PM PDT 24 | Jul 26 04:26:05 PM PDT 24 | 12683960000 ps | ||
| T31 | /workspace/coverage/default/32.prim_present_test.1354232307 | Jul 26 04:27:49 PM PDT 24 | Jul 26 04:28:43 PM PDT 24 | 8406580000 ps | ||
| T32 | /workspace/coverage/default/40.prim_present_test.3469971458 | Jul 26 04:27:47 PM PDT 24 | Jul 26 04:28:33 PM PDT 24 | 8977600000 ps | ||
| T33 | /workspace/coverage/default/36.prim_present_test.589920829 | Jul 26 04:27:55 PM PDT 24 | Jul 26 04:28:53 PM PDT 24 | 9141900000 ps | ||
| T34 | /workspace/coverage/default/19.prim_present_test.2003032515 | Jul 26 04:25:09 PM PDT 24 | Jul 26 04:25:46 PM PDT 24 | 7179600000 ps | ||
| T35 | /workspace/coverage/default/10.prim_present_test.1382350032 | Jul 26 04:24:19 PM PDT 24 | Jul 26 04:25:49 PM PDT 24 | 14036180000 ps | ||
| T36 | /workspace/coverage/default/12.prim_present_test.3475153882 | Jul 26 04:24:20 PM PDT 24 | Jul 26 04:25:35 PM PDT 24 | 11731640000 ps | ||
| T37 | /workspace/coverage/default/44.prim_present_test.3486093799 | Jul 26 04:27:46 PM PDT 24 | Jul 26 04:29:25 PM PDT 24 | 12105500000 ps | ||
| T38 | /workspace/coverage/default/26.prim_present_test.1384290467 | Jul 26 04:24:27 PM PDT 24 | Jul 26 04:24:58 PM PDT 24 | 4666120000 ps | ||
| T39 | /workspace/coverage/default/41.prim_present_test.1494124666 | Jul 26 04:27:45 PM PDT 24 | Jul 26 04:28:49 PM PDT 24 | 9812740000 ps | ||
| T40 | /workspace/coverage/default/23.prim_present_test.868559813 | Jul 26 04:24:33 PM PDT 24 | Jul 26 04:25:54 PM PDT 24 | 11456360000 ps | ||
| T41 | /workspace/coverage/default/28.prim_present_test.3287815784 | Jul 26 04:27:51 PM PDT 24 | Jul 26 04:29:24 PM PDT 24 | 15454740000 ps | ||
| T42 | /workspace/coverage/default/6.prim_present_test.123370602 | Jul 26 04:20:55 PM PDT 24 | Jul 26 04:21:26 PM PDT 24 | 3906620000 ps | ||
| T43 | /workspace/coverage/default/13.prim_present_test.381640452 | Jul 26 04:26:18 PM PDT 24 | Jul 26 04:27:45 PM PDT 24 | 13808020000 ps | ||
| T44 | /workspace/coverage/default/48.prim_present_test.559253164 | Jul 26 04:27:57 PM PDT 24 | Jul 26 04:28:54 PM PDT 24 | 8592580000 ps | ||
| T45 | /workspace/coverage/default/24.prim_present_test.3607527962 | Jul 26 04:24:41 PM PDT 24 | Jul 26 04:25:46 PM PDT 24 | 11297020000 ps | ||
| T46 | /workspace/coverage/default/22.prim_present_test.660770799 | Jul 26 04:25:07 PM PDT 24 | Jul 26 04:25:59 PM PDT 24 | 9371300000 ps | ||
| T47 | /workspace/coverage/default/45.prim_present_test.2789122365 | Jul 26 04:27:49 PM PDT 24 | Jul 26 04:28:39 PM PDT 24 | 7742560000 ps | ||
| T48 | /workspace/coverage/default/2.prim_present_test.2181962998 | Jul 26 04:22:48 PM PDT 24 | Jul 26 04:24:26 PM PDT 24 | 14098180000 ps | ||
| T49 | /workspace/coverage/default/8.prim_present_test.4220162688 | Jul 26 04:24:57 PM PDT 24 | Jul 26 04:25:26 PM PDT 24 | 4810580000 ps | ||
| T50 | /workspace/coverage/default/33.prim_present_test.3875610082 | Jul 26 04:27:48 PM PDT 24 | Jul 26 04:28:15 PM PDT 24 | 4594200000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.3200489805 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11835800000 ps |
| CPU time | 39.6 seconds |
| Started | Jul 26 04:25:52 PM PDT 24 |
| Finished | Jul 26 04:27:04 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-ebdc69d5-1b25-454e-b246-f3eae13d25cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200489805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3200489805 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.78770647 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10332300000 ps |
| CPU time | 33.71 seconds |
| Started | Jul 26 04:25:55 PM PDT 24 |
| Finished | Jul 26 04:26:57 PM PDT 24 |
| Peak memory | 144056 kb |
| Host | smart-c87359a5-affe-402d-b487-ca1d8a141022 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78770647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.78770647 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1382350032 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14036180000 ps |
| CPU time | 47.78 seconds |
| Started | Jul 26 04:24:19 PM PDT 24 |
| Finished | Jul 26 04:25:49 PM PDT 24 |
| Peak memory | 144400 kb |
| Host | smart-cdd116a1-c646-4ce2-a6d9-ebe3e003e29f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382350032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1382350032 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.548451567 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 10340980000 ps |
| CPU time | 36.82 seconds |
| Started | Jul 26 04:24:19 PM PDT 24 |
| Finished | Jul 26 04:25:29 PM PDT 24 |
| Peak memory | 143448 kb |
| Host | smart-2a121137-a4a5-4d75-b5d5-6d37ac5ac85f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548451567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.548451567 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3475153882 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11731640000 ps |
| CPU time | 39.82 seconds |
| Started | Jul 26 04:24:20 PM PDT 24 |
| Finished | Jul 26 04:25:35 PM PDT 24 |
| Peak memory | 144712 kb |
| Host | smart-d016581a-ec62-4165-94b7-b46541a28581 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475153882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3475153882 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.381640452 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13808020000 ps |
| CPU time | 47.24 seconds |
| Started | Jul 26 04:26:18 PM PDT 24 |
| Finished | Jul 26 04:27:45 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-01e7fe9c-68c6-4ac0-b7f8-147b00a3cb21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381640452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.381640452 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2521715947 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7570200000 ps |
| CPU time | 27.43 seconds |
| Started | Jul 26 04:24:35 PM PDT 24 |
| Finished | Jul 26 04:25:27 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-460a4478-0aaf-4d02-88d8-d51d42d0ceb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521715947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2521715947 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3312470909 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 6354380000 ps |
| CPU time | 21.71 seconds |
| Started | Jul 26 04:22:00 PM PDT 24 |
| Finished | Jul 26 04:22:41 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-a91ed166-f04f-4d7f-91b1-272b6c6040f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3312470909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3312470909 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2604759423 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10947960000 ps |
| CPU time | 38.38 seconds |
| Started | Jul 26 04:24:19 PM PDT 24 |
| Finished | Jul 26 04:25:32 PM PDT 24 |
| Peak memory | 143488 kb |
| Host | smart-04fb5f21-3e7a-4cfd-9528-5c484649de4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604759423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2604759423 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3611211749 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5937740000 ps |
| CPU time | 18.35 seconds |
| Started | Jul 26 04:24:55 PM PDT 24 |
| Finished | Jul 26 04:25:29 PM PDT 24 |
| Peak memory | 144556 kb |
| Host | smart-497b8655-c5bf-45d3-adbb-b899ce6b7b99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611211749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3611211749 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.977917017 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8624820000 ps |
| CPU time | 30.96 seconds |
| Started | Jul 26 04:20:36 PM PDT 24 |
| Finished | Jul 26 04:21:34 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-98df4641-42ef-4f88-82d7-b4abfe069565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977917017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.977917017 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2003032515 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7179600000 ps |
| CPU time | 20.66 seconds |
| Started | Jul 26 04:25:09 PM PDT 24 |
| Finished | Jul 26 04:25:46 PM PDT 24 |
| Peak memory | 144040 kb |
| Host | smart-34dc7273-7d99-4c5c-8bb5-a5c866b504e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003032515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2003032515 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2181962998 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14098180000 ps |
| CPU time | 52.08 seconds |
| Started | Jul 26 04:22:48 PM PDT 24 |
| Finished | Jul 26 04:24:26 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-f6ae198b-f87f-4488-a3c7-66a516a8b9a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181962998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2181962998 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3569731324 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10114060000 ps |
| CPU time | 35.45 seconds |
| Started | Jul 26 04:22:21 PM PDT 24 |
| Finished | Jul 26 04:23:27 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-46cbdc6d-748a-4925-b35b-7967abce57be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569731324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3569731324 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1345273954 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 12683960000 ps |
| CPU time | 48.89 seconds |
| Started | Jul 26 04:24:32 PM PDT 24 |
| Finished | Jul 26 04:26:05 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-2e2d4edd-dc9a-43c2-8a1b-f2acabd696d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345273954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1345273954 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.660770799 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9371300000 ps |
| CPU time | 28.23 seconds |
| Started | Jul 26 04:25:07 PM PDT 24 |
| Finished | Jul 26 04:25:59 PM PDT 24 |
| Peak memory | 144032 kb |
| Host | smart-2e7a2916-4f43-412c-9a52-ac31c57c6ce0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660770799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.660770799 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.868559813 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11456360000 ps |
| CPU time | 42.58 seconds |
| Started | Jul 26 04:24:33 PM PDT 24 |
| Finished | Jul 26 04:25:54 PM PDT 24 |
| Peak memory | 144788 kb |
| Host | smart-6717a8ef-2892-4352-b27a-2eb2ae76c679 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868559813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.868559813 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3607527962 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11297020000 ps |
| CPU time | 35.93 seconds |
| Started | Jul 26 04:24:41 PM PDT 24 |
| Finished | Jul 26 04:25:46 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-06304ace-bdbc-4ded-a63b-4fe9c06f6e33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607527962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3607527962 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1908422690 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12238800000 ps |
| CPU time | 53.88 seconds |
| Started | Jul 26 04:21:40 PM PDT 24 |
| Finished | Jul 26 04:23:27 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-9e6f0d4a-5acb-402d-be55-4a450a57ef26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908422690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1908422690 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1384290467 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4666120000 ps |
| CPU time | 16.2 seconds |
| Started | Jul 26 04:24:27 PM PDT 24 |
| Finished | Jul 26 04:24:58 PM PDT 24 |
| Peak memory | 143788 kb |
| Host | smart-2ebcbfb1-f31f-49ec-ae4b-c046d56fbe72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384290467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1384290467 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1587771770 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3493080000 ps |
| CPU time | 12.74 seconds |
| Started | Jul 26 04:24:38 PM PDT 24 |
| Finished | Jul 26 04:25:02 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-4846c780-ff04-4431-9cc8-6acbea18cb02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587771770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1587771770 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3287815784 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 15454740000 ps |
| CPU time | 50.15 seconds |
| Started | Jul 26 04:27:51 PM PDT 24 |
| Finished | Jul 26 04:29:24 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-d0a768a8-615c-4278-8752-6c6b24b620c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287815784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3287815784 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3283529378 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 15473960000 ps |
| CPU time | 61.38 seconds |
| Started | Jul 26 04:22:52 PM PDT 24 |
| Finished | Jul 26 04:24:49 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-e70fc543-a59d-4eea-8e45-788dd94047a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283529378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3283529378 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3393623877 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12475020000 ps |
| CPU time | 43.64 seconds |
| Started | Jul 26 04:25:25 PM PDT 24 |
| Finished | Jul 26 04:26:48 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-099b2b17-4500-4dfd-8e36-a1f111135827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393623877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3393623877 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3431712064 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4022560000 ps |
| CPU time | 14.17 seconds |
| Started | Jul 26 04:27:54 PM PDT 24 |
| Finished | Jul 26 04:28:20 PM PDT 24 |
| Peak memory | 144700 kb |
| Host | smart-5c155216-4312-4a20-bb91-3e6574f0c5ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431712064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3431712064 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1809553903 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6541000000 ps |
| CPU time | 21.11 seconds |
| Started | Jul 26 04:27:48 PM PDT 24 |
| Finished | Jul 26 04:28:27 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-274a3373-7bbf-4af7-8201-7d830ed6ab81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809553903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1809553903 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1354232307 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8406580000 ps |
| CPU time | 29.26 seconds |
| Started | Jul 26 04:27:49 PM PDT 24 |
| Finished | Jul 26 04:28:43 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-a90bb6ab-a48e-4ddc-91cd-e405a7ce0ade |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354232307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1354232307 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3875610082 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4594200000 ps |
| CPU time | 14.53 seconds |
| Started | Jul 26 04:27:48 PM PDT 24 |
| Finished | Jul 26 04:28:15 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-e8fe8fe1-8f1d-4e27-bbf0-1437bf2b3854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875610082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3875610082 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.25116623 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6117540000 ps |
| CPU time | 23.62 seconds |
| Started | Jul 26 04:27:48 PM PDT 24 |
| Finished | Jul 26 04:28:32 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-ef99bcd8-d704-4054-9601-45ab994a7c41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25116623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.25116623 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.188803871 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8247240000 ps |
| CPU time | 27.77 seconds |
| Started | Jul 26 04:27:54 PM PDT 24 |
| Finished | Jul 26 04:28:46 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-27754194-33cf-4017-a8cc-63d70d462f85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=188803871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.188803871 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.589920829 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9141900000 ps |
| CPU time | 31.24 seconds |
| Started | Jul 26 04:27:55 PM PDT 24 |
| Finished | Jul 26 04:28:53 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-d4900e0d-504f-4072-8f31-156a8e6e699a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=589920829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.589920829 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.210611367 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10974620000 ps |
| CPU time | 32.51 seconds |
| Started | Jul 26 04:27:52 PM PDT 24 |
| Finished | Jul 26 04:28:51 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-5064c370-0d6f-4d06-a6ea-1f62869128d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210611367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.210611367 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.730979462 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4180660000 ps |
| CPU time | 14.99 seconds |
| Started | Jul 26 04:27:48 PM PDT 24 |
| Finished | Jul 26 04:28:16 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-716f1606-989c-4081-96e2-82fd9c38cad3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=730979462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.730979462 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3548253684 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6571380000 ps |
| CPU time | 21.1 seconds |
| Started | Jul 26 04:27:48 PM PDT 24 |
| Finished | Jul 26 04:28:27 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-55aad6d2-9511-4752-810d-82e4165c586f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548253684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3548253684 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3264218902 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8922420000 ps |
| CPU time | 34.15 seconds |
| Started | Jul 26 04:20:56 PM PDT 24 |
| Finished | Jul 26 04:22:01 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-cea31250-670e-4df1-bcfc-0bedc9fc43cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3264218902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3264218902 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3469971458 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8977600000 ps |
| CPU time | 25.72 seconds |
| Started | Jul 26 04:27:47 PM PDT 24 |
| Finished | Jul 26 04:28:33 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-b32983c8-84e6-4a57-8276-383838527ed9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469971458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3469971458 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1494124666 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9812740000 ps |
| CPU time | 34.47 seconds |
| Started | Jul 26 04:27:45 PM PDT 24 |
| Finished | Jul 26 04:28:49 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-288730b4-512f-44be-81df-820d0d99f578 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1494124666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1494124666 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2623189350 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13589160000 ps |
| CPU time | 43.58 seconds |
| Started | Jul 26 04:27:58 PM PDT 24 |
| Finished | Jul 26 04:29:19 PM PDT 24 |
| Peak memory | 144856 kb |
| Host | smart-0f04f41f-77a4-473a-a8f3-07b0ec787e79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623189350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2623189350 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2308999475 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12237560000 ps |
| CPU time | 37.81 seconds |
| Started | Jul 26 04:27:51 PM PDT 24 |
| Finished | Jul 26 04:29:01 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-f1fe492b-c660-4b0b-9f27-981af961cd24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2308999475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2308999475 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3486093799 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12105500000 ps |
| CPU time | 50.77 seconds |
| Started | Jul 26 04:27:46 PM PDT 24 |
| Finished | Jul 26 04:29:25 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-3705eb36-0387-4bf6-b064-8e063e3ab631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486093799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3486093799 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2789122365 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7742560000 ps |
| CPU time | 27 seconds |
| Started | Jul 26 04:27:49 PM PDT 24 |
| Finished | Jul 26 04:28:39 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-f202ac1b-60e3-4a62-86f4-35286d13463b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789122365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2789122365 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2317073385 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14129800000 ps |
| CPU time | 49.13 seconds |
| Started | Jul 26 04:27:50 PM PDT 24 |
| Finished | Jul 26 04:29:23 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-428cbd17-72fb-4b11-bb91-e880a17cfee0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317073385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2317073385 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3119314565 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4649380000 ps |
| CPU time | 15.88 seconds |
| Started | Jul 26 04:27:47 PM PDT 24 |
| Finished | Jul 26 04:28:17 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-6770aa84-05a2-4895-a01d-dc28d4e5fe50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119314565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3119314565 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.559253164 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8592580000 ps |
| CPU time | 30.67 seconds |
| Started | Jul 26 04:27:57 PM PDT 24 |
| Finished | Jul 26 04:28:54 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-ccf4088c-c93c-4738-823b-43f33552fa87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559253164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.559253164 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2725160476 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13935120000 ps |
| CPU time | 50.86 seconds |
| Started | Jul 26 04:27:48 PM PDT 24 |
| Finished | Jul 26 04:29:25 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-75cb1533-87bf-442c-899e-2838f4619057 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725160476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2725160476 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2420332483 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6456680000 ps |
| CPU time | 21.33 seconds |
| Started | Jul 26 04:26:07 PM PDT 24 |
| Finished | Jul 26 04:26:46 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-2478fa13-7482-4feb-bba0-1e45c9ec9b68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2420332483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2420332483 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.123370602 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3906620000 ps |
| CPU time | 16.26 seconds |
| Started | Jul 26 04:20:55 PM PDT 24 |
| Finished | Jul 26 04:21:26 PM PDT 24 |
| Peak memory | 144856 kb |
| Host | smart-1c2212e0-25bf-41ef-9275-81725e6df61a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123370602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.123370602 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2952870956 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6655700000 ps |
| CPU time | 24.04 seconds |
| Started | Jul 26 04:24:06 PM PDT 24 |
| Finished | Jul 26 04:24:52 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-90ff189b-5238-4957-a6c4-76e707d84392 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952870956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2952870956 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4220162688 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4810580000 ps |
| CPU time | 15.48 seconds |
| Started | Jul 26 04:24:57 PM PDT 24 |
| Finished | Jul 26 04:25:26 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-153a43c8-9f00-41a4-959e-2d25bbba6463 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220162688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4220162688 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2744440121 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11832080000 ps |
| CPU time | 38.9 seconds |
| Started | Jul 26 04:25:05 PM PDT 24 |
| Finished | Jul 26 04:26:18 PM PDT 24 |
| Peak memory | 144796 kb |
| Host | smart-83e2ebe1-da80-4c3b-bf17-354df75e2051 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744440121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2744440121 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |