| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.2931720310 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.315572155 |
| /workspace/coverage/default/1.prim_present_test.2828388415 |
| /workspace/coverage/default/10.prim_present_test.2074872994 |
| /workspace/coverage/default/12.prim_present_test.3549305682 |
| /workspace/coverage/default/13.prim_present_test.192091621 |
| /workspace/coverage/default/14.prim_present_test.513213809 |
| /workspace/coverage/default/15.prim_present_test.658899919 |
| /workspace/coverage/default/16.prim_present_test.4158327569 |
| /workspace/coverage/default/17.prim_present_test.877353426 |
| /workspace/coverage/default/18.prim_present_test.2142984404 |
| /workspace/coverage/default/19.prim_present_test.1057655856 |
| /workspace/coverage/default/2.prim_present_test.2076623556 |
| /workspace/coverage/default/20.prim_present_test.2062066499 |
| /workspace/coverage/default/21.prim_present_test.3352645600 |
| /workspace/coverage/default/22.prim_present_test.1559149529 |
| /workspace/coverage/default/23.prim_present_test.4178437977 |
| /workspace/coverage/default/24.prim_present_test.3940498276 |
| /workspace/coverage/default/25.prim_present_test.66993822 |
| /workspace/coverage/default/26.prim_present_test.994703866 |
| /workspace/coverage/default/27.prim_present_test.1014331299 |
| /workspace/coverage/default/28.prim_present_test.3947487116 |
| /workspace/coverage/default/29.prim_present_test.1090872895 |
| /workspace/coverage/default/3.prim_present_test.3667813798 |
| /workspace/coverage/default/30.prim_present_test.4260246739 |
| /workspace/coverage/default/31.prim_present_test.3896170803 |
| /workspace/coverage/default/32.prim_present_test.4052295303 |
| /workspace/coverage/default/33.prim_present_test.978628061 |
| /workspace/coverage/default/34.prim_present_test.1810037085 |
| /workspace/coverage/default/35.prim_present_test.4100458189 |
| /workspace/coverage/default/36.prim_present_test.2182178421 |
| /workspace/coverage/default/37.prim_present_test.928836508 |
| /workspace/coverage/default/38.prim_present_test.820392215 |
| /workspace/coverage/default/39.prim_present_test.1036539959 |
| /workspace/coverage/default/4.prim_present_test.137622354 |
| /workspace/coverage/default/40.prim_present_test.267555944 |
| /workspace/coverage/default/41.prim_present_test.1451036356 |
| /workspace/coverage/default/42.prim_present_test.3839137331 |
| /workspace/coverage/default/43.prim_present_test.2748007459 |
| /workspace/coverage/default/44.prim_present_test.3552501672 |
| /workspace/coverage/default/45.prim_present_test.2896371505 |
| /workspace/coverage/default/46.prim_present_test.3569561879 |
| /workspace/coverage/default/47.prim_present_test.4281394283 |
| /workspace/coverage/default/48.prim_present_test.2605826129 |
| /workspace/coverage/default/49.prim_present_test.3641045079 |
| /workspace/coverage/default/5.prim_present_test.2285786705 |
| /workspace/coverage/default/6.prim_present_test.4077848119 |
| /workspace/coverage/default/7.prim_present_test.87363400 |
| /workspace/coverage/default/8.prim_present_test.4206562552 |
| /workspace/coverage/default/9.prim_present_test.1614176552 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/35.prim_present_test.4100458189 | Jul 27 04:22:32 PM PDT 24 | Jul 27 04:23:52 PM PDT 24 | 11886640000 ps | ||
| T2 | /workspace/coverage/default/36.prim_present_test.2182178421 | Jul 27 04:22:04 PM PDT 24 | Jul 27 04:23:11 PM PDT 24 | 8955900000 ps | ||
| T3 | /workspace/coverage/default/13.prim_present_test.192091621 | Jul 27 04:18:41 PM PDT 24 | Jul 27 04:20:17 PM PDT 24 | 13707580000 ps | ||
| T4 | /workspace/coverage/default/11.prim_present_test.2931720310 | Jul 27 04:18:48 PM PDT 24 | Jul 27 04:20:13 PM PDT 24 | 12566160000 ps | ||
| T5 | /workspace/coverage/default/29.prim_present_test.1090872895 | Jul 27 04:22:21 PM PDT 24 | Jul 27 04:24:07 PM PDT 24 | 15436140000 ps | ||
| T6 | /workspace/coverage/default/48.prim_present_test.2605826129 | Jul 27 04:18:24 PM PDT 24 | Jul 27 04:18:47 PM PDT 24 | 3457120000 ps | ||
| T7 | /workspace/coverage/default/47.prim_present_test.4281394283 | Jul 27 04:17:49 PM PDT 24 | Jul 27 04:19:25 PM PDT 24 | 11891600000 ps | ||
| T8 | /workspace/coverage/default/26.prim_present_test.994703866 | Jul 27 04:22:33 PM PDT 24 | Jul 27 04:23:53 PM PDT 24 | 10734060000 ps | ||
| T9 | /workspace/coverage/default/6.prim_present_test.4077848119 | Jul 27 04:17:30 PM PDT 24 | Jul 27 04:18:05 PM PDT 24 | 6041900000 ps | ||
| T10 | /workspace/coverage/default/37.prim_present_test.928836508 | Jul 27 04:22:04 PM PDT 24 | Jul 27 04:22:51 PM PDT 24 | 6439320000 ps | ||
| T11 | /workspace/coverage/default/41.prim_present_test.1451036356 | Jul 27 04:19:15 PM PDT 24 | Jul 27 04:20:55 PM PDT 24 | 13827860000 ps | ||
| T12 | /workspace/coverage/default/2.prim_present_test.2076623556 | Jul 27 04:17:30 PM PDT 24 | Jul 27 04:18:13 PM PDT 24 | 7473480000 ps | ||
| T13 | /workspace/coverage/default/7.prim_present_test.87363400 | Jul 27 04:17:40 PM PDT 24 | Jul 27 04:18:16 PM PDT 24 | 5835440000 ps | ||
| T14 | /workspace/coverage/default/34.prim_present_test.1810037085 | Jul 27 04:22:17 PM PDT 24 | Jul 27 04:23:46 PM PDT 24 | 12764560000 ps | ||
| T15 | /workspace/coverage/default/22.prim_present_test.1559149529 | Jul 27 04:22:30 PM PDT 24 | Jul 27 04:23:08 PM PDT 24 | 6000360000 ps | ||
| T16 | /workspace/coverage/default/16.prim_present_test.4158327569 | Jul 27 04:22:34 PM PDT 24 | Jul 27 04:24:00 PM PDT 24 | 11700640000 ps | ||
| T17 | /workspace/coverage/default/39.prim_present_test.1036539959 | Jul 27 04:20:03 PM PDT 24 | Jul 27 04:20:50 PM PDT 24 | 6561460000 ps | ||
| T18 | /workspace/coverage/default/40.prim_present_test.267555944 | Jul 27 04:22:33 PM PDT 24 | Jul 27 04:23:56 PM PDT 24 | 12497960000 ps | ||
| T19 | /workspace/coverage/default/9.prim_present_test.1614176552 | Jul 27 04:17:34 PM PDT 24 | Jul 27 04:18:57 PM PDT 24 | 12901580000 ps | ||
| T20 | /workspace/coverage/default/18.prim_present_test.2142984404 | Jul 27 04:20:49 PM PDT 24 | Jul 27 04:21:59 PM PDT 24 | 9173520000 ps | ||
| T21 | /workspace/coverage/default/30.prim_present_test.4260246739 | Jul 27 04:22:38 PM PDT 24 | Jul 27 04:24:01 PM PDT 24 | 14354860000 ps | ||
| T22 | /workspace/coverage/default/21.prim_present_test.3352645600 | Jul 27 04:22:07 PM PDT 24 | Jul 27 04:22:43 PM PDT 24 | 5379740000 ps | ||
| T23 | /workspace/coverage/default/24.prim_present_test.3940498276 | Jul 27 04:22:34 PM PDT 24 | Jul 27 04:23:01 PM PDT 24 | 3599720000 ps | ||
| T24 | /workspace/coverage/default/31.prim_present_test.3896170803 | Jul 27 04:22:27 PM PDT 24 | Jul 27 04:23:00 PM PDT 24 | 5493200000 ps | ||
| T25 | /workspace/coverage/default/10.prim_present_test.2074872994 | Jul 27 04:22:15 PM PDT 24 | Jul 27 04:22:46 PM PDT 24 | 4027520000 ps | ||
| T26 | /workspace/coverage/default/23.prim_present_test.4178437977 | Jul 27 04:22:02 PM PDT 24 | Jul 27 04:22:29 PM PDT 24 | 4637600000 ps | ||
| T27 | /workspace/coverage/default/32.prim_present_test.4052295303 | Jul 27 04:22:04 PM PDT 24 | Jul 27 04:22:39 PM PDT 24 | 4930860000 ps | ||
| T28 | /workspace/coverage/default/20.prim_present_test.2062066499 | Jul 27 04:23:14 PM PDT 24 | Jul 27 04:24:25 PM PDT 24 | 10703680000 ps | ||
| T29 | /workspace/coverage/default/49.prim_present_test.3641045079 | Jul 27 04:17:36 PM PDT 24 | Jul 27 04:19:07 PM PDT 24 | 11368940000 ps | ||
| T30 | /workspace/coverage/default/27.prim_present_test.1014331299 | Jul 27 04:22:20 PM PDT 24 | Jul 27 04:23:16 PM PDT 24 | 7995520000 ps | ||
| T31 | /workspace/coverage/default/28.prim_present_test.3947487116 | Jul 27 04:19:01 PM PDT 24 | Jul 27 04:19:58 PM PDT 24 | 9071220000 ps | ||
| T32 | /workspace/coverage/default/45.prim_present_test.2896371505 | Jul 27 04:22:33 PM PDT 24 | Jul 27 04:23:18 PM PDT 24 | 6581300000 ps | ||
| T33 | /workspace/coverage/default/19.prim_present_test.1057655856 | Jul 27 04:22:08 PM PDT 24 | Jul 27 04:22:56 PM PDT 24 | 7468520000 ps | ||
| T34 | /workspace/coverage/default/43.prim_present_test.2748007459 | Jul 27 04:19:16 PM PDT 24 | Jul 27 04:20:31 PM PDT 24 | 10667720000 ps | ||
| T35 | /workspace/coverage/default/33.prim_present_test.978628061 | Jul 27 04:22:04 PM PDT 24 | Jul 27 04:22:38 PM PDT 24 | 4728740000 ps | ||
| T36 | /workspace/coverage/default/46.prim_present_test.3569561879 | Jul 27 04:22:31 PM PDT 24 | Jul 27 04:23:50 PM PDT 24 | 11498520000 ps | ||
| T37 | /workspace/coverage/default/0.prim_present_test.315572155 | Jul 27 04:22:08 PM PDT 24 | Jul 27 04:23:47 PM PDT 24 | 15030660000 ps | ||
| T38 | /workspace/coverage/default/44.prim_present_test.3552501672 | Jul 27 04:22:37 PM PDT 24 | Jul 27 04:23:35 PM PDT 24 | 7939720000 ps | ||
| T39 | /workspace/coverage/default/17.prim_present_test.877353426 | Jul 27 04:18:41 PM PDT 24 | Jul 27 04:19:28 PM PDT 24 | 6857820000 ps | ||
| T40 | /workspace/coverage/default/25.prim_present_test.66993822 | Jul 27 04:20:36 PM PDT 24 | Jul 27 04:21:28 PM PDT 24 | 7173400000 ps | ||
| T41 | /workspace/coverage/default/12.prim_present_test.3549305682 | Jul 27 04:18:41 PM PDT 24 | Jul 27 04:19:37 PM PDT 24 | 8595060000 ps | ||
| T42 | /workspace/coverage/default/38.prim_present_test.820392215 | Jul 27 04:22:21 PM PDT 24 | Jul 27 04:23:48 PM PDT 24 | 12109840000 ps | ||
| T43 | /workspace/coverage/default/42.prim_present_test.3839137331 | Jul 27 04:17:48 PM PDT 24 | Jul 27 04:18:35 PM PDT 24 | 5824900000 ps | ||
| T44 | /workspace/coverage/default/14.prim_present_test.513213809 | Jul 27 04:23:13 PM PDT 24 | Jul 27 04:24:37 PM PDT 24 | 14276740000 ps | ||
| T45 | /workspace/coverage/default/15.prim_present_test.658899919 | Jul 27 04:18:41 PM PDT 24 | Jul 27 04:19:33 PM PDT 24 | 7643360000 ps | ||
| T46 | /workspace/coverage/default/5.prim_present_test.2285786705 | Jul 27 04:22:20 PM PDT 24 | Jul 27 04:23:43 PM PDT 24 | 12377680000 ps | ||
| T47 | /workspace/coverage/default/4.prim_present_test.137622354 | Jul 27 04:22:21 PM PDT 24 | Jul 27 04:22:55 PM PDT 24 | 4430520000 ps | ||
| T48 | /workspace/coverage/default/1.prim_present_test.2828388415 | Jul 27 04:17:41 PM PDT 24 | Jul 27 04:18:20 PM PDT 24 | 5668040000 ps | ||
| T49 | /workspace/coverage/default/8.prim_present_test.4206562552 | Jul 27 04:22:47 PM PDT 24 | Jul 27 04:23:52 PM PDT 24 | 10745220000 ps | ||
| T50 | /workspace/coverage/default/3.prim_present_test.3667813798 | Jul 27 04:21:14 PM PDT 24 | Jul 27 04:22:16 PM PDT 24 | 8286920000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.2931720310 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12566160000 ps |
| CPU time | 45.23 seconds |
| Started | Jul 27 04:18:48 PM PDT 24 |
| Finished | Jul 27 04:20:13 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-431b9857-e427-4830-b29a-a19fba5d93ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2931720310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2931720310 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.315572155 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 15030660000 ps |
| CPU time | 52.91 seconds |
| Started | Jul 27 04:22:08 PM PDT 24 |
| Finished | Jul 27 04:23:47 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-9121fc2c-334f-4569-b710-9d758ca1e85f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315572155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.315572155 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2828388415 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5668040000 ps |
| CPU time | 21.04 seconds |
| Started | Jul 27 04:17:41 PM PDT 24 |
| Finished | Jul 27 04:18:20 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-22352db8-90e0-4e46-bc75-163072fb0b2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828388415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2828388415 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2074872994 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4027520000 ps |
| CPU time | 16.03 seconds |
| Started | Jul 27 04:22:15 PM PDT 24 |
| Finished | Jul 27 04:22:46 PM PDT 24 |
| Peak memory | 144768 kb |
| Host | smart-6770a14f-1b97-4e63-810f-22c6db06a5ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074872994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2074872994 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3549305682 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8595060000 ps |
| CPU time | 30.14 seconds |
| Started | Jul 27 04:18:41 PM PDT 24 |
| Finished | Jul 27 04:19:37 PM PDT 24 |
| Peak memory | 144340 kb |
| Host | smart-e6cd6e99-62b3-4b6b-a3ba-bf7cfc79d01a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549305682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3549305682 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.192091621 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13707580000 ps |
| CPU time | 50.69 seconds |
| Started | Jul 27 04:18:41 PM PDT 24 |
| Finished | Jul 27 04:20:17 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-86855ba3-7fa5-4c75-838b-862f7833817e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192091621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.192091621 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.513213809 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14276740000 ps |
| CPU time | 45.17 seconds |
| Started | Jul 27 04:23:13 PM PDT 24 |
| Finished | Jul 27 04:24:37 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-2b22b9d7-efac-42e5-ac38-22b2c50bd5e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513213809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.513213809 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.658899919 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7643360000 ps |
| CPU time | 28.2 seconds |
| Started | Jul 27 04:18:41 PM PDT 24 |
| Finished | Jul 27 04:19:33 PM PDT 24 |
| Peak memory | 143012 kb |
| Host | smart-d54d64c5-0201-4f7a-9eed-b5f18e57c1b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=658899919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.658899919 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.4158327569 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11700640000 ps |
| CPU time | 44.61 seconds |
| Started | Jul 27 04:22:34 PM PDT 24 |
| Finished | Jul 27 04:24:00 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-97d13a45-d2ae-44a7-b38e-bab4f6cd1cba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158327569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.4158327569 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.877353426 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6857820000 ps |
| CPU time | 25.17 seconds |
| Started | Jul 27 04:18:41 PM PDT 24 |
| Finished | Jul 27 04:19:28 PM PDT 24 |
| Peak memory | 143992 kb |
| Host | smart-1266d53e-88e5-40d6-aca4-ad2921727ff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877353426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.877353426 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2142984404 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9173520000 ps |
| CPU time | 36.46 seconds |
| Started | Jul 27 04:20:49 PM PDT 24 |
| Finished | Jul 27 04:21:59 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-e854206e-3239-4624-9f46-12cec70f1e0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142984404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2142984404 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1057655856 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7468520000 ps |
| CPU time | 26.16 seconds |
| Started | Jul 27 04:22:08 PM PDT 24 |
| Finished | Jul 27 04:22:56 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-b7c62fba-b4d5-484c-b014-8838c7c51cef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057655856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1057655856 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2076623556 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7473480000 ps |
| CPU time | 22.72 seconds |
| Started | Jul 27 04:17:30 PM PDT 24 |
| Finished | Jul 27 04:18:13 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-cbd5bfec-7074-4154-b713-e382bd6398a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076623556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2076623556 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2062066499 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10703680000 ps |
| CPU time | 37.58 seconds |
| Started | Jul 27 04:23:14 PM PDT 24 |
| Finished | Jul 27 04:24:25 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-ab714aa4-a02b-4788-ab16-240c80b1c6e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062066499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2062066499 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3352645600 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5379740000 ps |
| CPU time | 19.34 seconds |
| Started | Jul 27 04:22:07 PM PDT 24 |
| Finished | Jul 27 04:22:43 PM PDT 24 |
| Peak memory | 143848 kb |
| Host | smart-7597fd27-609a-4b36-b3cb-562752774707 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352645600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3352645600 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1559149529 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6000360000 ps |
| CPU time | 19.95 seconds |
| Started | Jul 27 04:22:30 PM PDT 24 |
| Finished | Jul 27 04:23:08 PM PDT 24 |
| Peak memory | 143628 kb |
| Host | smart-eb7bde99-a040-487f-93e6-f2bba20e34d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1559149529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1559149529 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.4178437977 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4637600000 ps |
| CPU time | 14.78 seconds |
| Started | Jul 27 04:22:02 PM PDT 24 |
| Finished | Jul 27 04:22:29 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-56ff9d78-16a5-4b92-8aa7-418866b95c94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178437977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.4178437977 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3940498276 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3599720000 ps |
| CPU time | 14.1 seconds |
| Started | Jul 27 04:22:34 PM PDT 24 |
| Finished | Jul 27 04:23:01 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-41fb38de-8a3e-40df-b3a2-c676c8b040b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940498276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3940498276 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.66993822 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7173400000 ps |
| CPU time | 27.36 seconds |
| Started | Jul 27 04:20:36 PM PDT 24 |
| Finished | Jul 27 04:21:28 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-50412ffb-208a-4c7e-b92d-31d866a4bf6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66993822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.66993822 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.994703866 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10734060000 ps |
| CPU time | 42.52 seconds |
| Started | Jul 27 04:22:33 PM PDT 24 |
| Finished | Jul 27 04:23:53 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-f811d40d-e09f-4bef-bf05-df849bc08d77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=994703866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.994703866 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1014331299 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7995520000 ps |
| CPU time | 29.41 seconds |
| Started | Jul 27 04:22:20 PM PDT 24 |
| Finished | Jul 27 04:23:16 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-04c230a2-8e88-4a19-a4e3-26e278b156fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014331299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1014331299 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3947487116 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9071220000 ps |
| CPU time | 30.96 seconds |
| Started | Jul 27 04:19:01 PM PDT 24 |
| Finished | Jul 27 04:19:58 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-512e2b69-fc14-42d6-a8cc-05b9530ed4ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947487116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3947487116 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1090872895 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 15436140000 ps |
| CPU time | 55.7 seconds |
| Started | Jul 27 04:22:21 PM PDT 24 |
| Finished | Jul 27 04:24:07 PM PDT 24 |
| Peak memory | 144700 kb |
| Host | smart-6ab32bb9-b273-4ac5-a8d0-b0f3d24b4c2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090872895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1090872895 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3667813798 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8286920000 ps |
| CPU time | 32.52 seconds |
| Started | Jul 27 04:21:14 PM PDT 24 |
| Finished | Jul 27 04:22:16 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-327369fd-8133-43f4-a67e-90348e505468 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667813798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3667813798 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.4260246739 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14354860000 ps |
| CPU time | 44.5 seconds |
| Started | Jul 27 04:22:38 PM PDT 24 |
| Finished | Jul 27 04:24:01 PM PDT 24 |
| Peak memory | 144300 kb |
| Host | smart-8db2fc6b-a6e5-4583-9d64-0be135e3cc09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4260246739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4260246739 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3896170803 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5493200000 ps |
| CPU time | 17.98 seconds |
| Started | Jul 27 04:22:27 PM PDT 24 |
| Finished | Jul 27 04:23:00 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-cde913de-f14b-46fb-b56a-5830ff507aed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896170803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3896170803 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4052295303 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4930860000 ps |
| CPU time | 18.26 seconds |
| Started | Jul 27 04:22:04 PM PDT 24 |
| Finished | Jul 27 04:22:39 PM PDT 24 |
| Peak memory | 142748 kb |
| Host | smart-5f28a0f1-7f24-4355-9e50-3ac7b28a609a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052295303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4052295303 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.978628061 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4728740000 ps |
| CPU time | 17.66 seconds |
| Started | Jul 27 04:22:04 PM PDT 24 |
| Finished | Jul 27 04:22:38 PM PDT 24 |
| Peak memory | 142400 kb |
| Host | smart-93cb78ff-f51b-4026-915e-32b157e0bcca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=978628061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.978628061 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1810037085 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12764560000 ps |
| CPU time | 47.04 seconds |
| Started | Jul 27 04:22:17 PM PDT 24 |
| Finished | Jul 27 04:23:46 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-103f2712-7e41-4599-ab2c-8f90e1254262 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1810037085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1810037085 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4100458189 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11886640000 ps |
| CPU time | 42.87 seconds |
| Started | Jul 27 04:22:32 PM PDT 24 |
| Finished | Jul 27 04:23:52 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-50769cb1-5899-4cd2-9139-eddaccaa0f18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4100458189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4100458189 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2182178421 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8955900000 ps |
| CPU time | 35.14 seconds |
| Started | Jul 27 04:22:04 PM PDT 24 |
| Finished | Jul 27 04:23:11 PM PDT 24 |
| Peak memory | 142192 kb |
| Host | smart-3f0ea870-1cef-49c8-888c-5ee17f8e5060 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182178421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2182178421 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.928836508 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6439320000 ps |
| CPU time | 24.49 seconds |
| Started | Jul 27 04:22:04 PM PDT 24 |
| Finished | Jul 27 04:22:51 PM PDT 24 |
| Peak memory | 141888 kb |
| Host | smart-9a6563be-b319-4f47-8c51-79941de43672 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928836508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.928836508 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.820392215 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12109840000 ps |
| CPU time | 45.48 seconds |
| Started | Jul 27 04:22:21 PM PDT 24 |
| Finished | Jul 27 04:23:48 PM PDT 24 |
| Peak memory | 144540 kb |
| Host | smart-0fb80dcf-f1d1-4818-9597-29ad6b9a3959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820392215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.820392215 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1036539959 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6561460000 ps |
| CPU time | 24.53 seconds |
| Started | Jul 27 04:20:03 PM PDT 24 |
| Finished | Jul 27 04:20:50 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-c0888de9-9bd2-496f-96b6-795ce48c8c48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1036539959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1036539959 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.137622354 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4430520000 ps |
| CPU time | 17.78 seconds |
| Started | Jul 27 04:22:21 PM PDT 24 |
| Finished | Jul 27 04:22:55 PM PDT 24 |
| Peak memory | 144608 kb |
| Host | smart-df750daa-ee69-4263-a1f8-65926095693f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137622354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.137622354 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.267555944 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12497960000 ps |
| CPU time | 44.06 seconds |
| Started | Jul 27 04:22:33 PM PDT 24 |
| Finished | Jul 27 04:23:56 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-5fc2c3b1-00b2-4052-932f-d4680ced83fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267555944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.267555944 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1451036356 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13827860000 ps |
| CPU time | 53.47 seconds |
| Started | Jul 27 04:19:15 PM PDT 24 |
| Finished | Jul 27 04:20:55 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-298ffe77-47f3-467b-94c6-1881f9be2249 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451036356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1451036356 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3839137331 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5824900000 ps |
| CPU time | 24.47 seconds |
| Started | Jul 27 04:17:48 PM PDT 24 |
| Finished | Jul 27 04:18:35 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-fa566545-45a5-4734-90da-ba024a3bf616 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839137331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3839137331 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2748007459 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10667720000 ps |
| CPU time | 39.87 seconds |
| Started | Jul 27 04:19:16 PM PDT 24 |
| Finished | Jul 27 04:20:31 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-d98c13e4-bd25-4d95-bcb2-8221ee9f1c5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748007459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2748007459 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3552501672 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7939720000 ps |
| CPU time | 30.6 seconds |
| Started | Jul 27 04:22:37 PM PDT 24 |
| Finished | Jul 27 04:23:35 PM PDT 24 |
| Peak memory | 144852 kb |
| Host | smart-08a4eb14-3821-419d-a319-c9ef124c1846 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552501672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3552501672 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2896371505 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6581300000 ps |
| CPU time | 23.96 seconds |
| Started | Jul 27 04:22:33 PM PDT 24 |
| Finished | Jul 27 04:23:18 PM PDT 24 |
| Peak memory | 144844 kb |
| Host | smart-c18f8350-5f6d-4c25-a243-67db03340bad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896371505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2896371505 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3569561879 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11498520000 ps |
| CPU time | 41.6 seconds |
| Started | Jul 27 04:22:31 PM PDT 24 |
| Finished | Jul 27 04:23:50 PM PDT 24 |
| Peak memory | 144676 kb |
| Host | smart-35517537-f5e7-464c-a551-e8e7e19d77f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569561879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3569561879 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4281394283 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11891600000 ps |
| CPU time | 49.77 seconds |
| Started | Jul 27 04:17:49 PM PDT 24 |
| Finished | Jul 27 04:19:25 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-5243840e-1c01-4626-9a2b-9db26c5c431d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281394283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4281394283 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2605826129 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3457120000 ps |
| CPU time | 12.86 seconds |
| Started | Jul 27 04:18:24 PM PDT 24 |
| Finished | Jul 27 04:18:47 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-f07cc0d4-1b0e-4d21-abfc-e7102cc69422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605826129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2605826129 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3641045079 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11368940000 ps |
| CPU time | 46.95 seconds |
| Started | Jul 27 04:17:36 PM PDT 24 |
| Finished | Jul 27 04:19:07 PM PDT 24 |
| Peak memory | 143956 kb |
| Host | smart-e1eb9307-51ff-476d-b0a4-7556dfd6b714 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641045079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3641045079 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2285786705 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12377680000 ps |
| CPU time | 43.45 seconds |
| Started | Jul 27 04:22:20 PM PDT 24 |
| Finished | Jul 27 04:23:43 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-3dc42126-a5ac-4d1c-a00a-f788f293acd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285786705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2285786705 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4077848119 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6041900000 ps |
| CPU time | 18.59 seconds |
| Started | Jul 27 04:17:30 PM PDT 24 |
| Finished | Jul 27 04:18:05 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-3ba9635c-5beb-4637-9eb2-b20cfac11f98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077848119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4077848119 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.87363400 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5835440000 ps |
| CPU time | 19.38 seconds |
| Started | Jul 27 04:17:40 PM PDT 24 |
| Finished | Jul 27 04:18:16 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-216a4510-de69-4e8b-b8ca-9bec6492a721 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87363400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.87363400 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4206562552 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10745220000 ps |
| CPU time | 35.52 seconds |
| Started | Jul 27 04:22:47 PM PDT 24 |
| Finished | Jul 27 04:23:52 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-76d3ad3e-522f-491c-8352-e50f71c07a6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206562552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4206562552 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1614176552 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12901580000 ps |
| CPU time | 45.75 seconds |
| Started | Jul 27 04:17:34 PM PDT 24 |
| Finished | Jul 27 04:18:57 PM PDT 24 |
| Peak memory | 143452 kb |
| Host | smart-b55d0540-3ad9-450b-8cd2-c2312c8da58f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614176552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1614176552 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |