| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.4062913935 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.426915654 |
| /workspace/coverage/default/1.prim_present_test.58012652 |
| /workspace/coverage/default/10.prim_present_test.2619420131 |
| /workspace/coverage/default/12.prim_present_test.1182586314 |
| /workspace/coverage/default/13.prim_present_test.91588843 |
| /workspace/coverage/default/14.prim_present_test.4242056554 |
| /workspace/coverage/default/15.prim_present_test.269035307 |
| /workspace/coverage/default/16.prim_present_test.1845364494 |
| /workspace/coverage/default/17.prim_present_test.2783419239 |
| /workspace/coverage/default/18.prim_present_test.2648454525 |
| /workspace/coverage/default/19.prim_present_test.3833145258 |
| /workspace/coverage/default/2.prim_present_test.3291981738 |
| /workspace/coverage/default/20.prim_present_test.678158520 |
| /workspace/coverage/default/21.prim_present_test.1831416691 |
| /workspace/coverage/default/22.prim_present_test.4239185957 |
| /workspace/coverage/default/23.prim_present_test.2822388149 |
| /workspace/coverage/default/24.prim_present_test.2287591847 |
| /workspace/coverage/default/25.prim_present_test.4031481794 |
| /workspace/coverage/default/26.prim_present_test.2666909772 |
| /workspace/coverage/default/27.prim_present_test.3346331586 |
| /workspace/coverage/default/28.prim_present_test.3928758635 |
| /workspace/coverage/default/29.prim_present_test.2812697168 |
| /workspace/coverage/default/3.prim_present_test.942328017 |
| /workspace/coverage/default/30.prim_present_test.987591251 |
| /workspace/coverage/default/31.prim_present_test.3107604858 |
| /workspace/coverage/default/32.prim_present_test.2173866104 |
| /workspace/coverage/default/33.prim_present_test.2140873405 |
| /workspace/coverage/default/34.prim_present_test.3148215845 |
| /workspace/coverage/default/35.prim_present_test.1496981587 |
| /workspace/coverage/default/36.prim_present_test.313189109 |
| /workspace/coverage/default/37.prim_present_test.854591750 |
| /workspace/coverage/default/38.prim_present_test.2599419116 |
| /workspace/coverage/default/39.prim_present_test.2794328433 |
| /workspace/coverage/default/4.prim_present_test.371902702 |
| /workspace/coverage/default/40.prim_present_test.3117191570 |
| /workspace/coverage/default/41.prim_present_test.1095031412 |
| /workspace/coverage/default/42.prim_present_test.3418941596 |
| /workspace/coverage/default/43.prim_present_test.3521343316 |
| /workspace/coverage/default/44.prim_present_test.3308088095 |
| /workspace/coverage/default/45.prim_present_test.1846221102 |
| /workspace/coverage/default/46.prim_present_test.3847857639 |
| /workspace/coverage/default/47.prim_present_test.4098716331 |
| /workspace/coverage/default/48.prim_present_test.4206459572 |
| /workspace/coverage/default/49.prim_present_test.363302587 |
| /workspace/coverage/default/5.prim_present_test.3403053159 |
| /workspace/coverage/default/6.prim_present_test.1333865171 |
| /workspace/coverage/default/7.prim_present_test.3827706021 |
| /workspace/coverage/default/8.prim_present_test.4211082447 |
| /workspace/coverage/default/9.prim_present_test.2569862267 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/32.prim_present_test.2173866104 | Jul 28 04:22:34 PM PDT 24 | Jul 28 04:23:53 PM PDT 24 | 10533180000 ps | ||
| T2 | /workspace/coverage/default/37.prim_present_test.854591750 | Jul 28 04:21:06 PM PDT 24 | Jul 28 04:22:22 PM PDT 24 | 11111640000 ps | ||
| T3 | /workspace/coverage/default/11.prim_present_test.4062913935 | Jul 28 04:20:04 PM PDT 24 | Jul 28 04:21:45 PM PDT 24 | 15227200000 ps | ||
| T4 | /workspace/coverage/default/3.prim_present_test.942328017 | Jul 28 04:21:16 PM PDT 24 | Jul 28 04:21:41 PM PDT 24 | 3409380000 ps | ||
| T5 | /workspace/coverage/default/35.prim_present_test.1496981587 | Jul 28 04:25:06 PM PDT 24 | Jul 28 04:26:28 PM PDT 24 | 14244500000 ps | ||
| T6 | /workspace/coverage/default/19.prim_present_test.3833145258 | Jul 28 04:21:29 PM PDT 24 | Jul 28 04:21:56 PM PDT 24 | 3501760000 ps | ||
| T7 | /workspace/coverage/default/40.prim_present_test.3117191570 | Jul 28 04:25:32 PM PDT 24 | Jul 28 04:26:12 PM PDT 24 | 6121880000 ps | ||
| T8 | /workspace/coverage/default/16.prim_present_test.1845364494 | Jul 28 04:21:28 PM PDT 24 | Jul 28 04:22:57 PM PDT 24 | 11662200000 ps | ||
| T9 | /workspace/coverage/default/2.prim_present_test.3291981738 | Jul 28 04:20:14 PM PDT 24 | Jul 28 04:20:40 PM PDT 24 | 4010160000 ps | ||
| T10 | /workspace/coverage/default/23.prim_present_test.2822388149 | Jul 28 04:21:18 PM PDT 24 | Jul 28 04:22:04 PM PDT 24 | 6302300000 ps | ||
| T11 | /workspace/coverage/default/18.prim_present_test.2648454525 | Jul 28 04:21:17 PM PDT 24 | Jul 28 04:22:14 PM PDT 24 | 7585700000 ps | ||
| T12 | /workspace/coverage/default/43.prim_present_test.3521343316 | Jul 28 04:25:32 PM PDT 24 | Jul 28 04:26:39 PM PDT 24 | 10283320000 ps | ||
| T13 | /workspace/coverage/default/48.prim_present_test.4206459572 | Jul 28 04:25:06 PM PDT 24 | Jul 28 04:26:33 PM PDT 24 | 15088320000 ps | ||
| T14 | /workspace/coverage/default/33.prim_present_test.2140873405 | Jul 28 04:25:06 PM PDT 24 | Jul 28 04:25:32 PM PDT 24 | 4132300000 ps | ||
| T15 | /workspace/coverage/default/25.prim_present_test.4031481794 | Jul 28 04:20:30 PM PDT 24 | Jul 28 04:21:29 PM PDT 24 | 9177860000 ps | ||
| T16 | /workspace/coverage/default/42.prim_present_test.3418941596 | Jul 28 04:25:32 PM PDT 24 | Jul 28 04:26:56 PM PDT 24 | 12727360000 ps | ||
| T17 | /workspace/coverage/default/9.prim_present_test.2569862267 | Jul 28 04:20:26 PM PDT 24 | Jul 28 04:21:48 PM PDT 24 | 12189820000 ps | ||
| T18 | /workspace/coverage/default/1.prim_present_test.58012652 | Jul 28 04:21:15 PM PDT 24 | Jul 28 04:22:34 PM PDT 24 | 12856940000 ps | ||
| T19 | /workspace/coverage/default/4.prim_present_test.371902702 | Jul 28 04:21:25 PM PDT 24 | Jul 28 04:22:44 PM PDT 24 | 11280900000 ps | ||
| T20 | /workspace/coverage/default/47.prim_present_test.4098716331 | Jul 28 04:21:43 PM PDT 24 | Jul 28 04:22:33 PM PDT 24 | 6518060000 ps | ||
| T21 | /workspace/coverage/default/28.prim_present_test.3928758635 | Jul 28 04:25:03 PM PDT 24 | Jul 28 04:25:54 PM PDT 24 | 7652660000 ps | ||
| T22 | /workspace/coverage/default/14.prim_present_test.4242056554 | Jul 28 04:21:14 PM PDT 24 | Jul 28 04:22:22 PM PDT 24 | 10292620000 ps | ||
| T23 | /workspace/coverage/default/5.prim_present_test.3403053159 | Jul 28 04:21:15 PM PDT 24 | Jul 28 04:21:44 PM PDT 24 | 4297220000 ps | ||
| T24 | /workspace/coverage/default/0.prim_present_test.426915654 | Jul 28 04:21:15 PM PDT 24 | Jul 28 04:22:10 PM PDT 24 | 7600580000 ps | ||
| T25 | /workspace/coverage/default/17.prim_present_test.2783419239 | Jul 28 04:21:17 PM PDT 24 | Jul 28 04:22:36 PM PDT 24 | 11106680000 ps | ||
| T26 | /workspace/coverage/default/45.prim_present_test.1846221102 | Jul 28 04:25:31 PM PDT 24 | Jul 28 04:26:50 PM PDT 24 | 12137120000 ps | ||
| T27 | /workspace/coverage/default/41.prim_present_test.1095031412 | Jul 28 04:22:21 PM PDT 24 | Jul 28 04:23:20 PM PDT 24 | 9605040000 ps | ||
| T28 | /workspace/coverage/default/31.prim_present_test.3107604858 | Jul 28 04:22:43 PM PDT 24 | Jul 28 04:23:30 PM PDT 24 | 8388600000 ps | ||
| T29 | /workspace/coverage/default/21.prim_present_test.1831416691 | Jul 28 04:21:30 PM PDT 24 | Jul 28 04:22:25 PM PDT 24 | 7240980000 ps | ||
| T30 | /workspace/coverage/default/27.prim_present_test.3346331586 | Jul 28 04:21:03 PM PDT 24 | Jul 28 04:22:34 PM PDT 24 | 13268620000 ps | ||
| T31 | /workspace/coverage/default/7.prim_present_test.3827706021 | Jul 28 04:21:25 PM PDT 24 | Jul 28 04:21:54 PM PDT 24 | 4082080000 ps | ||
| T32 | /workspace/coverage/default/8.prim_present_test.4211082447 | Jul 28 04:21:24 PM PDT 24 | Jul 28 04:22:07 PM PDT 24 | 6213640000 ps | ||
| T33 | /workspace/coverage/default/36.prim_present_test.313189109 | Jul 28 04:22:56 PM PDT 24 | Jul 28 04:23:21 PM PDT 24 | 3235780000 ps | ||
| T34 | /workspace/coverage/default/46.prim_present_test.3847857639 | Jul 28 04:24:48 PM PDT 24 | Jul 28 04:25:29 PM PDT 24 | 6168380000 ps | ||
| T35 | /workspace/coverage/default/34.prim_present_test.3148215845 | Jul 28 04:21:05 PM PDT 24 | Jul 28 04:21:49 PM PDT 24 | 6486440000 ps | ||
| T36 | /workspace/coverage/default/10.prim_present_test.2619420131 | Jul 28 04:21:20 PM PDT 24 | Jul 28 04:22:47 PM PDT 24 | 14901700000 ps | ||
| T37 | /workspace/coverage/default/6.prim_present_test.1333865171 | Jul 28 04:21:15 PM PDT 24 | Jul 28 04:22:51 PM PDT 24 | 13744780000 ps | ||
| T38 | /workspace/coverage/default/39.prim_present_test.2794328433 | Jul 28 04:22:57 PM PDT 24 | Jul 28 04:24:43 PM PDT 24 | 15098240000 ps | ||
| T39 | /workspace/coverage/default/26.prim_present_test.2666909772 | Jul 28 04:21:15 PM PDT 24 | Jul 28 04:22:26 PM PDT 24 | 9885280000 ps | ||
| T40 | /workspace/coverage/default/49.prim_present_test.363302587 | Jul 28 04:25:07 PM PDT 24 | Jul 28 04:26:01 PM PDT 24 | 8964580000 ps | ||
| T41 | /workspace/coverage/default/20.prim_present_test.678158520 | Jul 28 04:21:06 PM PDT 24 | Jul 28 04:21:42 PM PDT 24 | 4938300000 ps | ||
| T42 | /workspace/coverage/default/22.prim_present_test.4239185957 | Jul 28 04:21:17 PM PDT 24 | Jul 28 04:22:32 PM PDT 24 | 10318040000 ps | ||
| T43 | /workspace/coverage/default/24.prim_present_test.2287591847 | Jul 28 04:24:54 PM PDT 24 | Jul 28 04:26:23 PM PDT 24 | 15191240000 ps | ||
| T44 | /workspace/coverage/default/13.prim_present_test.91588843 | Jul 28 04:21:20 PM PDT 24 | Jul 28 04:22:29 PM PDT 24 | 10959740000 ps | ||
| T45 | /workspace/coverage/default/44.prim_present_test.3308088095 | Jul 28 04:25:38 PM PDT 24 | Jul 28 04:25:58 PM PDT 24 | 3107440000 ps | ||
| T46 | /workspace/coverage/default/38.prim_present_test.2599419116 | Jul 28 04:24:53 PM PDT 24 | Jul 28 04:26:30 PM PDT 24 | 14889920000 ps | ||
| T47 | /workspace/coverage/default/12.prim_present_test.1182586314 | Jul 28 04:21:19 PM PDT 24 | Jul 28 04:22:08 PM PDT 24 | 7661340000 ps | ||
| T48 | /workspace/coverage/default/15.prim_present_test.269035307 | Jul 28 04:21:14 PM PDT 24 | Jul 28 04:22:41 PM PDT 24 | 12860660000 ps | ||
| T49 | /workspace/coverage/default/30.prim_present_test.987591251 | Jul 28 04:24:53 PM PDT 24 | Jul 28 04:25:19 PM PDT 24 | 3237640000 ps | ||
| T50 | /workspace/coverage/default/29.prim_present_test.2812697168 | Jul 28 04:25:06 PM PDT 24 | Jul 28 04:25:30 PM PDT 24 | 3511680000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.4062913935 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 15227200000 ps |
| CPU time | 53.6 seconds |
| Started | Jul 28 04:20:04 PM PDT 24 |
| Finished | Jul 28 04:21:45 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-6963b8ea-869e-40c9-bbf8-8aa784f5f82a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062913935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4062913935 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.426915654 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7600580000 ps |
| CPU time | 27.65 seconds |
| Started | Jul 28 04:21:15 PM PDT 24 |
| Finished | Jul 28 04:22:10 PM PDT 24 |
| Peak memory | 143760 kb |
| Host | smart-e3c47d71-9b0d-4819-99de-d495304d1eaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426915654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.426915654 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.58012652 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12856940000 ps |
| CPU time | 42.73 seconds |
| Started | Jul 28 04:21:15 PM PDT 24 |
| Finished | Jul 28 04:22:34 PM PDT 24 |
| Peak memory | 144108 kb |
| Host | smart-12ad19ee-f5ea-4cab-8a40-9a5d16ea283b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58012652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.58012652 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2619420131 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14901700000 ps |
| CPU time | 47.01 seconds |
| Started | Jul 28 04:21:20 PM PDT 24 |
| Finished | Jul 28 04:22:47 PM PDT 24 |
| Peak memory | 144780 kb |
| Host | smart-eb7f608e-af93-4011-bcc7-261150605c12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619420131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2619420131 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1182586314 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7661340000 ps |
| CPU time | 25.95 seconds |
| Started | Jul 28 04:21:19 PM PDT 24 |
| Finished | Jul 28 04:22:08 PM PDT 24 |
| Peak memory | 144708 kb |
| Host | smart-3408cdd6-2047-4cbf-9faa-4f2b91073907 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182586314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1182586314 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.91588843 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10959740000 ps |
| CPU time | 36.35 seconds |
| Started | Jul 28 04:21:20 PM PDT 24 |
| Finished | Jul 28 04:22:29 PM PDT 24 |
| Peak memory | 144732 kb |
| Host | smart-b59a62e3-38fd-48cc-a9eb-f2fec684e730 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91588843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.91588843 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4242056554 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10292620000 ps |
| CPU time | 36.6 seconds |
| Started | Jul 28 04:21:14 PM PDT 24 |
| Finished | Jul 28 04:22:22 PM PDT 24 |
| Peak memory | 144556 kb |
| Host | smart-d6ca8692-b96a-4552-8d13-cb74868f18b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242056554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4242056554 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.269035307 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12860660000 ps |
| CPU time | 46.63 seconds |
| Started | Jul 28 04:21:14 PM PDT 24 |
| Finished | Jul 28 04:22:41 PM PDT 24 |
| Peak memory | 143744 kb |
| Host | smart-547e4aa9-b10e-48fe-8d0a-b3554307f4df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269035307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.269035307 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1845364494 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11662200000 ps |
| CPU time | 47.35 seconds |
| Started | Jul 28 04:21:28 PM PDT 24 |
| Finished | Jul 28 04:22:57 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-f81ddf47-8b1e-47ff-8fb7-2855e1c7e1b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845364494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1845364494 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2783419239 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11106680000 ps |
| CPU time | 41.2 seconds |
| Started | Jul 28 04:21:17 PM PDT 24 |
| Finished | Jul 28 04:22:36 PM PDT 24 |
| Peak memory | 144540 kb |
| Host | smart-8f688fc6-e7f4-42a1-a521-c0846ba5cef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783419239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2783419239 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2648454525 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7585700000 ps |
| CPU time | 29.49 seconds |
| Started | Jul 28 04:21:17 PM PDT 24 |
| Finished | Jul 28 04:22:14 PM PDT 24 |
| Peak memory | 143196 kb |
| Host | smart-b069b56b-8eec-4808-9564-bb2ac912de89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2648454525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2648454525 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3833145258 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3501760000 ps |
| CPU time | 14.06 seconds |
| Started | Jul 28 04:21:29 PM PDT 24 |
| Finished | Jul 28 04:21:56 PM PDT 24 |
| Peak memory | 144856 kb |
| Host | smart-e51f14ca-8fcb-4c00-bda2-fd45daabb457 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833145258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3833145258 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3291981738 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4010160000 ps |
| CPU time | 13.77 seconds |
| Started | Jul 28 04:20:14 PM PDT 24 |
| Finished | Jul 28 04:20:40 PM PDT 24 |
| Peak memory | 143896 kb |
| Host | smart-7706632e-88c7-4997-bee4-e3c0172abdd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291981738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3291981738 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.678158520 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4938300000 ps |
| CPU time | 18.99 seconds |
| Started | Jul 28 04:21:06 PM PDT 24 |
| Finished | Jul 28 04:21:42 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-322ab229-029b-45ed-bc6d-b0fe2854ea19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=678158520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.678158520 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1831416691 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7240980000 ps |
| CPU time | 28.81 seconds |
| Started | Jul 28 04:21:30 PM PDT 24 |
| Finished | Jul 28 04:22:25 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-6b09f3a2-e5f0-44d0-ad3a-487e2afd119e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831416691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1831416691 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.4239185957 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10318040000 ps |
| CPU time | 38.89 seconds |
| Started | Jul 28 04:21:17 PM PDT 24 |
| Finished | Jul 28 04:22:32 PM PDT 24 |
| Peak memory | 143364 kb |
| Host | smart-8358826c-600d-45fb-9ef7-427e7de592bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4239185957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.4239185957 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2822388149 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6302300000 ps |
| CPU time | 24.14 seconds |
| Started | Jul 28 04:21:18 PM PDT 24 |
| Finished | Jul 28 04:22:04 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-f796530a-5433-4364-a4be-e54ea1a20068 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822388149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2822388149 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2287591847 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15191240000 ps |
| CPU time | 48.43 seconds |
| Started | Jul 28 04:24:54 PM PDT 24 |
| Finished | Jul 28 04:26:23 PM PDT 24 |
| Peak memory | 143692 kb |
| Host | smart-c7fb4932-658c-45a7-bf42-47ca5c2b680d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287591847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2287591847 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4031481794 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9177860000 ps |
| CPU time | 31.4 seconds |
| Started | Jul 28 04:20:30 PM PDT 24 |
| Finished | Jul 28 04:21:29 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-82d94988-6025-42aa-95a2-4f7b31e806fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031481794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4031481794 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2666909772 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9885280000 ps |
| CPU time | 36.71 seconds |
| Started | Jul 28 04:21:15 PM PDT 24 |
| Finished | Jul 28 04:22:26 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-eef42ef2-78a6-4cfc-aaf7-24aeeece9389 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666909772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2666909772 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3346331586 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13268620000 ps |
| CPU time | 48.1 seconds |
| Started | Jul 28 04:21:03 PM PDT 24 |
| Finished | Jul 28 04:22:34 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-5a13f01b-6124-4d3b-82bc-99b754e18e81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346331586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3346331586 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3928758635 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7652660000 ps |
| CPU time | 27.52 seconds |
| Started | Jul 28 04:25:03 PM PDT 24 |
| Finished | Jul 28 04:25:54 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-36eeab5f-3171-47de-ada0-3de5b1143580 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928758635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3928758635 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2812697168 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3511680000 ps |
| CPU time | 12.75 seconds |
| Started | Jul 28 04:25:06 PM PDT 24 |
| Finished | Jul 28 04:25:30 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-af575791-aedb-4746-87f4-c1cd947500b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2812697168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2812697168 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.942328017 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3409380000 ps |
| CPU time | 12.88 seconds |
| Started | Jul 28 04:21:16 PM PDT 24 |
| Finished | Jul 28 04:21:41 PM PDT 24 |
| Peak memory | 144620 kb |
| Host | smart-cd12703c-80da-41e7-90e1-0bf495e51097 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=942328017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.942328017 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.987591251 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3237640000 ps |
| CPU time | 13.31 seconds |
| Started | Jul 28 04:24:53 PM PDT 24 |
| Finished | Jul 28 04:25:19 PM PDT 24 |
| Peak memory | 142984 kb |
| Host | smart-e7960bfb-b020-4209-aaef-04a2d433859b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987591251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.987591251 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3107604858 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8388600000 ps |
| CPU time | 25.41 seconds |
| Started | Jul 28 04:22:43 PM PDT 24 |
| Finished | Jul 28 04:23:30 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-791fea02-6f3f-4a9f-8da8-0da61f5b196e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3107604858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3107604858 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2173866104 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10533180000 ps |
| CPU time | 41.21 seconds |
| Started | Jul 28 04:22:34 PM PDT 24 |
| Finished | Jul 28 04:23:53 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-a1b95b08-e8a6-4a15-bdac-ad5f67baa6a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173866104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2173866104 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2140873405 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4132300000 ps |
| CPU time | 14.22 seconds |
| Started | Jul 28 04:25:06 PM PDT 24 |
| Finished | Jul 28 04:25:32 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-e01e54ef-814b-4717-808c-5bc067eece77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140873405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2140873405 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3148215845 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6486440000 ps |
| CPU time | 23.4 seconds |
| Started | Jul 28 04:21:05 PM PDT 24 |
| Finished | Jul 28 04:21:49 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-13d8ab45-6502-4f03-a1a7-139b071b9939 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148215845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3148215845 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1496981587 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14244500000 ps |
| CPU time | 44.68 seconds |
| Started | Jul 28 04:25:06 PM PDT 24 |
| Finished | Jul 28 04:26:28 PM PDT 24 |
| Peak memory | 144232 kb |
| Host | smart-7e081533-1d7e-4ed2-8513-0bf6f1a2c41d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1496981587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1496981587 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.313189109 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3235780000 ps |
| CPU time | 13.32 seconds |
| Started | Jul 28 04:22:56 PM PDT 24 |
| Finished | Jul 28 04:23:21 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-4b95be28-82a8-4b73-a8de-5ca02f0954d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313189109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.313189109 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.854591750 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11111640000 ps |
| CPU time | 40.28 seconds |
| Started | Jul 28 04:21:06 PM PDT 24 |
| Finished | Jul 28 04:22:22 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-605531b6-b1cc-4b7e-8501-05a8079ddc24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854591750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.854591750 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2599419116 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14889920000 ps |
| CPU time | 51.61 seconds |
| Started | Jul 28 04:24:53 PM PDT 24 |
| Finished | Jul 28 04:26:30 PM PDT 24 |
| Peak memory | 143280 kb |
| Host | smart-7f759c3f-3bfc-4bb8-86d8-e564af8607ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599419116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2599419116 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2794328433 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 15098240000 ps |
| CPU time | 55.64 seconds |
| Started | Jul 28 04:22:57 PM PDT 24 |
| Finished | Jul 28 04:24:43 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-575fb6c4-6928-4448-b640-9bff6ba8f6b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794328433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2794328433 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.371902702 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11280900000 ps |
| CPU time | 41.81 seconds |
| Started | Jul 28 04:21:25 PM PDT 24 |
| Finished | Jul 28 04:22:44 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-624f3a6e-1465-4e6b-8614-5bc9ed3e4d43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371902702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.371902702 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3117191570 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6121880000 ps |
| CPU time | 21.33 seconds |
| Started | Jul 28 04:25:32 PM PDT 24 |
| Finished | Jul 28 04:26:12 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-a9159541-18e0-4945-b661-3a11ccc70e3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3117191570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3117191570 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1095031412 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9605040000 ps |
| CPU time | 31.7 seconds |
| Started | Jul 28 04:22:21 PM PDT 24 |
| Finished | Jul 28 04:23:20 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-8885ea0f-44e9-4eb0-b26f-8775e0d9e541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095031412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1095031412 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3418941596 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12727360000 ps |
| CPU time | 44.99 seconds |
| Started | Jul 28 04:25:32 PM PDT 24 |
| Finished | Jul 28 04:26:56 PM PDT 24 |
| Peak memory | 144580 kb |
| Host | smart-487b9b16-bcf8-4dec-96e9-6d2d31763baf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418941596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3418941596 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3521343316 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10283320000 ps |
| CPU time | 36.06 seconds |
| Started | Jul 28 04:25:32 PM PDT 24 |
| Finished | Jul 28 04:26:39 PM PDT 24 |
| Peak memory | 144608 kb |
| Host | smart-e1a43e66-c2f8-4354-89d2-2b20a37e4cf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521343316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3521343316 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3308088095 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3107440000 ps |
| CPU time | 10.97 seconds |
| Started | Jul 28 04:25:38 PM PDT 24 |
| Finished | Jul 28 04:25:58 PM PDT 24 |
| Peak memory | 144844 kb |
| Host | smart-ce25e9bd-6d67-4f24-bdac-df8477acc811 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308088095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3308088095 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1846221102 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12137120000 ps |
| CPU time | 42.56 seconds |
| Started | Jul 28 04:25:31 PM PDT 24 |
| Finished | Jul 28 04:26:50 PM PDT 24 |
| Peak memory | 144032 kb |
| Host | smart-8171b342-6910-490b-bfd0-f6224c93b088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846221102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1846221102 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3847857639 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6168380000 ps |
| CPU time | 21.65 seconds |
| Started | Jul 28 04:24:48 PM PDT 24 |
| Finished | Jul 28 04:25:29 PM PDT 24 |
| Peak memory | 143628 kb |
| Host | smart-6d6681a0-3a6e-4266-ac53-92c90b3c0115 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3847857639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3847857639 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4098716331 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6518060000 ps |
| CPU time | 26.38 seconds |
| Started | Jul 28 04:21:43 PM PDT 24 |
| Finished | Jul 28 04:22:33 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-8ba62aa6-70c4-4d6a-a342-62da72bb597f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098716331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4098716331 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4206459572 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 15088320000 ps |
| CPU time | 47.55 seconds |
| Started | Jul 28 04:25:06 PM PDT 24 |
| Finished | Jul 28 04:26:33 PM PDT 24 |
| Peak memory | 144264 kb |
| Host | smart-169af05c-69f8-43e5-9d06-8250a9ef94cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206459572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4206459572 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.363302587 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8964580000 ps |
| CPU time | 29.11 seconds |
| Started | Jul 28 04:25:07 PM PDT 24 |
| Finished | Jul 28 04:26:01 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-21fbb654-11ba-4db1-9db0-4101f6b4f4ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363302587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.363302587 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3403053159 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4297220000 ps |
| CPU time | 15.26 seconds |
| Started | Jul 28 04:21:15 PM PDT 24 |
| Finished | Jul 28 04:21:44 PM PDT 24 |
| Peak memory | 143588 kb |
| Host | smart-a0b46e42-cd1b-405d-8807-4381e595b9f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403053159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3403053159 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1333865171 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13744780000 ps |
| CPU time | 50.21 seconds |
| Started | Jul 28 04:21:15 PM PDT 24 |
| Finished | Jul 28 04:22:51 PM PDT 24 |
| Peak memory | 143392 kb |
| Host | smart-ddaa7f6e-70bb-4657-bba9-86318f6e1d1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1333865171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1333865171 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3827706021 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4082080000 ps |
| CPU time | 15.13 seconds |
| Started | Jul 28 04:21:25 PM PDT 24 |
| Finished | Jul 28 04:21:54 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-7d3c692f-7cdf-4cfc-b375-e76deac25b2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3827706021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3827706021 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4211082447 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6213640000 ps |
| CPU time | 22.29 seconds |
| Started | Jul 28 04:21:24 PM PDT 24 |
| Finished | Jul 28 04:22:07 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-136daeec-9846-4681-a4d4-8d5381fc810c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211082447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4211082447 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2569862267 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12189820000 ps |
| CPU time | 43.63 seconds |
| Started | Jul 28 04:20:26 PM PDT 24 |
| Finished | Jul 28 04:21:48 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-1f47bfec-8a5f-4c43-b422-60d276aff1b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569862267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2569862267 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |