| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.3363768372 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.2721285693 |
| /workspace/coverage/default/10.prim_present_test.2640110218 |
| /workspace/coverage/default/11.prim_present_test.601375992 |
| /workspace/coverage/default/12.prim_present_test.1072773850 |
| /workspace/coverage/default/13.prim_present_test.1960082422 |
| /workspace/coverage/default/14.prim_present_test.808094288 |
| /workspace/coverage/default/15.prim_present_test.4163095923 |
| /workspace/coverage/default/16.prim_present_test.175417871 |
| /workspace/coverage/default/17.prim_present_test.1623610793 |
| /workspace/coverage/default/18.prim_present_test.889490741 |
| /workspace/coverage/default/19.prim_present_test.1954344008 |
| /workspace/coverage/default/2.prim_present_test.70927433 |
| /workspace/coverage/default/20.prim_present_test.482622496 |
| /workspace/coverage/default/21.prim_present_test.2549321569 |
| /workspace/coverage/default/22.prim_present_test.2289880962 |
| /workspace/coverage/default/23.prim_present_test.3529569033 |
| /workspace/coverage/default/24.prim_present_test.3284581108 |
| /workspace/coverage/default/25.prim_present_test.3082107633 |
| /workspace/coverage/default/26.prim_present_test.1202150782 |
| /workspace/coverage/default/27.prim_present_test.4080146663 |
| /workspace/coverage/default/28.prim_present_test.1931368846 |
| /workspace/coverage/default/29.prim_present_test.890210970 |
| /workspace/coverage/default/3.prim_present_test.801129742 |
| /workspace/coverage/default/30.prim_present_test.1351387863 |
| /workspace/coverage/default/31.prim_present_test.1714367500 |
| /workspace/coverage/default/32.prim_present_test.715636651 |
| /workspace/coverage/default/33.prim_present_test.192624929 |
| /workspace/coverage/default/34.prim_present_test.3864369605 |
| /workspace/coverage/default/35.prim_present_test.2697374295 |
| /workspace/coverage/default/36.prim_present_test.955000011 |
| /workspace/coverage/default/37.prim_present_test.737100910 |
| /workspace/coverage/default/38.prim_present_test.1588209028 |
| /workspace/coverage/default/39.prim_present_test.1083684920 |
| /workspace/coverage/default/4.prim_present_test.1599478368 |
| /workspace/coverage/default/40.prim_present_test.1080977047 |
| /workspace/coverage/default/41.prim_present_test.3683175605 |
| /workspace/coverage/default/42.prim_present_test.1671620057 |
| /workspace/coverage/default/43.prim_present_test.3357086369 |
| /workspace/coverage/default/44.prim_present_test.1262385472 |
| /workspace/coverage/default/45.prim_present_test.1978852390 |
| /workspace/coverage/default/46.prim_present_test.1160775192 |
| /workspace/coverage/default/47.prim_present_test.4091390916 |
| /workspace/coverage/default/48.prim_present_test.3579367856 |
| /workspace/coverage/default/49.prim_present_test.3915672907 |
| /workspace/coverage/default/5.prim_present_test.3945696571 |
| /workspace/coverage/default/6.prim_present_test.1432770502 |
| /workspace/coverage/default/7.prim_present_test.3225239905 |
| /workspace/coverage/default/8.prim_present_test.2569192448 |
| /workspace/coverage/default/9.prim_present_test.1472754850 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_present_test.3363768372 | Jul 29 06:38:11 PM PDT 24 | Jul 29 06:39:24 PM PDT 24 | 14046720000 ps | ||
| T2 | /workspace/coverage/default/15.prim_present_test.4163095923 | Jul 29 06:39:07 PM PDT 24 | Jul 29 06:40:45 PM PDT 24 | 13270480000 ps | ||
| T3 | /workspace/coverage/default/21.prim_present_test.2549321569 | Jul 29 06:39:06 PM PDT 24 | Jul 29 06:40:40 PM PDT 24 | 14211640000 ps | ||
| T4 | /workspace/coverage/default/35.prim_present_test.2697374295 | Jul 29 06:38:40 PM PDT 24 | Jul 29 06:39:40 PM PDT 24 | 7833080000 ps | ||
| T5 | /workspace/coverage/default/14.prim_present_test.808094288 | Jul 29 06:39:05 PM PDT 24 | Jul 29 06:40:39 PM PDT 24 | 12528960000 ps | ||
| T6 | /workspace/coverage/default/24.prim_present_test.3284581108 | Jul 29 06:39:09 PM PDT 24 | Jul 29 06:40:32 PM PDT 24 | 12268560000 ps | ||
| T7 | /workspace/coverage/default/7.prim_present_test.3225239905 | Jul 29 06:38:27 PM PDT 24 | Jul 29 06:39:59 PM PDT 24 | 12665980000 ps | ||
| T8 | /workspace/coverage/default/46.prim_present_test.1160775192 | Jul 29 06:38:46 PM PDT 24 | Jul 29 06:39:14 PM PDT 24 | 4904200000 ps | ||
| T9 | /workspace/coverage/default/10.prim_present_test.2640110218 | Jul 29 06:39:06 PM PDT 24 | Jul 29 06:40:17 PM PDT 24 | 11948020000 ps | ||
| T10 | /workspace/coverage/default/42.prim_present_test.1671620057 | Jul 29 06:38:42 PM PDT 24 | Jul 29 06:39:41 PM PDT 24 | 11003760000 ps | ||
| T11 | /workspace/coverage/default/34.prim_present_test.3864369605 | Jul 29 06:38:41 PM PDT 24 | Jul 29 06:39:21 PM PDT 24 | 5991060000 ps | ||
| T12 | /workspace/coverage/default/33.prim_present_test.192624929 | Jul 29 06:38:40 PM PDT 24 | Jul 29 06:40:09 PM PDT 24 | 13096880000 ps | ||
| T13 | /workspace/coverage/default/45.prim_present_test.1978852390 | Jul 29 06:38:41 PM PDT 24 | Jul 29 06:39:17 PM PDT 24 | 5835440000 ps | ||
| T14 | /workspace/coverage/default/8.prim_present_test.2569192448 | Jul 29 06:38:32 PM PDT 24 | Jul 29 06:39:40 PM PDT 24 | 8374960000 ps | ||
| T15 | /workspace/coverage/default/20.prim_present_test.482622496 | Jul 29 06:39:07 PM PDT 24 | Jul 29 06:39:52 PM PDT 24 | 5938360000 ps | ||
| T16 | /workspace/coverage/default/49.prim_present_test.3915672907 | Jul 29 06:38:46 PM PDT 24 | Jul 29 06:39:09 PM PDT 24 | 3902280000 ps | ||
| T17 | /workspace/coverage/default/19.prim_present_test.1954344008 | Jul 29 06:39:09 PM PDT 24 | Jul 29 06:39:33 PM PDT 24 | 3945060000 ps | ||
| T18 | /workspace/coverage/default/16.prim_present_test.175417871 | Jul 29 06:39:05 PM PDT 24 | Jul 29 06:39:49 PM PDT 24 | 5230940000 ps | ||
| T19 | /workspace/coverage/default/29.prim_present_test.890210970 | Jul 29 06:38:41 PM PDT 24 | Jul 29 06:39:28 PM PDT 24 | 7595000000 ps | ||
| T20 | /workspace/coverage/default/9.prim_present_test.1472754850 | Jul 29 06:38:30 PM PDT 24 | Jul 29 06:38:59 PM PDT 24 | 5470880000 ps | ||
| T21 | /workspace/coverage/default/5.prim_present_test.3945696571 | Jul 29 06:38:25 PM PDT 24 | Jul 29 06:39:39 PM PDT 24 | 11398700000 ps | ||
| T22 | /workspace/coverage/default/47.prim_present_test.4091390916 | Jul 29 06:38:46 PM PDT 24 | Jul 29 06:39:40 PM PDT 24 | 9929920000 ps | ||
| T23 | /workspace/coverage/default/4.prim_present_test.1599478368 | Jul 29 06:38:25 PM PDT 24 | Jul 29 06:40:07 PM PDT 24 | 15032520000 ps | ||
| T24 | /workspace/coverage/default/27.prim_present_test.4080146663 | Jul 29 06:38:40 PM PDT 24 | Jul 29 06:40:00 PM PDT 24 | 13057820000 ps | ||
| T25 | /workspace/coverage/default/31.prim_present_test.1714367500 | Jul 29 06:38:42 PM PDT 24 | Jul 29 06:39:26 PM PDT 24 | 6425680000 ps | ||
| T26 | /workspace/coverage/default/37.prim_present_test.737100910 | Jul 29 06:38:42 PM PDT 24 | Jul 29 06:39:39 PM PDT 24 | 9205760000 ps | ||
| T27 | /workspace/coverage/default/44.prim_present_test.1262385472 | Jul 29 06:38:43 PM PDT 24 | Jul 29 06:40:21 PM PDT 24 | 14307120000 ps | ||
| T28 | /workspace/coverage/default/41.prim_present_test.3683175605 | Jul 29 06:38:41 PM PDT 24 | Jul 29 06:40:08 PM PDT 24 | 12591580000 ps | ||
| T29 | /workspace/coverage/default/38.prim_present_test.1588209028 | Jul 29 06:38:41 PM PDT 24 | Jul 29 06:40:24 PM PDT 24 | 14930840000 ps | ||
| T30 | /workspace/coverage/default/26.prim_present_test.1202150782 | Jul 29 06:38:41 PM PDT 24 | Jul 29 06:40:11 PM PDT 24 | 15440480000 ps | ||
| T31 | /workspace/coverage/default/17.prim_present_test.1623610793 | Jul 29 06:39:06 PM PDT 24 | Jul 29 06:40:45 PM PDT 24 | 14884960000 ps | ||
| T32 | /workspace/coverage/default/18.prim_present_test.889490741 | Jul 29 06:39:07 PM PDT 24 | Jul 29 06:40:48 PM PDT 24 | 13724940000 ps | ||
| T33 | /workspace/coverage/default/22.prim_present_test.2289880962 | Jul 29 06:39:09 PM PDT 24 | Jul 29 06:40:33 PM PDT 24 | 12370240000 ps | ||
| T34 | /workspace/coverage/default/48.prim_present_test.3579367856 | Jul 29 06:38:47 PM PDT 24 | Jul 29 06:40:12 PM PDT 24 | 10870460000 ps | ||
| T35 | /workspace/coverage/default/11.prim_present_test.601375992 | Jul 29 06:39:04 PM PDT 24 | Jul 29 06:40:07 PM PDT 24 | 10355860000 ps | ||
| T36 | /workspace/coverage/default/36.prim_present_test.955000011 | Jul 29 06:38:42 PM PDT 24 | Jul 29 06:39:26 PM PDT 24 | 8356980000 ps | ||
| T37 | /workspace/coverage/default/39.prim_present_test.1083684920 | Jul 29 06:38:41 PM PDT 24 | Jul 29 06:40:21 PM PDT 24 | 12318160000 ps | ||
| T38 | /workspace/coverage/default/28.prim_present_test.1931368846 | Jul 29 06:38:44 PM PDT 24 | Jul 29 06:39:23 PM PDT 24 | 6314700000 ps | ||
| T39 | /workspace/coverage/default/30.prim_present_test.1351387863 | Jul 29 06:38:41 PM PDT 24 | Jul 29 06:39:06 PM PDT 24 | 3916540000 ps | ||
| T40 | /workspace/coverage/default/23.prim_present_test.3529569033 | Jul 29 06:39:07 PM PDT 24 | Jul 29 06:40:36 PM PDT 24 | 11969720000 ps | ||
| T41 | /workspace/coverage/default/2.prim_present_test.70927433 | Jul 29 06:38:21 PM PDT 24 | Jul 29 06:38:43 PM PDT 24 | 3642500000 ps | ||
| T42 | /workspace/coverage/default/12.prim_present_test.1072773850 | Jul 29 06:39:07 PM PDT 24 | Jul 29 06:39:36 PM PDT 24 | 4881260000 ps | ||
| T43 | /workspace/coverage/default/25.prim_present_test.3082107633 | Jul 29 06:39:07 PM PDT 24 | Jul 29 06:40:12 PM PDT 24 | 8525620000 ps | ||
| T44 | /workspace/coverage/default/40.prim_present_test.1080977047 | Jul 29 06:38:42 PM PDT 24 | Jul 29 06:40:09 PM PDT 24 | 10158700000 ps | ||
| T45 | /workspace/coverage/default/13.prim_present_test.1960082422 | Jul 29 06:38:39 PM PDT 24 | Jul 29 06:39:06 PM PDT 24 | 4087660000 ps | ||
| T46 | /workspace/coverage/default/3.prim_present_test.801129742 | Jul 29 06:38:12 PM PDT 24 | Jul 29 06:39:01 PM PDT 24 | 7821300000 ps | ||
| T47 | /workspace/coverage/default/32.prim_present_test.715636651 | Jul 29 06:38:42 PM PDT 24 | Jul 29 06:40:18 PM PDT 24 | 11565480000 ps | ||
| T48 | /workspace/coverage/default/1.prim_present_test.2721285693 | Jul 29 06:38:14 PM PDT 24 | Jul 29 06:38:52 PM PDT 24 | 6009040000 ps | ||
| T49 | /workspace/coverage/default/43.prim_present_test.3357086369 | Jul 29 06:38:41 PM PDT 24 | Jul 29 06:39:05 PM PDT 24 | 3882440000 ps | ||
| T50 | /workspace/coverage/default/6.prim_present_test.1432770502 | Jul 29 06:38:26 PM PDT 24 | Jul 29 06:39:28 PM PDT 24 | 9964640000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.3363768372 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14046720000 ps |
| CPU time | 38.64 seconds |
| Started | Jul 29 06:38:11 PM PDT 24 |
| Finished | Jul 29 06:39:24 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-3ad9f83c-6462-4cc6-ba99-c9cba07011a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363768372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3363768372 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2721285693 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6009040000 ps |
| CPU time | 19.88 seconds |
| Started | Jul 29 06:38:14 PM PDT 24 |
| Finished | Jul 29 06:38:52 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-a6afbb1c-2e5f-4983-85c9-e8b145581bae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721285693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2721285693 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2640110218 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11948020000 ps |
| CPU time | 37.59 seconds |
| Started | Jul 29 06:39:06 PM PDT 24 |
| Finished | Jul 29 06:40:17 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-238c7741-5e1a-4ea9-9199-a6925b3e66c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640110218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2640110218 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.601375992 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10355860000 ps |
| CPU time | 33.2 seconds |
| Started | Jul 29 06:39:04 PM PDT 24 |
| Finished | Jul 29 06:40:07 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-37e36edb-4720-4660-b54d-7da35a487e6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601375992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.601375992 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1072773850 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4881260000 ps |
| CPU time | 15.73 seconds |
| Started | Jul 29 06:39:07 PM PDT 24 |
| Finished | Jul 29 06:39:36 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-0cbd636e-4983-4c69-b7bb-7a9ba24d0772 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072773850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1072773850 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1960082422 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4087660000 ps |
| CPU time | 14.55 seconds |
| Started | Jul 29 06:38:39 PM PDT 24 |
| Finished | Jul 29 06:39:06 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-f972ca71-cfce-4544-9524-ec2f7c41e124 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960082422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1960082422 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.808094288 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12528960000 ps |
| CPU time | 48.29 seconds |
| Started | Jul 29 06:39:05 PM PDT 24 |
| Finished | Jul 29 06:40:39 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-8d658c94-36e1-41cb-93a7-e58989d33f9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=808094288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.808094288 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.4163095923 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13270480000 ps |
| CPU time | 49.88 seconds |
| Started | Jul 29 06:39:07 PM PDT 24 |
| Finished | Jul 29 06:40:45 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-db0de88e-e756-412d-8cab-702458c688cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163095923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.4163095923 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.175417871 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5230940000 ps |
| CPU time | 22.13 seconds |
| Started | Jul 29 06:39:05 PM PDT 24 |
| Finished | Jul 29 06:39:49 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-f3ec30f8-3ef9-47f2-b8f1-8eab3c30803e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175417871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.175417871 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1623610793 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14884960000 ps |
| CPU time | 51.96 seconds |
| Started | Jul 29 06:39:06 PM PDT 24 |
| Finished | Jul 29 06:40:45 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-6ced4c0c-c2e7-4ff8-8975-c6096465d084 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623610793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1623610793 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.889490741 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13724940000 ps |
| CPU time | 51.85 seconds |
| Started | Jul 29 06:39:07 PM PDT 24 |
| Finished | Jul 29 06:40:48 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-3d60ed40-32e6-4a29-b3f3-e6296572bcf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889490741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.889490741 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1954344008 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3945060000 ps |
| CPU time | 13.38 seconds |
| Started | Jul 29 06:39:09 PM PDT 24 |
| Finished | Jul 29 06:39:33 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-c0afc0b9-0695-42a9-812d-86d73ad0cf02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954344008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1954344008 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.70927433 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3642500000 ps |
| CPU time | 11.58 seconds |
| Started | Jul 29 06:38:21 PM PDT 24 |
| Finished | Jul 29 06:38:43 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-0d51cdeb-a07f-4b46-868d-e95c61747fcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70927433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.70927433 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.482622496 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5938360000 ps |
| CPU time | 22.46 seconds |
| Started | Jul 29 06:39:07 PM PDT 24 |
| Finished | Jul 29 06:39:52 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-b80eaba8-fd70-47aa-9afd-fe26c3ac2b6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482622496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.482622496 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2549321569 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 14211640000 ps |
| CPU time | 49.28 seconds |
| Started | Jul 29 06:39:06 PM PDT 24 |
| Finished | Jul 29 06:40:40 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-a4692dfa-8d7e-4b80-aaad-adaef97be0d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2549321569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2549321569 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2289880962 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12370240000 ps |
| CPU time | 44.42 seconds |
| Started | Jul 29 06:39:09 PM PDT 24 |
| Finished | Jul 29 06:40:33 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-1d336eff-ff37-4388-b691-92aaefc7aef4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289880962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2289880962 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3529569033 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11969720000 ps |
| CPU time | 46.2 seconds |
| Started | Jul 29 06:39:07 PM PDT 24 |
| Finished | Jul 29 06:40:36 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-450f2d6b-36fa-48be-b8bf-013f74d92d10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529569033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3529569033 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3284581108 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12268560000 ps |
| CPU time | 44.14 seconds |
| Started | Jul 29 06:39:09 PM PDT 24 |
| Finished | Jul 29 06:40:32 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-fc6253e8-2318-4fdb-8398-313760e5e576 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3284581108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3284581108 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3082107633 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8525620000 ps |
| CPU time | 33.41 seconds |
| Started | Jul 29 06:39:07 PM PDT 24 |
| Finished | Jul 29 06:40:12 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-f7015436-d306-4c07-b6d1-884dc1827213 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082107633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3082107633 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1202150782 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 15440480000 ps |
| CPU time | 48.3 seconds |
| Started | Jul 29 06:38:41 PM PDT 24 |
| Finished | Jul 29 06:40:11 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-06ea1885-8ea1-4b9e-ad33-919829b2b28f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1202150782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1202150782 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.4080146663 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 13057820000 ps |
| CPU time | 42.84 seconds |
| Started | Jul 29 06:38:40 PM PDT 24 |
| Finished | Jul 29 06:40:00 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-ae7031d5-ef95-41eb-ae7f-93a9fc1aa186 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080146663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.4080146663 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1931368846 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6314700000 ps |
| CPU time | 21.35 seconds |
| Started | Jul 29 06:38:44 PM PDT 24 |
| Finished | Jul 29 06:39:23 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-13611e5e-75cc-44e1-9206-e4ee50c6a940 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931368846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1931368846 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.890210970 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7595000000 ps |
| CPU time | 24.87 seconds |
| Started | Jul 29 06:38:41 PM PDT 24 |
| Finished | Jul 29 06:39:28 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-169a9961-0466-4ac0-988f-b2a5db8adf20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=890210970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.890210970 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.801129742 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7821300000 ps |
| CPU time | 26.26 seconds |
| Started | Jul 29 06:38:12 PM PDT 24 |
| Finished | Jul 29 06:39:01 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-5ce03534-0d3b-4fd9-b674-925e259a887d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801129742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.801129742 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1351387863 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3916540000 ps |
| CPU time | 13.15 seconds |
| Started | Jul 29 06:38:41 PM PDT 24 |
| Finished | Jul 29 06:39:06 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-22a68d69-6a8c-40e3-91b8-8f3b75fe7195 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1351387863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1351387863 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1714367500 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6425680000 ps |
| CPU time | 23.61 seconds |
| Started | Jul 29 06:38:42 PM PDT 24 |
| Finished | Jul 29 06:39:26 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-d63c06ce-d339-4cad-95db-06825e1121dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714367500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1714367500 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.715636651 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11565480000 ps |
| CPU time | 47.08 seconds |
| Started | Jul 29 06:38:42 PM PDT 24 |
| Finished | Jul 29 06:40:18 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-985a9585-0418-464b-972e-b62d2212c96d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715636651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.715636651 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.192624929 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13096880000 ps |
| CPU time | 46.77 seconds |
| Started | Jul 29 06:38:40 PM PDT 24 |
| Finished | Jul 29 06:40:09 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-8b13abf1-abfb-4112-bbb1-7bc9457caa98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192624929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.192624929 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3864369605 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5991060000 ps |
| CPU time | 20.98 seconds |
| Started | Jul 29 06:38:41 PM PDT 24 |
| Finished | Jul 29 06:39:21 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-81154c9d-6eb6-45ca-9bc5-5105f9737bb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864369605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3864369605 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2697374295 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7833080000 ps |
| CPU time | 31.14 seconds |
| Started | Jul 29 06:38:40 PM PDT 24 |
| Finished | Jul 29 06:39:40 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-ec9fb200-a267-489c-88e7-08d66c53c2cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697374295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2697374295 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.955000011 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8356980000 ps |
| CPU time | 24.49 seconds |
| Started | Jul 29 06:38:42 PM PDT 24 |
| Finished | Jul 29 06:39:26 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-689b9a10-e281-472a-be1e-5713deca2804 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955000011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.955000011 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.737100910 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9205760000 ps |
| CPU time | 30.52 seconds |
| Started | Jul 29 06:38:42 PM PDT 24 |
| Finished | Jul 29 06:39:39 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-0c92dadd-766c-4224-be9b-f12d1b94010f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737100910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.737100910 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1588209028 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14930840000 ps |
| CPU time | 54.17 seconds |
| Started | Jul 29 06:38:41 PM PDT 24 |
| Finished | Jul 29 06:40:24 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-cdbb8ee6-91d3-454b-833d-3ef827c03d32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1588209028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1588209028 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1083684920 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12318160000 ps |
| CPU time | 50.57 seconds |
| Started | Jul 29 06:38:41 PM PDT 24 |
| Finished | Jul 29 06:40:21 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-ae946a44-790a-4987-a293-2b7956135a59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083684920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1083684920 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1599478368 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 15032520000 ps |
| CPU time | 53.7 seconds |
| Started | Jul 29 06:38:25 PM PDT 24 |
| Finished | Jul 29 06:40:07 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-c6ecfcd2-13ef-4860-93dc-6ff27ace2c3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599478368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1599478368 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1080977047 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10158700000 ps |
| CPU time | 42.31 seconds |
| Started | Jul 29 06:38:42 PM PDT 24 |
| Finished | Jul 29 06:40:09 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-1d80eeb8-6d04-48f9-80e2-b50319c5d65c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080977047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1080977047 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3683175605 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12591580000 ps |
| CPU time | 46.86 seconds |
| Started | Jul 29 06:38:41 PM PDT 24 |
| Finished | Jul 29 06:40:08 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-2e325782-edda-4a07-98a4-f7789254ea99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683175605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3683175605 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1671620057 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11003760000 ps |
| CPU time | 31.87 seconds |
| Started | Jul 29 06:38:42 PM PDT 24 |
| Finished | Jul 29 06:39:41 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-0b73216c-021c-4969-b4e8-9495be46d9f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671620057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1671620057 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3357086369 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3882440000 ps |
| CPU time | 13.26 seconds |
| Started | Jul 29 06:38:41 PM PDT 24 |
| Finished | Jul 29 06:39:05 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-e8a3e217-3478-4000-a9de-35978aa2cdc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357086369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3357086369 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1262385472 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14307120000 ps |
| CPU time | 52.51 seconds |
| Started | Jul 29 06:38:43 PM PDT 24 |
| Finished | Jul 29 06:40:21 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-c9e4056a-a817-48ce-bdef-c18d2174b4d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262385472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1262385472 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1978852390 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5835440000 ps |
| CPU time | 18.88 seconds |
| Started | Jul 29 06:38:41 PM PDT 24 |
| Finished | Jul 29 06:39:17 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-cb6312a4-fd4d-4630-91d8-9d7d240d70be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978852390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1978852390 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1160775192 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4904200000 ps |
| CPU time | 14.91 seconds |
| Started | Jul 29 06:38:46 PM PDT 24 |
| Finished | Jul 29 06:39:14 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-1fa95810-b129-4d9d-8e74-0570fefe889f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160775192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1160775192 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4091390916 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9929920000 ps |
| CPU time | 28.69 seconds |
| Started | Jul 29 06:38:46 PM PDT 24 |
| Finished | Jul 29 06:39:40 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-39e3316a-4d7e-40ec-af22-22284d1283b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091390916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4091390916 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3579367856 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10870460000 ps |
| CPU time | 43.61 seconds |
| Started | Jul 29 06:38:47 PM PDT 24 |
| Finished | Jul 29 06:40:12 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-9e456a84-feae-4b28-a83e-6e2a75e05bf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579367856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3579367856 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3915672907 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3902280000 ps |
| CPU time | 12.53 seconds |
| Started | Jul 29 06:38:46 PM PDT 24 |
| Finished | Jul 29 06:39:09 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-02e7f501-bcdf-4d69-80e5-753fb6f54a2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915672907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3915672907 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3945696571 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11398700000 ps |
| CPU time | 39.84 seconds |
| Started | Jul 29 06:38:25 PM PDT 24 |
| Finished | Jul 29 06:39:39 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-901a7d5f-7f53-49ad-9e72-3064314946c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945696571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3945696571 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1432770502 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 9964640000 ps |
| CPU time | 33.12 seconds |
| Started | Jul 29 06:38:26 PM PDT 24 |
| Finished | Jul 29 06:39:28 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-a6b16160-1cc0-4155-ad24-25e8b11a52b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432770502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1432770502 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3225239905 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12665980000 ps |
| CPU time | 49.41 seconds |
| Started | Jul 29 06:38:27 PM PDT 24 |
| Finished | Jul 29 06:39:59 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-7d74710a-7472-404b-ab56-0748235f6d5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225239905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3225239905 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2569192448 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8374960000 ps |
| CPU time | 35.74 seconds |
| Started | Jul 29 06:38:32 PM PDT 24 |
| Finished | Jul 29 06:39:40 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-d98fe4dc-588a-4891-bfa4-f22c17e8a286 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569192448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2569192448 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1472754850 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5470880000 ps |
| CPU time | 15.68 seconds |
| Started | Jul 29 06:38:30 PM PDT 24 |
| Finished | Jul 29 06:38:59 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-963dcd62-31a2-4c3b-ad15-ba4cc1ec252e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472754850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1472754850 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |