| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.3408034608 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1998781831 |
| /workspace/coverage/default/1.prim_present_test.2132220220 |
| /workspace/coverage/default/10.prim_present_test.2539286590 |
| /workspace/coverage/default/12.prim_present_test.3787427961 |
| /workspace/coverage/default/13.prim_present_test.1209838926 |
| /workspace/coverage/default/14.prim_present_test.3590096660 |
| /workspace/coverage/default/15.prim_present_test.3712086405 |
| /workspace/coverage/default/16.prim_present_test.2879537986 |
| /workspace/coverage/default/17.prim_present_test.2369322605 |
| /workspace/coverage/default/18.prim_present_test.273669186 |
| /workspace/coverage/default/19.prim_present_test.2235478135 |
| /workspace/coverage/default/2.prim_present_test.3444209684 |
| /workspace/coverage/default/20.prim_present_test.3345612266 |
| /workspace/coverage/default/21.prim_present_test.768397692 |
| /workspace/coverage/default/22.prim_present_test.1227719695 |
| /workspace/coverage/default/23.prim_present_test.86367280 |
| /workspace/coverage/default/24.prim_present_test.1092938199 |
| /workspace/coverage/default/25.prim_present_test.3477423928 |
| /workspace/coverage/default/26.prim_present_test.963303186 |
| /workspace/coverage/default/27.prim_present_test.2843821665 |
| /workspace/coverage/default/28.prim_present_test.1612343929 |
| /workspace/coverage/default/29.prim_present_test.3533139686 |
| /workspace/coverage/default/3.prim_present_test.357303643 |
| /workspace/coverage/default/30.prim_present_test.537392142 |
| /workspace/coverage/default/31.prim_present_test.3025136715 |
| /workspace/coverage/default/32.prim_present_test.297553148 |
| /workspace/coverage/default/33.prim_present_test.3633056074 |
| /workspace/coverage/default/34.prim_present_test.927738533 |
| /workspace/coverage/default/35.prim_present_test.3906483299 |
| /workspace/coverage/default/36.prim_present_test.2996472771 |
| /workspace/coverage/default/37.prim_present_test.958263959 |
| /workspace/coverage/default/38.prim_present_test.1557382753 |
| /workspace/coverage/default/39.prim_present_test.3099914854 |
| /workspace/coverage/default/4.prim_present_test.597567811 |
| /workspace/coverage/default/40.prim_present_test.2537732829 |
| /workspace/coverage/default/41.prim_present_test.3550280777 |
| /workspace/coverage/default/42.prim_present_test.704226618 |
| /workspace/coverage/default/43.prim_present_test.628707569 |
| /workspace/coverage/default/44.prim_present_test.2361240780 |
| /workspace/coverage/default/45.prim_present_test.3102952088 |
| /workspace/coverage/default/46.prim_present_test.981291718 |
| /workspace/coverage/default/47.prim_present_test.4167278977 |
| /workspace/coverage/default/48.prim_present_test.2624174952 |
| /workspace/coverage/default/49.prim_present_test.471082745 |
| /workspace/coverage/default/5.prim_present_test.2282103546 |
| /workspace/coverage/default/6.prim_present_test.2223462053 |
| /workspace/coverage/default/7.prim_present_test.3426880647 |
| /workspace/coverage/default/8.prim_present_test.3212381632 |
| /workspace/coverage/default/9.prim_present_test.118498829 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/35.prim_present_test.3906483299 | Jul 30 05:19:45 PM PDT 24 | Jul 30 05:21:15 PM PDT 24 | 11911440000 ps | ||
| T2 | /workspace/coverage/default/43.prim_present_test.628707569 | Jul 30 05:19:50 PM PDT 24 | Jul 30 05:20:32 PM PDT 24 | 5260700000 ps | ||
| T3 | /workspace/coverage/default/34.prim_present_test.927738533 | Jul 30 05:19:44 PM PDT 24 | Jul 30 05:20:25 PM PDT 24 | 5584960000 ps | ||
| T4 | /workspace/coverage/default/47.prim_present_test.4167278977 | Jul 30 05:19:49 PM PDT 24 | Jul 30 05:21:11 PM PDT 24 | 13620160000 ps | ||
| T5 | /workspace/coverage/default/38.prim_present_test.1557382753 | Jul 30 05:19:51 PM PDT 24 | Jul 30 05:20:35 PM PDT 24 | 4656200000 ps | ||
| T6 | /workspace/coverage/default/29.prim_present_test.3533139686 | Jul 30 05:19:43 PM PDT 24 | Jul 30 05:21:19 PM PDT 24 | 12311960000 ps | ||
| T7 | /workspace/coverage/default/3.prim_present_test.357303643 | Jul 30 05:19:31 PM PDT 24 | Jul 30 05:20:14 PM PDT 24 | 7449920000 ps | ||
| T8 | /workspace/coverage/default/21.prim_present_test.768397692 | Jul 30 05:19:42 PM PDT 24 | Jul 30 05:20:56 PM PDT 24 | 8965820000 ps | ||
| T9 | /workspace/coverage/default/26.prim_present_test.963303186 | Jul 30 05:19:41 PM PDT 24 | Jul 30 05:21:23 PM PDT 24 | 12675280000 ps | ||
| T10 | /workspace/coverage/default/11.prim_present_test.3408034608 | Jul 30 05:19:37 PM PDT 24 | Jul 30 05:21:03 PM PDT 24 | 11688860000 ps | ||
| T11 | /workspace/coverage/default/45.prim_present_test.3102952088 | Jul 30 05:19:50 PM PDT 24 | Jul 30 05:21:13 PM PDT 24 | 12771380000 ps | ||
| T12 | /workspace/coverage/default/4.prim_present_test.597567811 | Jul 30 05:19:33 PM PDT 24 | Jul 30 05:20:34 PM PDT 24 | 8880880000 ps | ||
| T13 | /workspace/coverage/default/40.prim_present_test.2537732829 | Jul 30 05:19:52 PM PDT 24 | Jul 30 05:21:02 PM PDT 24 | 7843620000 ps | ||
| T14 | /workspace/coverage/default/24.prim_present_test.1092938199 | Jul 30 05:19:40 PM PDT 24 | Jul 30 05:20:45 PM PDT 24 | 10519540000 ps | ||
| T15 | /workspace/coverage/default/7.prim_present_test.3426880647 | Jul 30 05:19:33 PM PDT 24 | Jul 30 05:21:08 PM PDT 24 | 12416740000 ps | ||
| T16 | /workspace/coverage/default/14.prim_present_test.3590096660 | Jul 30 05:19:37 PM PDT 24 | Jul 30 05:20:49 PM PDT 24 | 9672000000 ps | ||
| T17 | /workspace/coverage/default/33.prim_present_test.3633056074 | Jul 30 05:19:46 PM PDT 24 | Jul 30 05:20:48 PM PDT 24 | 8742620000 ps | ||
| T18 | /workspace/coverage/default/37.prim_present_test.958263959 | Jul 30 05:19:51 PM PDT 24 | Jul 30 05:21:09 PM PDT 24 | 11316240000 ps | ||
| T19 | /workspace/coverage/default/1.prim_present_test.2132220220 | Jul 30 05:19:31 PM PDT 24 | Jul 30 05:20:56 PM PDT 24 | 15156520000 ps | ||
| T20 | /workspace/coverage/default/0.prim_present_test.1998781831 | Jul 30 05:19:32 PM PDT 24 | Jul 30 05:20:50 PM PDT 24 | 11821540000 ps | ||
| T21 | /workspace/coverage/default/15.prim_present_test.3712086405 | Jul 30 05:19:37 PM PDT 24 | Jul 30 05:20:55 PM PDT 24 | 10708640000 ps | ||
| T22 | /workspace/coverage/default/32.prim_present_test.297553148 | Jul 30 05:19:44 PM PDT 24 | Jul 30 05:20:29 PM PDT 24 | 6122500000 ps | ||
| T23 | /workspace/coverage/default/25.prim_present_test.3477423928 | Jul 30 05:19:43 PM PDT 24 | Jul 30 05:21:19 PM PDT 24 | 12400620000 ps | ||
| T24 | /workspace/coverage/default/20.prim_present_test.3345612266 | Jul 30 05:19:42 PM PDT 24 | Jul 30 05:20:13 PM PDT 24 | 3920880000 ps | ||
| T25 | /workspace/coverage/default/44.prim_present_test.2361240780 | Jul 30 05:19:50 PM PDT 24 | Jul 30 05:21:14 PM PDT 24 | 13971080000 ps | ||
| T26 | /workspace/coverage/default/18.prim_present_test.273669186 | Jul 30 05:19:38 PM PDT 24 | Jul 30 05:21:09 PM PDT 24 | 14619600000 ps | ||
| T27 | /workspace/coverage/default/42.prim_present_test.704226618 | Jul 30 05:19:50 PM PDT 24 | Jul 30 05:20:50 PM PDT 24 | 6294240000 ps | ||
| T28 | /workspace/coverage/default/48.prim_present_test.2624174952 | Jul 30 05:19:53 PM PDT 24 | Jul 30 05:21:03 PM PDT 24 | 10004940000 ps | ||
| T29 | /workspace/coverage/default/27.prim_present_test.2843821665 | Jul 30 05:19:42 PM PDT 24 | Jul 30 05:20:27 PM PDT 24 | 5953860000 ps | ||
| T30 | /workspace/coverage/default/5.prim_present_test.2282103546 | Jul 30 05:19:32 PM PDT 24 | Jul 30 05:20:51 PM PDT 24 | 10450100000 ps | ||
| T31 | /workspace/coverage/default/41.prim_present_test.3550280777 | Jul 30 05:19:49 PM PDT 24 | Jul 30 05:21:03 PM PDT 24 | 10160560000 ps | ||
| T32 | /workspace/coverage/default/39.prim_present_test.3099914854 | Jul 30 05:19:48 PM PDT 24 | Jul 30 05:20:16 PM PDT 24 | 4932100000 ps | ||
| T33 | /workspace/coverage/default/16.prim_present_test.2879537986 | Jul 30 05:19:34 PM PDT 24 | Jul 30 05:20:23 PM PDT 24 | 6470940000 ps | ||
| T34 | /workspace/coverage/default/10.prim_present_test.2539286590 | Jul 30 05:19:37 PM PDT 24 | Jul 30 05:21:39 PM PDT 24 | 13837780000 ps | ||
| T35 | /workspace/coverage/default/23.prim_present_test.86367280 | Jul 30 05:19:41 PM PDT 24 | Jul 30 05:21:07 PM PDT 24 | 13712540000 ps | ||
| T36 | /workspace/coverage/default/31.prim_present_test.3025136715 | Jul 30 05:19:45 PM PDT 24 | Jul 30 05:20:24 PM PDT 24 | 5772820000 ps | ||
| T37 | /workspace/coverage/default/30.prim_present_test.537392142 | Jul 30 05:19:44 PM PDT 24 | Jul 30 05:20:07 PM PDT 24 | 3751000000 ps | ||
| T38 | /workspace/coverage/default/6.prim_present_test.2223462053 | Jul 30 05:19:32 PM PDT 24 | Jul 30 05:20:23 PM PDT 24 | 8767420000 ps | ||
| T39 | /workspace/coverage/default/28.prim_present_test.1612343929 | Jul 30 05:19:42 PM PDT 24 | Jul 30 05:21:32 PM PDT 24 | 14906040000 ps | ||
| T40 | /workspace/coverage/default/19.prim_present_test.2235478135 | Jul 30 05:19:43 PM PDT 24 | Jul 30 05:20:51 PM PDT 24 | 7996760000 ps | ||
| T41 | /workspace/coverage/default/17.prim_present_test.2369322605 | Jul 30 05:19:36 PM PDT 24 | Jul 30 05:20:30 PM PDT 24 | 9801580000 ps | ||
| T42 | /workspace/coverage/default/49.prim_present_test.471082745 | Jul 30 05:19:55 PM PDT 24 | Jul 30 05:20:31 PM PDT 24 | 4671700000 ps | ||
| T43 | /workspace/coverage/default/46.prim_present_test.981291718 | Jul 30 05:19:50 PM PDT 24 | Jul 30 05:20:24 PM PDT 24 | 5821180000 ps | ||
| T44 | /workspace/coverage/default/36.prim_present_test.2996472771 | Jul 30 05:19:45 PM PDT 24 | Jul 30 05:20:37 PM PDT 24 | 8126960000 ps | ||
| T45 | /workspace/coverage/default/8.prim_present_test.3212381632 | Jul 30 05:19:37 PM PDT 24 | Jul 30 05:21:03 PM PDT 24 | 12107360000 ps | ||
| T46 | /workspace/coverage/default/13.prim_present_test.1209838926 | Jul 30 05:19:37 PM PDT 24 | Jul 30 05:21:16 PM PDT 24 | 12902200000 ps | ||
| T47 | /workspace/coverage/default/9.prim_present_test.118498829 | Jul 30 05:19:36 PM PDT 24 | Jul 30 05:20:58 PM PDT 24 | 10423440000 ps | ||
| T48 | /workspace/coverage/default/22.prim_present_test.1227719695 | Jul 30 05:19:42 PM PDT 24 | Jul 30 05:20:52 PM PDT 24 | 8445640000 ps | ||
| T49 | /workspace/coverage/default/12.prim_present_test.3787427961 | Jul 30 05:19:34 PM PDT 24 | Jul 30 05:21:03 PM PDT 24 | 13210960000 ps | ||
| T50 | /workspace/coverage/default/2.prim_present_test.3444209684 | Jul 30 05:19:31 PM PDT 24 | Jul 30 05:20:52 PM PDT 24 | 10993840000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.3408034608 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11688860000 ps |
| CPU time | 44.44 seconds |
| Started | Jul 30 05:19:37 PM PDT 24 |
| Finished | Jul 30 05:21:03 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-86cb83a0-ca6e-4a0a-a933-3dcc40c53f94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408034608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3408034608 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1998781831 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11821540000 ps |
| CPU time | 41.48 seconds |
| Started | Jul 30 05:19:32 PM PDT 24 |
| Finished | Jul 30 05:20:50 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-91f34b03-9687-411e-9722-f4edd72ea468 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998781831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1998781831 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2132220220 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 15156520000 ps |
| CPU time | 45.63 seconds |
| Started | Jul 30 05:19:31 PM PDT 24 |
| Finished | Jul 30 05:20:56 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-78a9178b-4e78-4256-8e80-0659db9eb9a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132220220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2132220220 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2539286590 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13837780000 ps |
| CPU time | 60.81 seconds |
| Started | Jul 30 05:19:37 PM PDT 24 |
| Finished | Jul 30 05:21:39 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-ea3db173-afb3-47ce-a058-ffee799ebdbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2539286590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2539286590 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3787427961 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13210960000 ps |
| CPU time | 47.2 seconds |
| Started | Jul 30 05:19:34 PM PDT 24 |
| Finished | Jul 30 05:21:03 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-1c0f90af-b9e2-4361-8e5a-6e2991680162 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787427961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3787427961 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1209838926 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12902200000 ps |
| CPU time | 51.63 seconds |
| Started | Jul 30 05:19:37 PM PDT 24 |
| Finished | Jul 30 05:21:16 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-4925bffb-edfc-4811-9709-601173168daf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209838926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1209838926 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3590096660 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9672000000 ps |
| CPU time | 37.35 seconds |
| Started | Jul 30 05:19:37 PM PDT 24 |
| Finished | Jul 30 05:20:49 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-46345192-67fb-4be8-bd54-d3406017617f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590096660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3590096660 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3712086405 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10708640000 ps |
| CPU time | 39.71 seconds |
| Started | Jul 30 05:19:37 PM PDT 24 |
| Finished | Jul 30 05:20:55 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-19642970-c359-4b99-95d0-b538261b265e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712086405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3712086405 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2879537986 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6470940000 ps |
| CPU time | 25.88 seconds |
| Started | Jul 30 05:19:34 PM PDT 24 |
| Finished | Jul 30 05:20:23 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-6e65a5d5-e9b2-45b0-a16a-fc3dd60ec881 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879537986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2879537986 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2369322605 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9801580000 ps |
| CPU time | 29.49 seconds |
| Started | Jul 30 05:19:36 PM PDT 24 |
| Finished | Jul 30 05:20:30 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-93b66d55-860d-42e7-8293-c3b8cb8abdfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2369322605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2369322605 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.273669186 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14619600000 ps |
| CPU time | 47.82 seconds |
| Started | Jul 30 05:19:38 PM PDT 24 |
| Finished | Jul 30 05:21:09 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-9991dc9b-7028-4b21-90f9-86008205873b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273669186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.273669186 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2235478135 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7996760000 ps |
| CPU time | 34.08 seconds |
| Started | Jul 30 05:19:43 PM PDT 24 |
| Finished | Jul 30 05:20:51 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-b82b2cae-9c8d-47e4-8cd1-746126e968e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235478135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2235478135 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3444209684 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10993840000 ps |
| CPU time | 42.36 seconds |
| Started | Jul 30 05:19:31 PM PDT 24 |
| Finished | Jul 30 05:20:52 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-a20f3c3b-e5fa-42b5-9310-c403bc937f4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3444209684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3444209684 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3345612266 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3920880000 ps |
| CPU time | 15.29 seconds |
| Started | Jul 30 05:19:42 PM PDT 24 |
| Finished | Jul 30 05:20:13 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-8f86db55-d13f-451b-bdde-7307faf3080f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3345612266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3345612266 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.768397692 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8965820000 ps |
| CPU time | 37.61 seconds |
| Started | Jul 30 05:19:42 PM PDT 24 |
| Finished | Jul 30 05:20:56 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-1a47cc13-7938-443d-8ed7-109585674127 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768397692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.768397692 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1227719695 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8445640000 ps |
| CPU time | 35.63 seconds |
| Started | Jul 30 05:19:42 PM PDT 24 |
| Finished | Jul 30 05:20:52 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-a91d9247-267c-42f7-987f-70dc88e35307 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227719695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1227719695 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.86367280 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13712540000 ps |
| CPU time | 46.82 seconds |
| Started | Jul 30 05:19:41 PM PDT 24 |
| Finished | Jul 30 05:21:07 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-cd3fadfc-4990-4035-afd1-0a6fc6d124a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86367280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.86367280 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1092938199 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10519540000 ps |
| CPU time | 34.75 seconds |
| Started | Jul 30 05:19:40 PM PDT 24 |
| Finished | Jul 30 05:20:45 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-a9ae8410-dceb-4a4a-bcb7-553d239c5f60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092938199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1092938199 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3477423928 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12400620000 ps |
| CPU time | 50.49 seconds |
| Started | Jul 30 05:19:43 PM PDT 24 |
| Finished | Jul 30 05:21:19 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-8202a77c-baa5-415f-86be-45eba2ec8c92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3477423928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3477423928 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.963303186 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12675280000 ps |
| CPU time | 53.15 seconds |
| Started | Jul 30 05:19:41 PM PDT 24 |
| Finished | Jul 30 05:21:23 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-6f8536fd-9dc6-4a41-bcf1-61859d6c1093 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963303186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.963303186 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2843821665 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5953860000 ps |
| CPU time | 23.61 seconds |
| Started | Jul 30 05:19:42 PM PDT 24 |
| Finished | Jul 30 05:20:27 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-96f17191-a1ae-4d14-9de3-6d82576a87d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843821665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2843821665 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1612343929 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 14906040000 ps |
| CPU time | 57.54 seconds |
| Started | Jul 30 05:19:42 PM PDT 24 |
| Finished | Jul 30 05:21:32 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-28d77237-b77c-4667-b685-21298860c234 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612343929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1612343929 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3533139686 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12311960000 ps |
| CPU time | 49.27 seconds |
| Started | Jul 30 05:19:43 PM PDT 24 |
| Finished | Jul 30 05:21:19 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-7ae198a4-3888-4c20-9392-69cf2de75b98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533139686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3533139686 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.357303643 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7449920000 ps |
| CPU time | 23.39 seconds |
| Started | Jul 30 05:19:31 PM PDT 24 |
| Finished | Jul 30 05:20:14 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-0f5da7a7-d4f9-49bb-b382-228675a5243c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357303643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.357303643 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.537392142 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3751000000 ps |
| CPU time | 12.4 seconds |
| Started | Jul 30 05:19:44 PM PDT 24 |
| Finished | Jul 30 05:20:07 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-f70d7913-b100-4ef3-9de7-fe0f999af55e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537392142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.537392142 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3025136715 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5772820000 ps |
| CPU time | 20.48 seconds |
| Started | Jul 30 05:19:45 PM PDT 24 |
| Finished | Jul 30 05:20:24 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-e3ef58c8-3fc8-4776-a0fa-209d3bd785c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025136715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3025136715 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.297553148 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6122500000 ps |
| CPU time | 23.02 seconds |
| Started | Jul 30 05:19:44 PM PDT 24 |
| Finished | Jul 30 05:20:29 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-aedf2319-1caf-44f1-883c-f8d5810aa1b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=297553148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.297553148 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3633056074 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8742620000 ps |
| CPU time | 32.47 seconds |
| Started | Jul 30 05:19:46 PM PDT 24 |
| Finished | Jul 30 05:20:48 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-657796b7-b459-4c65-963c-e4db4e909999 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633056074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3633056074 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.927738533 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5584960000 ps |
| CPU time | 21.19 seconds |
| Started | Jul 30 05:19:44 PM PDT 24 |
| Finished | Jul 30 05:20:25 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-b766d335-358e-48cc-906e-41b268549bcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927738533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.927738533 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3906483299 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11911440000 ps |
| CPU time | 46.66 seconds |
| Started | Jul 30 05:19:45 PM PDT 24 |
| Finished | Jul 30 05:21:15 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-5f96c3c8-791b-4565-9e7e-1cfc227cc0fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906483299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3906483299 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2996472771 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8126960000 ps |
| CPU time | 27.3 seconds |
| Started | Jul 30 05:19:45 PM PDT 24 |
| Finished | Jul 30 05:20:37 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-3d16ca8b-db9b-46db-a2c8-7816ce308be4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996472771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2996472771 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.958263959 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11316240000 ps |
| CPU time | 40.52 seconds |
| Started | Jul 30 05:19:51 PM PDT 24 |
| Finished | Jul 30 05:21:09 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-1b7bbd99-bdd7-4b61-b970-b00f95bfbd3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958263959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.958263959 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1557382753 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4656200000 ps |
| CPU time | 21.66 seconds |
| Started | Jul 30 05:19:51 PM PDT 24 |
| Finished | Jul 30 05:20:35 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-16218420-ea5f-46f5-b1d7-bb811e272aa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1557382753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1557382753 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3099914854 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4932100000 ps |
| CPU time | 14.89 seconds |
| Started | Jul 30 05:19:48 PM PDT 24 |
| Finished | Jul 30 05:20:16 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-0e393765-2b83-4183-8710-2e2af2627763 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3099914854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3099914854 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.597567811 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8880880000 ps |
| CPU time | 32.33 seconds |
| Started | Jul 30 05:19:33 PM PDT 24 |
| Finished | Jul 30 05:20:34 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-2de85442-7195-4390-a4d7-1712ec5c17d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=597567811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.597567811 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2537732829 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7843620000 ps |
| CPU time | 34.79 seconds |
| Started | Jul 30 05:19:52 PM PDT 24 |
| Finished | Jul 30 05:21:02 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-00579008-3d63-4679-b6e0-2379c71ccd7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537732829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2537732829 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3550280777 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10160560000 ps |
| CPU time | 39.59 seconds |
| Started | Jul 30 05:19:49 PM PDT 24 |
| Finished | Jul 30 05:21:03 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-a24292fe-1a5a-40c1-b287-d852d10f634d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550280777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3550280777 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.704226618 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6294240000 ps |
| CPU time | 28.75 seconds |
| Started | Jul 30 05:19:50 PM PDT 24 |
| Finished | Jul 30 05:20:50 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-a7181942-0bd9-4709-81ae-27f51dc429fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=704226618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.704226618 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.628707569 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5260700000 ps |
| CPU time | 20.18 seconds |
| Started | Jul 30 05:19:50 PM PDT 24 |
| Finished | Jul 30 05:20:32 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-c2cc6e7c-c185-4d67-83e8-41294a01d59d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628707569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.628707569 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2361240780 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13971080000 ps |
| CPU time | 44.51 seconds |
| Started | Jul 30 05:19:50 PM PDT 24 |
| Finished | Jul 30 05:21:14 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-87144b2a-62ed-4bdb-8d38-9ef79fc1cc70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361240780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2361240780 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3102952088 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12771380000 ps |
| CPU time | 44.62 seconds |
| Started | Jul 30 05:19:50 PM PDT 24 |
| Finished | Jul 30 05:21:13 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-97e3d0b1-4f7c-4cf9-82f4-eef2e2099a1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102952088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3102952088 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.981291718 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5821180000 ps |
| CPU time | 18.71 seconds |
| Started | Jul 30 05:19:50 PM PDT 24 |
| Finished | Jul 30 05:20:24 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-643cd73d-8cc9-4279-8cd5-21ac1530ed4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981291718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.981291718 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4167278977 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13620160000 ps |
| CPU time | 44.17 seconds |
| Started | Jul 30 05:19:49 PM PDT 24 |
| Finished | Jul 30 05:21:11 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-e2be1ff1-9464-4068-9537-cf5fca2d9c88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4167278977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4167278977 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2624174952 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10004940000 ps |
| CPU time | 37.85 seconds |
| Started | Jul 30 05:19:53 PM PDT 24 |
| Finished | Jul 30 05:21:03 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-1c930f45-8e1c-4bc5-a4aa-a86d0873884d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624174952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2624174952 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.471082745 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4671700000 ps |
| CPU time | 18.59 seconds |
| Started | Jul 30 05:19:55 PM PDT 24 |
| Finished | Jul 30 05:20:31 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-dfdd84f7-9a75-44b0-a830-b1c6a3941cb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471082745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.471082745 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2282103546 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10450100000 ps |
| CPU time | 39.65 seconds |
| Started | Jul 30 05:19:32 PM PDT 24 |
| Finished | Jul 30 05:20:51 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-69d235d7-465c-4371-be72-1de0727f5e8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282103546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2282103546 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2223462053 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8767420000 ps |
| CPU time | 27.29 seconds |
| Started | Jul 30 05:19:32 PM PDT 24 |
| Finished | Jul 30 05:20:23 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-f73a0e95-8c36-4a57-ba24-ca2721812021 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223462053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2223462053 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3426880647 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12416740000 ps |
| CPU time | 48.12 seconds |
| Started | Jul 30 05:19:33 PM PDT 24 |
| Finished | Jul 30 05:21:08 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-552d75e7-355f-4420-9820-839af602b99e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426880647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3426880647 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3212381632 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12107360000 ps |
| CPU time | 44.36 seconds |
| Started | Jul 30 05:19:37 PM PDT 24 |
| Finished | Jul 30 05:21:03 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-946c821c-207d-41a1-ae18-234a99fa6eea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212381632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3212381632 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.118498829 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10423440000 ps |
| CPU time | 42.06 seconds |
| Started | Jul 30 05:19:36 PM PDT 24 |
| Finished | Jul 30 05:20:58 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-223488a3-2d71-42fd-b3fd-ab64affe4a82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118498829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.118498829 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |