| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.1839663630 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2370934972 |
| /workspace/coverage/default/1.prim_present_test.870162598 |
| /workspace/coverage/default/11.prim_present_test.3588935589 |
| /workspace/coverage/default/12.prim_present_test.328660057 |
| /workspace/coverage/default/13.prim_present_test.1901401158 |
| /workspace/coverage/default/14.prim_present_test.1660414870 |
| /workspace/coverage/default/15.prim_present_test.1415600344 |
| /workspace/coverage/default/16.prim_present_test.717587441 |
| /workspace/coverage/default/17.prim_present_test.3356018376 |
| /workspace/coverage/default/18.prim_present_test.2239871586 |
| /workspace/coverage/default/19.prim_present_test.2531717251 |
| /workspace/coverage/default/2.prim_present_test.2511065963 |
| /workspace/coverage/default/20.prim_present_test.507165203 |
| /workspace/coverage/default/21.prim_present_test.290199618 |
| /workspace/coverage/default/22.prim_present_test.1417776884 |
| /workspace/coverage/default/23.prim_present_test.1042079799 |
| /workspace/coverage/default/24.prim_present_test.3850984447 |
| /workspace/coverage/default/25.prim_present_test.1583841211 |
| /workspace/coverage/default/26.prim_present_test.3185261097 |
| /workspace/coverage/default/27.prim_present_test.2052779819 |
| /workspace/coverage/default/28.prim_present_test.1549566656 |
| /workspace/coverage/default/29.prim_present_test.1089365642 |
| /workspace/coverage/default/3.prim_present_test.3202890334 |
| /workspace/coverage/default/30.prim_present_test.333633711 |
| /workspace/coverage/default/31.prim_present_test.1454033383 |
| /workspace/coverage/default/32.prim_present_test.3953433892 |
| /workspace/coverage/default/33.prim_present_test.120284873 |
| /workspace/coverage/default/34.prim_present_test.3266034035 |
| /workspace/coverage/default/35.prim_present_test.326873044 |
| /workspace/coverage/default/36.prim_present_test.2494439757 |
| /workspace/coverage/default/37.prim_present_test.1972822446 |
| /workspace/coverage/default/38.prim_present_test.1770026396 |
| /workspace/coverage/default/39.prim_present_test.606457560 |
| /workspace/coverage/default/4.prim_present_test.2406415971 |
| /workspace/coverage/default/40.prim_present_test.1032550233 |
| /workspace/coverage/default/41.prim_present_test.459902245 |
| /workspace/coverage/default/42.prim_present_test.1304922052 |
| /workspace/coverage/default/43.prim_present_test.3681538490 |
| /workspace/coverage/default/44.prim_present_test.1296468402 |
| /workspace/coverage/default/45.prim_present_test.1233243687 |
| /workspace/coverage/default/46.prim_present_test.1753147923 |
| /workspace/coverage/default/47.prim_present_test.3970140677 |
| /workspace/coverage/default/48.prim_present_test.3032053060 |
| /workspace/coverage/default/49.prim_present_test.2453975639 |
| /workspace/coverage/default/5.prim_present_test.2626123851 |
| /workspace/coverage/default/6.prim_present_test.1844627946 |
| /workspace/coverage/default/7.prim_present_test.3102154030 |
| /workspace/coverage/default/8.prim_present_test.2248874065 |
| /workspace/coverage/default/9.prim_present_test.1936602701 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/46.prim_present_test.1753147923 | Jul 31 04:40:48 PM PDT 24 | Jul 31 04:42:14 PM PDT 24 | 13530260000 ps | ||
| T2 | /workspace/coverage/default/40.prim_present_test.1032550233 | Jul 31 04:40:44 PM PDT 24 | Jul 31 04:42:02 PM PDT 24 | 13189260000 ps | ||
| T3 | /workspace/coverage/default/39.prim_present_test.606457560 | Jul 31 04:40:43 PM PDT 24 | Jul 31 04:41:55 PM PDT 24 | 12727980000 ps | ||
| T4 | /workspace/coverage/default/10.prim_present_test.1839663630 | Jul 31 04:41:02 PM PDT 24 | Jul 31 04:41:25 PM PDT 24 | 3950640000 ps | ||
| T5 | /workspace/coverage/default/47.prim_present_test.3970140677 | Jul 31 04:40:51 PM PDT 24 | Jul 31 04:42:14 PM PDT 24 | 14023780000 ps | ||
| T6 | /workspace/coverage/default/48.prim_present_test.3032053060 | Jul 31 04:40:50 PM PDT 24 | Jul 31 04:41:40 PM PDT 24 | 7436900000 ps | ||
| T7 | /workspace/coverage/default/38.prim_present_test.1770026396 | Jul 31 04:40:34 PM PDT 24 | Jul 31 04:41:00 PM PDT 24 | 4483220000 ps | ||
| T8 | /workspace/coverage/default/15.prim_present_test.1415600344 | Jul 31 04:40:53 PM PDT 24 | Jul 31 04:42:16 PM PDT 24 | 10387480000 ps | ||
| T9 | /workspace/coverage/default/31.prim_present_test.1454033383 | Jul 31 04:41:43 PM PDT 24 | Jul 31 04:42:17 PM PDT 24 | 5624640000 ps | ||
| T10 | /workspace/coverage/default/37.prim_present_test.1972822446 | Jul 31 04:40:38 PM PDT 24 | Jul 31 04:41:44 PM PDT 24 | 11758300000 ps | ||
| T11 | /workspace/coverage/default/11.prim_present_test.3588935589 | Jul 31 04:40:48 PM PDT 24 | Jul 31 04:42:27 PM PDT 24 | 14446620000 ps | ||
| T12 | /workspace/coverage/default/24.prim_present_test.3850984447 | Jul 31 04:40:44 PM PDT 24 | Jul 31 04:41:25 PM PDT 24 | 6940280000 ps | ||
| T13 | /workspace/coverage/default/9.prim_present_test.1936602701 | Jul 31 04:40:47 PM PDT 24 | Jul 31 04:41:30 PM PDT 24 | 6102040000 ps | ||
| T14 | /workspace/coverage/default/21.prim_present_test.290199618 | Jul 31 04:40:44 PM PDT 24 | Jul 31 04:41:45 PM PDT 24 | 7616080000 ps | ||
| T15 | /workspace/coverage/default/36.prim_present_test.2494439757 | Jul 31 04:40:47 PM PDT 24 | Jul 31 04:41:15 PM PDT 24 | 4503060000 ps | ||
| T16 | /workspace/coverage/default/42.prim_present_test.1304922052 | Jul 31 04:40:52 PM PDT 24 | Jul 31 04:41:23 PM PDT 24 | 5844740000 ps | ||
| T17 | /workspace/coverage/default/41.prim_present_test.459902245 | Jul 31 04:40:40 PM PDT 24 | Jul 31 04:41:17 PM PDT 24 | 4132920000 ps | ||
| T18 | /workspace/coverage/default/14.prim_present_test.1660414870 | Jul 31 04:40:54 PM PDT 24 | Jul 31 04:42:23 PM PDT 24 | 12436580000 ps | ||
| T19 | /workspace/coverage/default/30.prim_present_test.333633711 | Jul 31 04:41:48 PM PDT 24 | Jul 31 04:42:57 PM PDT 24 | 10872940000 ps | ||
| T20 | /workspace/coverage/default/19.prim_present_test.2531717251 | Jul 31 04:40:58 PM PDT 24 | Jul 31 04:41:57 PM PDT 24 | 10317420000 ps | ||
| T21 | /workspace/coverage/default/16.prim_present_test.717587441 | Jul 31 04:40:42 PM PDT 24 | Jul 31 04:41:06 PM PDT 24 | 4354260000 ps | ||
| T22 | /workspace/coverage/default/5.prim_present_test.2626123851 | Jul 31 04:40:45 PM PDT 24 | Jul 31 04:42:01 PM PDT 24 | 11871140000 ps | ||
| T23 | /workspace/coverage/default/17.prim_present_test.3356018376 | Jul 31 04:40:41 PM PDT 24 | Jul 31 04:42:25 PM PDT 24 | 15050500000 ps | ||
| T24 | /workspace/coverage/default/28.prim_present_test.1549566656 | Jul 31 04:40:50 PM PDT 24 | Jul 31 04:41:28 PM PDT 24 | 6524880000 ps | ||
| T25 | /workspace/coverage/default/1.prim_present_test.870162598 | Jul 31 04:40:47 PM PDT 24 | Jul 31 04:41:17 PM PDT 24 | 4940160000 ps | ||
| T26 | /workspace/coverage/default/25.prim_present_test.1583841211 | Jul 31 04:40:51 PM PDT 24 | Jul 31 04:42:28 PM PDT 24 | 15167060000 ps | ||
| T27 | /workspace/coverage/default/33.prim_present_test.120284873 | Jul 31 04:40:46 PM PDT 24 | Jul 31 04:42:10 PM PDT 24 | 12389460000 ps | ||
| T28 | /workspace/coverage/default/8.prim_present_test.2248874065 | Jul 31 04:42:15 PM PDT 24 | Jul 31 04:42:57 PM PDT 24 | 6408940000 ps | ||
| T29 | /workspace/coverage/default/29.prim_present_test.1089365642 | Jul 31 04:40:46 PM PDT 24 | Jul 31 04:41:23 PM PDT 24 | 6690420000 ps | ||
| T30 | /workspace/coverage/default/35.prim_present_test.326873044 | Jul 31 04:41:16 PM PDT 24 | Jul 31 04:41:42 PM PDT 24 | 4472060000 ps | ||
| T31 | /workspace/coverage/default/7.prim_present_test.3102154030 | Jul 31 04:40:46 PM PDT 24 | Jul 31 04:42:13 PM PDT 24 | 15118700000 ps | ||
| T32 | /workspace/coverage/default/6.prim_present_test.1844627946 | Jul 31 04:40:48 PM PDT 24 | Jul 31 04:41:40 PM PDT 24 | 8417740000 ps | ||
| T33 | /workspace/coverage/default/0.prim_present_test.2370934972 | Jul 31 04:40:38 PM PDT 24 | Jul 31 04:42:19 PM PDT 24 | 11546260000 ps | ||
| T34 | /workspace/coverage/default/32.prim_present_test.3953433892 | Jul 31 04:40:41 PM PDT 24 | Jul 31 04:42:26 PM PDT 24 | 13693940000 ps | ||
| T35 | /workspace/coverage/default/12.prim_present_test.328660057 | Jul 31 04:40:48 PM PDT 24 | Jul 31 04:41:28 PM PDT 24 | 7075440000 ps | ||
| T36 | /workspace/coverage/default/3.prim_present_test.3202890334 | Jul 31 04:40:42 PM PDT 24 | Jul 31 04:41:28 PM PDT 24 | 7211840000 ps | ||
| T37 | /workspace/coverage/default/34.prim_present_test.3266034035 | Jul 31 04:42:05 PM PDT 24 | Jul 31 04:42:29 PM PDT 24 | 3857640000 ps | ||
| T38 | /workspace/coverage/default/13.prim_present_test.1901401158 | Jul 31 04:40:41 PM PDT 24 | Jul 31 04:41:45 PM PDT 24 | 9894580000 ps | ||
| T39 | /workspace/coverage/default/2.prim_present_test.2511065963 | Jul 31 04:40:45 PM PDT 24 | Jul 31 04:41:56 PM PDT 24 | 9185920000 ps | ||
| T40 | /workspace/coverage/default/44.prim_present_test.1296468402 | Jul 31 04:40:53 PM PDT 24 | Jul 31 04:41:54 PM PDT 24 | 9365720000 ps | ||
| T41 | /workspace/coverage/default/49.prim_present_test.2453975639 | Jul 31 04:40:46 PM PDT 24 | Jul 31 04:41:37 PM PDT 24 | 8912500000 ps | ||
| T42 | /workspace/coverage/default/22.prim_present_test.1417776884 | Jul 31 04:41:02 PM PDT 24 | Jul 31 04:41:43 PM PDT 24 | 5555200000 ps | ||
| T43 | /workspace/coverage/default/27.prim_present_test.2052779819 | Jul 31 04:40:47 PM PDT 24 | Jul 31 04:41:14 PM PDT 24 | 4529100000 ps | ||
| T44 | /workspace/coverage/default/26.prim_present_test.3185261097 | Jul 31 04:40:47 PM PDT 24 | Jul 31 04:41:22 PM PDT 24 | 5245200000 ps | ||
| T45 | /workspace/coverage/default/45.prim_present_test.1233243687 | Jul 31 04:40:59 PM PDT 24 | Jul 31 04:42:18 PM PDT 24 | 12664740000 ps | ||
| T46 | /workspace/coverage/default/4.prim_present_test.2406415971 | Jul 31 04:40:44 PM PDT 24 | Jul 31 04:41:23 PM PDT 24 | 5787700000 ps | ||
| T47 | /workspace/coverage/default/23.prim_present_test.1042079799 | Jul 31 04:40:42 PM PDT 24 | Jul 31 04:41:44 PM PDT 24 | 9486000000 ps | ||
| T48 | /workspace/coverage/default/43.prim_present_test.3681538490 | Jul 31 04:40:55 PM PDT 24 | Jul 31 04:41:40 PM PDT 24 | 7530520000 ps | ||
| T49 | /workspace/coverage/default/20.prim_present_test.507165203 | Jul 31 04:40:45 PM PDT 24 | Jul 31 04:41:15 PM PDT 24 | 4778960000 ps | ||
| T50 | /workspace/coverage/default/18.prim_present_test.2239871586 | Jul 31 04:40:35 PM PDT 24 | Jul 31 04:40:57 PM PDT 24 | 3503620000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.1839663630 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3950640000 ps |
| CPU time | 12.14 seconds |
| Started | Jul 31 04:41:02 PM PDT 24 |
| Finished | Jul 31 04:41:25 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-765bdd46-9994-44a2-8039-df3fc70e737a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839663630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1839663630 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2370934972 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11546260000 ps |
| CPU time | 49.8 seconds |
| Started | Jul 31 04:40:38 PM PDT 24 |
| Finished | Jul 31 04:42:19 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-ae4d53ab-1ab3-48ab-bbc0-2b07201548e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370934972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2370934972 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.870162598 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4940160000 ps |
| CPU time | 15.85 seconds |
| Started | Jul 31 04:40:47 PM PDT 24 |
| Finished | Jul 31 04:41:17 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-0ca78693-6dae-46b6-b1b5-a469fabdd695 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870162598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.870162598 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3588935589 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14446620000 ps |
| CPU time | 52.39 seconds |
| Started | Jul 31 04:40:48 PM PDT 24 |
| Finished | Jul 31 04:42:27 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-062db06e-e614-4ac2-981a-7626a56892d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588935589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3588935589 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.328660057 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7075440000 ps |
| CPU time | 21.58 seconds |
| Started | Jul 31 04:40:48 PM PDT 24 |
| Finished | Jul 31 04:41:28 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-5e550d72-532e-4f31-ab7c-10364c0e7a60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328660057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.328660057 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1901401158 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9894580000 ps |
| CPU time | 34.45 seconds |
| Started | Jul 31 04:40:41 PM PDT 24 |
| Finished | Jul 31 04:41:45 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-ab8111bc-5025-46a8-a43f-29737a0dbe83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901401158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1901401158 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1660414870 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12436580000 ps |
| CPU time | 46.29 seconds |
| Started | Jul 31 04:40:54 PM PDT 24 |
| Finished | Jul 31 04:42:23 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-42b95bb2-3d3f-4603-94e0-edd0dfee9502 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660414870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1660414870 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1415600344 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10387480000 ps |
| CPU time | 43.17 seconds |
| Started | Jul 31 04:40:53 PM PDT 24 |
| Finished | Jul 31 04:42:16 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-bcbf797c-6409-4726-8266-eabf8c1ac7c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415600344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1415600344 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.717587441 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4354260000 ps |
| CPU time | 13.48 seconds |
| Started | Jul 31 04:40:42 PM PDT 24 |
| Finished | Jul 31 04:41:06 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-6baada0d-faf6-4aa7-8d9e-2bdd969482a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=717587441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.717587441 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3356018376 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 15050500000 ps |
| CPU time | 54.59 seconds |
| Started | Jul 31 04:40:41 PM PDT 24 |
| Finished | Jul 31 04:42:25 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-007e56ce-1538-4153-a507-9c9aa1729cde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3356018376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3356018376 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2239871586 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3503620000 ps |
| CPU time | 11.85 seconds |
| Started | Jul 31 04:40:35 PM PDT 24 |
| Finished | Jul 31 04:40:57 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-4a435279-e1ee-4e8c-9407-5eec7c38f8b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239871586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2239871586 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2531717251 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10317420000 ps |
| CPU time | 31.96 seconds |
| Started | Jul 31 04:40:58 PM PDT 24 |
| Finished | Jul 31 04:41:57 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-cd69763f-9356-4258-8dec-7ce1d536cb56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2531717251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2531717251 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2511065963 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9185920000 ps |
| CPU time | 37.5 seconds |
| Started | Jul 31 04:40:45 PM PDT 24 |
| Finished | Jul 31 04:41:56 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-fe598c5b-76fb-4da1-ac4c-9bb06b8a05a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511065963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2511065963 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.507165203 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4778960000 ps |
| CPU time | 15.88 seconds |
| Started | Jul 31 04:40:45 PM PDT 24 |
| Finished | Jul 31 04:41:15 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-7ca376c5-c203-4d69-9be5-1fddb4cbdeea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507165203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.507165203 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.290199618 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7616080000 ps |
| CPU time | 31.64 seconds |
| Started | Jul 31 04:40:44 PM PDT 24 |
| Finished | Jul 31 04:41:45 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-b76d928a-f8a2-4d2c-a1c2-b9a533b6d8ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290199618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.290199618 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1417776884 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5555200000 ps |
| CPU time | 21.57 seconds |
| Started | Jul 31 04:41:02 PM PDT 24 |
| Finished | Jul 31 04:41:43 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-9adfffc0-1ad1-4b2e-981b-cb0a3a1f3331 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417776884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1417776884 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1042079799 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9486000000 ps |
| CPU time | 32.38 seconds |
| Started | Jul 31 04:40:42 PM PDT 24 |
| Finished | Jul 31 04:41:44 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-cbde29dc-ec11-4b9d-9f28-1ff8c5a4170f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042079799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1042079799 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3850984447 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6940280000 ps |
| CPU time | 22.41 seconds |
| Started | Jul 31 04:40:44 PM PDT 24 |
| Finished | Jul 31 04:41:25 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-594e9202-a854-438b-89a3-2a1f099a4ac0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3850984447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3850984447 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1583841211 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 15167060000 ps |
| CPU time | 51.48 seconds |
| Started | Jul 31 04:40:51 PM PDT 24 |
| Finished | Jul 31 04:42:28 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-b5735a81-263c-458a-a116-06ed78150edc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1583841211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1583841211 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3185261097 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5245200000 ps |
| CPU time | 18.9 seconds |
| Started | Jul 31 04:40:47 PM PDT 24 |
| Finished | Jul 31 04:41:22 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-4d0baa9c-47c7-4fc5-ab4f-8971fe7ca385 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3185261097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3185261097 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2052779819 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4529100000 ps |
| CPU time | 14.9 seconds |
| Started | Jul 31 04:40:47 PM PDT 24 |
| Finished | Jul 31 04:41:14 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-9d462727-4fdf-4ab2-883c-7c2094a243f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052779819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2052779819 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1549566656 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6524880000 ps |
| CPU time | 20.42 seconds |
| Started | Jul 31 04:40:50 PM PDT 24 |
| Finished | Jul 31 04:41:28 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-f33e76c8-8519-44c0-881f-771134a23dd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549566656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1549566656 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1089365642 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6690420000 ps |
| CPU time | 20.45 seconds |
| Started | Jul 31 04:40:46 PM PDT 24 |
| Finished | Jul 31 04:41:23 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-0c46bd4d-3e2f-41df-b8e9-d27ed8f9985b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089365642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1089365642 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3202890334 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7211840000 ps |
| CPU time | 24.67 seconds |
| Started | Jul 31 04:40:42 PM PDT 24 |
| Finished | Jul 31 04:41:28 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-3506d634-87ae-47f8-b1fd-3101ff557e03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202890334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3202890334 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.333633711 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10872940000 ps |
| CPU time | 36.45 seconds |
| Started | Jul 31 04:41:48 PM PDT 24 |
| Finished | Jul 31 04:42:57 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-d4c0a03c-81eb-4cf2-92cb-ef4356b88beb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333633711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.333633711 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1454033383 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5624640000 ps |
| CPU time | 18.39 seconds |
| Started | Jul 31 04:41:43 PM PDT 24 |
| Finished | Jul 31 04:42:17 PM PDT 24 |
| Peak memory | 144004 kb |
| Host | smart-c9be2d56-8886-4d3b-b04e-66892c03a0c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454033383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1454033383 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3953433892 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13693940000 ps |
| CPU time | 55.32 seconds |
| Started | Jul 31 04:40:41 PM PDT 24 |
| Finished | Jul 31 04:42:26 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-427f9325-8a7f-4eec-9719-e3aa52c6609d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953433892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3953433892 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.120284873 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12389460000 ps |
| CPU time | 44.3 seconds |
| Started | Jul 31 04:40:46 PM PDT 24 |
| Finished | Jul 31 04:42:10 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-881c9a98-6bed-4226-86b4-87fee28bdf26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120284873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.120284873 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3266034035 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3857640000 ps |
| CPU time | 12.98 seconds |
| Started | Jul 31 04:42:05 PM PDT 24 |
| Finished | Jul 31 04:42:29 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-a1f6a29b-0dc6-49cc-b515-96b2006f44aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266034035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3266034035 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.326873044 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4472060000 ps |
| CPU time | 14.22 seconds |
| Started | Jul 31 04:41:16 PM PDT 24 |
| Finished | Jul 31 04:41:42 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-a874204a-c4f8-4937-9c85-45919dc9fc88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326873044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.326873044 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2494439757 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4503060000 ps |
| CPU time | 15.38 seconds |
| Started | Jul 31 04:40:47 PM PDT 24 |
| Finished | Jul 31 04:41:15 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-088ade79-4040-4452-b18c-a9941283b7cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494439757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2494439757 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1972822446 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11758300000 ps |
| CPU time | 36.01 seconds |
| Started | Jul 31 04:40:38 PM PDT 24 |
| Finished | Jul 31 04:41:44 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-130f3cbe-b7e7-4250-8f01-0ed9aa163398 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972822446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1972822446 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1770026396 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4483220000 ps |
| CPU time | 13.86 seconds |
| Started | Jul 31 04:40:34 PM PDT 24 |
| Finished | Jul 31 04:41:00 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-9df3c82c-1b18-46cf-8551-8e316bb2efc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770026396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1770026396 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.606457560 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12727980000 ps |
| CPU time | 38.78 seconds |
| Started | Jul 31 04:40:43 PM PDT 24 |
| Finished | Jul 31 04:41:55 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-5630a493-9eb6-4fd9-956c-9b1b0b3bd622 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=606457560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.606457560 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2406415971 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5787700000 ps |
| CPU time | 20.91 seconds |
| Started | Jul 31 04:40:44 PM PDT 24 |
| Finished | Jul 31 04:41:23 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-cfe377eb-4684-4b0e-ad43-512bbb1837e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406415971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2406415971 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1032550233 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13189260000 ps |
| CPU time | 42.42 seconds |
| Started | Jul 31 04:40:44 PM PDT 24 |
| Finished | Jul 31 04:42:02 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-509e84b5-65c7-40d4-8abe-74e3b6897a98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1032550233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1032550233 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.459902245 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4132920000 ps |
| CPU time | 16.3 seconds |
| Started | Jul 31 04:40:40 PM PDT 24 |
| Finished | Jul 31 04:41:17 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-33d1479b-67fb-422d-bcb1-c5e1cacabef4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459902245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.459902245 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1304922052 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5844740000 ps |
| CPU time | 16.52 seconds |
| Started | Jul 31 04:40:52 PM PDT 24 |
| Finished | Jul 31 04:41:23 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-73953806-4ee4-42ce-9142-0585cb9e13a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304922052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1304922052 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3681538490 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7530520000 ps |
| CPU time | 24.55 seconds |
| Started | Jul 31 04:40:55 PM PDT 24 |
| Finished | Jul 31 04:41:40 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-17ece1df-12eb-49f3-afb8-b3a87115eaf0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681538490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3681538490 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1296468402 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9365720000 ps |
| CPU time | 32.49 seconds |
| Started | Jul 31 04:40:53 PM PDT 24 |
| Finished | Jul 31 04:41:54 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-19bb07db-8757-4e85-94b0-627d1b996006 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296468402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1296468402 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1233243687 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12664740000 ps |
| CPU time | 42.05 seconds |
| Started | Jul 31 04:40:59 PM PDT 24 |
| Finished | Jul 31 04:42:18 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-b7f7db44-1d48-42ff-b066-635a1586c6c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233243687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1233243687 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1753147923 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13530260000 ps |
| CPU time | 46.63 seconds |
| Started | Jul 31 04:40:48 PM PDT 24 |
| Finished | Jul 31 04:42:14 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-30f854ff-16a4-4ced-afb3-a884f70a8ee4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753147923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1753147923 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3970140677 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14023780000 ps |
| CPU time | 44.19 seconds |
| Started | Jul 31 04:40:51 PM PDT 24 |
| Finished | Jul 31 04:42:14 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-4faf731a-6c1b-4f0b-b0d0-2425b120fc3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970140677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3970140677 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3032053060 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7436900000 ps |
| CPU time | 26.23 seconds |
| Started | Jul 31 04:40:50 PM PDT 24 |
| Finished | Jul 31 04:41:40 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-e8a71cc8-7829-449a-b03a-05c715ef246d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032053060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3032053060 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2453975639 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8912500000 ps |
| CPU time | 27.59 seconds |
| Started | Jul 31 04:40:46 PM PDT 24 |
| Finished | Jul 31 04:41:37 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-9a58cb84-3004-44ca-a977-86946109b1d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453975639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2453975639 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2626123851 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11871140000 ps |
| CPU time | 40.24 seconds |
| Started | Jul 31 04:40:45 PM PDT 24 |
| Finished | Jul 31 04:42:01 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-1dfe8d92-790f-407b-815c-45e3f0b37e1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626123851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2626123851 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1844627946 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8417740000 ps |
| CPU time | 27.54 seconds |
| Started | Jul 31 04:40:48 PM PDT 24 |
| Finished | Jul 31 04:41:40 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-f71e9f3a-3de9-4bc9-969e-ac82ecff8eeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844627946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1844627946 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3102154030 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 15118700000 ps |
| CPU time | 47.32 seconds |
| Started | Jul 31 04:40:46 PM PDT 24 |
| Finished | Jul 31 04:42:13 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-5e22c3c1-cf76-48cd-a425-4a2b4377c936 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102154030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3102154030 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2248874065 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6408940000 ps |
| CPU time | 22.63 seconds |
| Started | Jul 31 04:42:15 PM PDT 24 |
| Finished | Jul 31 04:42:57 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-4aba4a6d-9989-4ed2-96fb-f9157b855b36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248874065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2248874065 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1936602701 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6102040000 ps |
| CPU time | 22.52 seconds |
| Started | Jul 31 04:40:47 PM PDT 24 |
| Finished | Jul 31 04:41:30 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-4f1cfa00-2d22-47b9-9bf8-dd8340355c29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936602701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1936602701 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |