| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.3090766205 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.2831247013 |
| /workspace/coverage/default/10.prim_present_test.4217640458 |
| /workspace/coverage/default/11.prim_present_test.811806021 |
| /workspace/coverage/default/12.prim_present_test.1684527174 |
| /workspace/coverage/default/13.prim_present_test.4083811377 |
| /workspace/coverage/default/14.prim_present_test.4045131802 |
| /workspace/coverage/default/15.prim_present_test.3405446112 |
| /workspace/coverage/default/16.prim_present_test.3997401708 |
| /workspace/coverage/default/17.prim_present_test.30185874 |
| /workspace/coverage/default/18.prim_present_test.884382697 |
| /workspace/coverage/default/19.prim_present_test.3733384936 |
| /workspace/coverage/default/2.prim_present_test.3640358067 |
| /workspace/coverage/default/20.prim_present_test.1810678120 |
| /workspace/coverage/default/21.prim_present_test.3680633749 |
| /workspace/coverage/default/22.prim_present_test.1145085787 |
| /workspace/coverage/default/23.prim_present_test.2527641842 |
| /workspace/coverage/default/24.prim_present_test.2221538623 |
| /workspace/coverage/default/25.prim_present_test.4254923170 |
| /workspace/coverage/default/26.prim_present_test.982536557 |
| /workspace/coverage/default/27.prim_present_test.2739197389 |
| /workspace/coverage/default/28.prim_present_test.2665359627 |
| /workspace/coverage/default/29.prim_present_test.198707329 |
| /workspace/coverage/default/3.prim_present_test.3715138876 |
| /workspace/coverage/default/30.prim_present_test.1363010788 |
| /workspace/coverage/default/31.prim_present_test.237612685 |
| /workspace/coverage/default/32.prim_present_test.2746026192 |
| /workspace/coverage/default/33.prim_present_test.2403475698 |
| /workspace/coverage/default/34.prim_present_test.2992500672 |
| /workspace/coverage/default/35.prim_present_test.956291723 |
| /workspace/coverage/default/36.prim_present_test.2366948409 |
| /workspace/coverage/default/37.prim_present_test.3221243643 |
| /workspace/coverage/default/38.prim_present_test.3321905031 |
| /workspace/coverage/default/39.prim_present_test.438694751 |
| /workspace/coverage/default/4.prim_present_test.3730237514 |
| /workspace/coverage/default/40.prim_present_test.760754415 |
| /workspace/coverage/default/41.prim_present_test.3261910873 |
| /workspace/coverage/default/42.prim_present_test.2320518869 |
| /workspace/coverage/default/43.prim_present_test.219858223 |
| /workspace/coverage/default/44.prim_present_test.1992431664 |
| /workspace/coverage/default/45.prim_present_test.2816601393 |
| /workspace/coverage/default/46.prim_present_test.2324096266 |
| /workspace/coverage/default/47.prim_present_test.1121774529 |
| /workspace/coverage/default/48.prim_present_test.3585227353 |
| /workspace/coverage/default/49.prim_present_test.1012515183 |
| /workspace/coverage/default/5.prim_present_test.101209156 |
| /workspace/coverage/default/6.prim_present_test.3128082004 |
| /workspace/coverage/default/7.prim_present_test.2288517882 |
| /workspace/coverage/default/8.prim_present_test.3308444900 |
| /workspace/coverage/default/9.prim_present_test.367961431 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_present_test.884382697 | Aug 01 04:17:48 PM PDT 24 | Aug 01 04:18:27 PM PDT 24 | 5478940000 ps | ||
| T2 | /workspace/coverage/default/3.prim_present_test.3715138876 | Aug 01 04:17:47 PM PDT 24 | Aug 01 04:18:10 PM PDT 24 | 3499280000 ps | ||
| T3 | /workspace/coverage/default/26.prim_present_test.982536557 | Aug 01 04:18:51 PM PDT 24 | Aug 01 04:19:40 PM PDT 24 | 7018400000 ps | ||
| T4 | /workspace/coverage/default/7.prim_present_test.2288517882 | Aug 01 04:17:52 PM PDT 24 | Aug 01 04:19:46 PM PDT 24 | 15142260000 ps | ||
| T5 | /workspace/coverage/default/40.prim_present_test.760754415 | Aug 01 04:23:14 PM PDT 24 | Aug 01 04:24:48 PM PDT 24 | 12713100000 ps | ||
| T6 | /workspace/coverage/default/22.prim_present_test.1145085787 | Aug 01 04:18:20 PM PDT 24 | Aug 01 04:19:59 PM PDT 24 | 15497520000 ps | ||
| T7 | /workspace/coverage/default/5.prim_present_test.101209156 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:19:20 PM PDT 24 | 11797980000 ps | ||
| T8 | /workspace/coverage/default/35.prim_present_test.956291723 | Aug 01 04:22:28 PM PDT 24 | Aug 01 04:23:09 PM PDT 24 | 5997260000 ps | ||
| T9 | /workspace/coverage/default/39.prim_present_test.438694751 | Aug 01 04:23:11 PM PDT 24 | Aug 01 04:24:12 PM PDT 24 | 9657120000 ps | ||
| T10 | /workspace/coverage/default/0.prim_present_test.3090766205 | Aug 01 04:17:38 PM PDT 24 | Aug 01 04:18:39 PM PDT 24 | 10032840000 ps | ||
| T11 | /workspace/coverage/default/19.prim_present_test.3733384936 | Aug 01 04:17:47 PM PDT 24 | Aug 01 04:18:51 PM PDT 24 | 9319220000 ps | ||
| T12 | /workspace/coverage/default/41.prim_present_test.3261910873 | Aug 01 04:19:42 PM PDT 24 | Aug 01 04:21:01 PM PDT 24 | 10889060000 ps | ||
| T13 | /workspace/coverage/default/30.prim_present_test.1363010788 | Aug 01 04:20:12 PM PDT 24 | Aug 01 04:21:56 PM PDT 24 | 14935800000 ps | ||
| T14 | /workspace/coverage/default/46.prim_present_test.2324096266 | Aug 01 04:23:07 PM PDT 24 | Aug 01 04:24:37 PM PDT 24 | 12285920000 ps | ||
| T15 | /workspace/coverage/default/45.prim_present_test.2816601393 | Aug 01 04:23:07 PM PDT 24 | Aug 01 04:24:39 PM PDT 24 | 12605840000 ps | ||
| T16 | /workspace/coverage/default/1.prim_present_test.2831247013 | Aug 01 04:17:36 PM PDT 24 | Aug 01 04:18:13 PM PDT 24 | 5603560000 ps | ||
| T17 | /workspace/coverage/default/42.prim_present_test.2320518869 | Aug 01 04:23:07 PM PDT 24 | Aug 01 04:24:44 PM PDT 24 | 13301480000 ps | ||
| T18 | /workspace/coverage/default/23.prim_present_test.2527641842 | Aug 01 04:17:47 PM PDT 24 | Aug 01 04:18:28 PM PDT 24 | 5386560000 ps | ||
| T19 | /workspace/coverage/default/48.prim_present_test.3585227353 | Aug 01 04:23:03 PM PDT 24 | Aug 01 04:24:05 PM PDT 24 | 8073640000 ps | ||
| T20 | /workspace/coverage/default/12.prim_present_test.1684527174 | Aug 01 04:17:49 PM PDT 24 | Aug 01 04:19:10 PM PDT 24 | 12109220000 ps | ||
| T21 | /workspace/coverage/default/28.prim_present_test.2665359627 | Aug 01 04:18:57 PM PDT 24 | Aug 01 04:20:09 PM PDT 24 | 9551720000 ps | ||
| T22 | /workspace/coverage/default/24.prim_present_test.2221538623 | Aug 01 04:17:47 PM PDT 24 | Aug 01 04:18:39 PM PDT 24 | 7281280000 ps | ||
| T23 | /workspace/coverage/default/13.prim_present_test.4083811377 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:18:11 PM PDT 24 | 3620180000 ps | ||
| T24 | /workspace/coverage/default/36.prim_present_test.2366948409 | Aug 01 04:23:11 PM PDT 24 | Aug 01 04:24:26 PM PDT 24 | 11618800000 ps | ||
| T25 | /workspace/coverage/default/8.prim_present_test.3308444900 | Aug 01 04:17:47 PM PDT 24 | Aug 01 04:18:17 PM PDT 24 | 4316440000 ps | ||
| T26 | /workspace/coverage/default/20.prim_present_test.1810678120 | Aug 01 04:17:47 PM PDT 24 | Aug 01 04:18:29 PM PDT 24 | 5891240000 ps | ||
| T27 | /workspace/coverage/default/38.prim_present_test.3321905031 | Aug 01 04:22:38 PM PDT 24 | Aug 01 04:24:02 PM PDT 24 | 14663620000 ps | ||
| T28 | /workspace/coverage/default/33.prim_present_test.2403475698 | Aug 01 04:23:21 PM PDT 24 | Aug 01 04:23:45 PM PDT 24 | 3739220000 ps | ||
| T29 | /workspace/coverage/default/32.prim_present_test.2746026192 | Aug 01 04:23:22 PM PDT 24 | Aug 01 04:23:45 PM PDT 24 | 3719380000 ps | ||
| T30 | /workspace/coverage/default/25.prim_present_test.4254923170 | Aug 01 04:18:57 PM PDT 24 | Aug 01 04:20:44 PM PDT 24 | 14193660000 ps | ||
| T31 | /workspace/coverage/default/17.prim_present_test.30185874 | Aug 01 04:17:47 PM PDT 24 | Aug 01 04:18:57 PM PDT 24 | 10410420000 ps | ||
| T32 | /workspace/coverage/default/47.prim_present_test.1121774529 | Aug 01 04:23:10 PM PDT 24 | Aug 01 04:23:51 PM PDT 24 | 7495800000 ps | ||
| T33 | /workspace/coverage/default/27.prim_present_test.2739197389 | Aug 01 04:18:56 PM PDT 24 | Aug 01 04:19:24 PM PDT 24 | 3615220000 ps | ||
| T34 | /workspace/coverage/default/4.prim_present_test.3730237514 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:19:14 PM PDT 24 | 12944980000 ps | ||
| T35 | /workspace/coverage/default/11.prim_present_test.811806021 | Aug 01 04:17:52 PM PDT 24 | Aug 01 04:18:21 PM PDT 24 | 4274280000 ps | ||
| T36 | /workspace/coverage/default/29.prim_present_test.198707329 | Aug 01 04:22:47 PM PDT 24 | Aug 01 04:23:56 PM PDT 24 | 11080020000 ps | ||
| T37 | /workspace/coverage/default/31.prim_present_test.237612685 | Aug 01 04:22:28 PM PDT 24 | Aug 01 04:23:13 PM PDT 24 | 6372360000 ps | ||
| T38 | /workspace/coverage/default/15.prim_present_test.3405446112 | Aug 01 04:17:44 PM PDT 24 | Aug 01 04:18:59 PM PDT 24 | 12062100000 ps | ||
| T39 | /workspace/coverage/default/44.prim_present_test.1992431664 | Aug 01 04:18:34 PM PDT 24 | Aug 01 04:19:45 PM PDT 24 | 8913740000 ps | ||
| T40 | /workspace/coverage/default/6.prim_present_test.3128082004 | Aug 01 04:17:52 PM PDT 24 | Aug 01 04:19:14 PM PDT 24 | 10948580000 ps | ||
| T41 | /workspace/coverage/default/37.prim_present_test.3221243643 | Aug 01 04:22:56 PM PDT 24 | Aug 01 04:24:33 PM PDT 24 | 14883100000 ps | ||
| T42 | /workspace/coverage/default/9.prim_present_test.367961431 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:18:14 PM PDT 24 | 4080220000 ps | ||
| T43 | /workspace/coverage/default/16.prim_present_test.3997401708 | Aug 01 04:17:47 PM PDT 24 | Aug 01 04:18:47 PM PDT 24 | 7890740000 ps | ||
| T44 | /workspace/coverage/default/2.prim_present_test.3640358067 | Aug 01 04:17:37 PM PDT 24 | Aug 01 04:18:12 PM PDT 24 | 5258220000 ps | ||
| T45 | /workspace/coverage/default/43.prim_present_test.219858223 | Aug 01 04:23:57 PM PDT 24 | Aug 01 04:24:20 PM PDT 24 | 4288540000 ps | ||
| T46 | /workspace/coverage/default/49.prim_present_test.1012515183 | Aug 01 04:22:28 PM PDT 24 | Aug 01 04:23:51 PM PDT 24 | 13369060000 ps | ||
| T47 | /workspace/coverage/default/34.prim_present_test.2992500672 | Aug 01 04:22:41 PM PDT 24 | Aug 01 04:23:24 PM PDT 24 | 6570760000 ps | ||
| T48 | /workspace/coverage/default/14.prim_present_test.4045131802 | Aug 01 04:17:37 PM PDT 24 | Aug 01 04:18:07 PM PDT 24 | 4538400000 ps | ||
| T49 | /workspace/coverage/default/21.prim_present_test.3680633749 | Aug 01 04:18:04 PM PDT 24 | Aug 01 04:19:00 PM PDT 24 | 7094660000 ps | ||
| T50 | /workspace/coverage/default/10.prim_present_test.4217640458 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:18:16 PM PDT 24 | 3968000000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.3090766205 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10032840000 ps |
| CPU time | 33.01 seconds |
| Started | Aug 01 04:17:38 PM PDT 24 |
| Finished | Aug 01 04:18:39 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-4afa6cdd-993f-4754-ba2b-eb057baf164f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090766205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3090766205 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2831247013 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5603560000 ps |
| CPU time | 19.99 seconds |
| Started | Aug 01 04:17:36 PM PDT 24 |
| Finished | Aug 01 04:18:13 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-01ffbd0c-c346-4a0a-a48b-19fc759963e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831247013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2831247013 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.4217640458 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3968000000 ps |
| CPU time | 16.11 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:18:16 PM PDT 24 |
| Peak memory | 144460 kb |
| Host | smart-cb9ac9b6-dcd2-4bc9-85bf-883f80547e0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217640458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.4217640458 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.811806021 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4274280000 ps |
| CPU time | 15.85 seconds |
| Started | Aug 01 04:17:52 PM PDT 24 |
| Finished | Aug 01 04:18:21 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-34b3ee32-43f9-4abb-aeab-eebee09c7844 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811806021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.811806021 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1684527174 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12109220000 ps |
| CPU time | 43.51 seconds |
| Started | Aug 01 04:17:49 PM PDT 24 |
| Finished | Aug 01 04:19:10 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-d2f42bbc-c245-4778-923a-551b963cee30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684527174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1684527174 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.4083811377 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3620180000 ps |
| CPU time | 13.79 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:18:11 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-368154b8-4ff9-4eb0-9cdd-9d18b2c74183 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083811377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.4083811377 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4045131802 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4538400000 ps |
| CPU time | 16.04 seconds |
| Started | Aug 01 04:17:37 PM PDT 24 |
| Finished | Aug 01 04:18:07 PM PDT 24 |
| Peak memory | 144560 kb |
| Host | smart-6288114d-b384-4f81-952e-54774a166b73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045131802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4045131802 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3405446112 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12062100000 ps |
| CPU time | 40.84 seconds |
| Started | Aug 01 04:17:44 PM PDT 24 |
| Finished | Aug 01 04:18:59 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-04bbbdb3-3899-45cc-9983-27a3ecb0742c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405446112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3405446112 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3997401708 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7890740000 ps |
| CPU time | 31.67 seconds |
| Started | Aug 01 04:17:47 PM PDT 24 |
| Finished | Aug 01 04:18:47 PM PDT 24 |
| Peak memory | 144012 kb |
| Host | smart-b8443741-95f7-4a67-90fd-79afcb2ffc86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997401708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3997401708 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.30185874 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10410420000 ps |
| CPU time | 37.03 seconds |
| Started | Aug 01 04:17:47 PM PDT 24 |
| Finished | Aug 01 04:18:57 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-0df508ba-59e1-46bb-ba2b-6cd51f86e64e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30185874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.30185874 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.884382697 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5478940000 ps |
| CPU time | 20.61 seconds |
| Started | Aug 01 04:17:48 PM PDT 24 |
| Finished | Aug 01 04:18:27 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-4fcbc92b-c07d-4c03-aa00-30b994728568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884382697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.884382697 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3733384936 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9319220000 ps |
| CPU time | 33.87 seconds |
| Started | Aug 01 04:17:47 PM PDT 24 |
| Finished | Aug 01 04:18:51 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-5043f903-77c0-4f8c-9631-c4f055ad25a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733384936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3733384936 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3640358067 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5258220000 ps |
| CPU time | 18.69 seconds |
| Started | Aug 01 04:17:37 PM PDT 24 |
| Finished | Aug 01 04:18:12 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-741c083a-7c3c-49a5-b001-43d62a8285e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3640358067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3640358067 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1810678120 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5891240000 ps |
| CPU time | 21.95 seconds |
| Started | Aug 01 04:17:47 PM PDT 24 |
| Finished | Aug 01 04:18:29 PM PDT 24 |
| Peak memory | 144620 kb |
| Host | smart-a005b3a4-684c-4017-9340-4020a9792151 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1810678120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1810678120 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3680633749 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7094660000 ps |
| CPU time | 29.98 seconds |
| Started | Aug 01 04:18:04 PM PDT 24 |
| Finished | Aug 01 04:19:00 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-b72bd5f0-3774-4f94-9288-d5a9bce753e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680633749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3680633749 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1145085787 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 15497520000 ps |
| CPU time | 53.51 seconds |
| Started | Aug 01 04:18:20 PM PDT 24 |
| Finished | Aug 01 04:19:59 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-1819b7d7-914f-48c6-a9b2-823106af5b22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145085787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1145085787 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2527641842 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5386560000 ps |
| CPU time | 21.48 seconds |
| Started | Aug 01 04:17:47 PM PDT 24 |
| Finished | Aug 01 04:18:28 PM PDT 24 |
| Peak memory | 143248 kb |
| Host | smart-37bda87b-6b9d-4ba3-a1ca-2091033c9172 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527641842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2527641842 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2221538623 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7281280000 ps |
| CPU time | 27.63 seconds |
| Started | Aug 01 04:17:47 PM PDT 24 |
| Finished | Aug 01 04:18:39 PM PDT 24 |
| Peak memory | 143236 kb |
| Host | smart-f22716f4-519c-4b08-ae02-aba192a2e890 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221538623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2221538623 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4254923170 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14193660000 ps |
| CPU time | 56.26 seconds |
| Started | Aug 01 04:18:57 PM PDT 24 |
| Finished | Aug 01 04:20:44 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-62f4264c-dc7e-4c50-a5f8-f637d519b638 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254923170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4254923170 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.982536557 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7018400000 ps |
| CPU time | 26.05 seconds |
| Started | Aug 01 04:18:51 PM PDT 24 |
| Finished | Aug 01 04:19:40 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-194ac9d5-c2c5-4cf7-902c-81b9f2419a6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982536557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.982536557 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2739197389 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3615220000 ps |
| CPU time | 14.92 seconds |
| Started | Aug 01 04:18:56 PM PDT 24 |
| Finished | Aug 01 04:19:24 PM PDT 24 |
| Peak memory | 144676 kb |
| Host | smart-36c0c9b4-1d19-41b9-95f5-815f222d8fb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739197389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2739197389 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2665359627 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9551720000 ps |
| CPU time | 38.1 seconds |
| Started | Aug 01 04:18:57 PM PDT 24 |
| Finished | Aug 01 04:20:09 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-5e1efa5b-43b9-4043-999b-68abae327346 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665359627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2665359627 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.198707329 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11080020000 ps |
| CPU time | 37.19 seconds |
| Started | Aug 01 04:22:47 PM PDT 24 |
| Finished | Aug 01 04:23:56 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-d33d8601-f60e-4b5a-883e-2709856962ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198707329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.198707329 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3715138876 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3499280000 ps |
| CPU time | 12.68 seconds |
| Started | Aug 01 04:17:47 PM PDT 24 |
| Finished | Aug 01 04:18:10 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-8a64788a-a3e1-49d5-a5b0-e23731166523 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715138876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3715138876 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1363010788 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14935800000 ps |
| CPU time | 55.36 seconds |
| Started | Aug 01 04:20:12 PM PDT 24 |
| Finished | Aug 01 04:21:56 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-9cd32125-ab1a-4202-8a6c-83f320f807a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1363010788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1363010788 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.237612685 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6372360000 ps |
| CPU time | 23.37 seconds |
| Started | Aug 01 04:22:28 PM PDT 24 |
| Finished | Aug 01 04:23:13 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-9163fe7f-c6c9-4a1e-a75d-a239b63153af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=237612685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.237612685 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2746026192 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3719380000 ps |
| CPU time | 12.85 seconds |
| Started | Aug 01 04:23:22 PM PDT 24 |
| Finished | Aug 01 04:23:45 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-da45d625-811b-4152-9b58-1e9302949527 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2746026192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2746026192 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2403475698 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3739220000 ps |
| CPU time | 13.2 seconds |
| Started | Aug 01 04:23:21 PM PDT 24 |
| Finished | Aug 01 04:23:45 PM PDT 24 |
| Peak memory | 143824 kb |
| Host | smart-ce927264-b033-480a-9f0e-958d73266d3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403475698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2403475698 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2992500672 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6570760000 ps |
| CPU time | 22.93 seconds |
| Started | Aug 01 04:22:41 PM PDT 24 |
| Finished | Aug 01 04:23:24 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-aab8b05e-84df-4eed-99ea-9872b189b247 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992500672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2992500672 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.956291723 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5997260000 ps |
| CPU time | 21.41 seconds |
| Started | Aug 01 04:22:28 PM PDT 24 |
| Finished | Aug 01 04:23:09 PM PDT 24 |
| Peak memory | 143736 kb |
| Host | smart-c622cf33-7869-4bb4-bb28-c5e0d8401a3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956291723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.956291723 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2366948409 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11618800000 ps |
| CPU time | 39.52 seconds |
| Started | Aug 01 04:23:11 PM PDT 24 |
| Finished | Aug 01 04:24:26 PM PDT 24 |
| Peak memory | 144784 kb |
| Host | smart-a7a1cf42-ebb2-48bb-8a9d-763b7ac0dff6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366948409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2366948409 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3221243643 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14883100000 ps |
| CPU time | 51.75 seconds |
| Started | Aug 01 04:22:56 PM PDT 24 |
| Finished | Aug 01 04:24:33 PM PDT 24 |
| Peak memory | 143928 kb |
| Host | smart-e5609d1b-d772-4997-9e83-9bda648bd2b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221243643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3221243643 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3321905031 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14663620000 ps |
| CPU time | 45.74 seconds |
| Started | Aug 01 04:22:38 PM PDT 24 |
| Finished | Aug 01 04:24:02 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-9191cbb1-007b-4d4f-9663-1fcfb385b171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321905031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3321905031 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.438694751 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9657120000 ps |
| CPU time | 32.29 seconds |
| Started | Aug 01 04:23:11 PM PDT 24 |
| Finished | Aug 01 04:24:12 PM PDT 24 |
| Peak memory | 144764 kb |
| Host | smart-4c2503fd-ffda-46f5-b6c2-92d1657ddb48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438694751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.438694751 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3730237514 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12944980000 ps |
| CPU time | 47.28 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:19:14 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-c9d5ffcf-4a09-4172-b352-65dbdc88de08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730237514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3730237514 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.760754415 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12713100000 ps |
| CPU time | 48.43 seconds |
| Started | Aug 01 04:23:14 PM PDT 24 |
| Finished | Aug 01 04:24:48 PM PDT 24 |
| Peak memory | 144840 kb |
| Host | smart-4003e191-3269-4e53-8c0a-13d0ff91fe6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760754415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.760754415 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3261910873 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10889060000 ps |
| CPU time | 41.84 seconds |
| Started | Aug 01 04:19:42 PM PDT 24 |
| Finished | Aug 01 04:21:01 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-c3ef6413-9591-430d-861f-5f7304735bf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3261910873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3261910873 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2320518869 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 13301480000 ps |
| CPU time | 50.08 seconds |
| Started | Aug 01 04:23:07 PM PDT 24 |
| Finished | Aug 01 04:24:44 PM PDT 24 |
| Peak memory | 143584 kb |
| Host | smart-f8dcd038-0c2d-40c3-a60d-1e1216541593 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320518869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2320518869 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.219858223 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4288540000 ps |
| CPU time | 12.79 seconds |
| Started | Aug 01 04:23:57 PM PDT 24 |
| Finished | Aug 01 04:24:20 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-919c31c9-2817-4eb3-bfc7-05d5e6e0afc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219858223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.219858223 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1992431664 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8913740000 ps |
| CPU time | 35.36 seconds |
| Started | Aug 01 04:18:34 PM PDT 24 |
| Finished | Aug 01 04:19:45 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-2ccb84ed-8002-469a-ba33-930c5d4ea4a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1992431664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1992431664 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2816601393 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12605840000 ps |
| CPU time | 47.28 seconds |
| Started | Aug 01 04:23:07 PM PDT 24 |
| Finished | Aug 01 04:24:39 PM PDT 24 |
| Peak memory | 143544 kb |
| Host | smart-ea20f03a-485c-4a60-90e1-0bde96b8f2d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816601393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2816601393 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2324096266 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12285920000 ps |
| CPU time | 46.5 seconds |
| Started | Aug 01 04:23:07 PM PDT 24 |
| Finished | Aug 01 04:24:37 PM PDT 24 |
| Peak memory | 143324 kb |
| Host | smart-a7bda035-0f51-4be8-97f5-ab4b3092410d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324096266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2324096266 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1121774529 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7495800000 ps |
| CPU time | 22.11 seconds |
| Started | Aug 01 04:23:10 PM PDT 24 |
| Finished | Aug 01 04:23:51 PM PDT 24 |
| Peak memory | 144020 kb |
| Host | smart-33d8f873-d97f-42db-aad9-b6db53e40a08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121774529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1121774529 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3585227353 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8073640000 ps |
| CPU time | 31.56 seconds |
| Started | Aug 01 04:23:03 PM PDT 24 |
| Finished | Aug 01 04:24:05 PM PDT 24 |
| Peak memory | 144032 kb |
| Host | smart-2e01f563-0f58-4711-9403-7c180f4f96da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585227353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3585227353 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1012515183 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13369060000 ps |
| CPU time | 44.2 seconds |
| Started | Aug 01 04:22:28 PM PDT 24 |
| Finished | Aug 01 04:23:51 PM PDT 24 |
| Peak memory | 144084 kb |
| Host | smart-65120ad5-4160-4a23-a4a6-593bc89364a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012515183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1012515183 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.101209156 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11797980000 ps |
| CPU time | 48.54 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:19:20 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-57125c54-2f75-4628-b96e-21d373ea1826 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101209156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.101209156 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3128082004 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10948580000 ps |
| CPU time | 43.05 seconds |
| Started | Aug 01 04:17:52 PM PDT 24 |
| Finished | Aug 01 04:19:14 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-32195078-c364-4dfe-8f3c-092145c1e3d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128082004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3128082004 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2288517882 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 15142260000 ps |
| CPU time | 59.4 seconds |
| Started | Aug 01 04:17:52 PM PDT 24 |
| Finished | Aug 01 04:19:46 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-c8aaff07-c527-401b-ace4-14561a92fa62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288517882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2288517882 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3308444900 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4316440000 ps |
| CPU time | 16.05 seconds |
| Started | Aug 01 04:17:47 PM PDT 24 |
| Finished | Aug 01 04:18:17 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-f669d35f-ca8f-4ee3-8b31-53b49ac3baa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308444900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3308444900 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.367961431 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4080220000 ps |
| CPU time | 15.19 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:18:14 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-69d0db07-c34e-4c81-b2a2-4866598054ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=367961431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.367961431 |
| Directory | /workspace/9.prim_present_test/latest |
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