| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/19.prim_present_test.2207835041 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2697671902 |
| /workspace/coverage/default/1.prim_present_test.375589866 |
| /workspace/coverage/default/10.prim_present_test.1541074720 |
| /workspace/coverage/default/11.prim_present_test.2582495125 |
| /workspace/coverage/default/12.prim_present_test.1230144188 |
| /workspace/coverage/default/13.prim_present_test.740671422 |
| /workspace/coverage/default/14.prim_present_test.149881820 |
| /workspace/coverage/default/15.prim_present_test.2422141797 |
| /workspace/coverage/default/16.prim_present_test.100605662 |
| /workspace/coverage/default/17.prim_present_test.3150975835 |
| /workspace/coverage/default/18.prim_present_test.1651360714 |
| /workspace/coverage/default/2.prim_present_test.1987391646 |
| /workspace/coverage/default/20.prim_present_test.193168142 |
| /workspace/coverage/default/21.prim_present_test.1293727833 |
| /workspace/coverage/default/22.prim_present_test.435375872 |
| /workspace/coverage/default/23.prim_present_test.3498235139 |
| /workspace/coverage/default/24.prim_present_test.3719685049 |
| /workspace/coverage/default/25.prim_present_test.102226502 |
| /workspace/coverage/default/26.prim_present_test.1879147684 |
| /workspace/coverage/default/27.prim_present_test.3940621869 |
| /workspace/coverage/default/28.prim_present_test.3934597622 |
| /workspace/coverage/default/29.prim_present_test.1069595997 |
| /workspace/coverage/default/3.prim_present_test.4258457175 |
| /workspace/coverage/default/30.prim_present_test.3464212104 |
| /workspace/coverage/default/31.prim_present_test.4055551661 |
| /workspace/coverage/default/32.prim_present_test.1982887124 |
| /workspace/coverage/default/33.prim_present_test.1228960500 |
| /workspace/coverage/default/34.prim_present_test.2822496502 |
| /workspace/coverage/default/35.prim_present_test.51603589 |
| /workspace/coverage/default/36.prim_present_test.811578183 |
| /workspace/coverage/default/37.prim_present_test.902673228 |
| /workspace/coverage/default/38.prim_present_test.1907302752 |
| /workspace/coverage/default/39.prim_present_test.1566685522 |
| /workspace/coverage/default/4.prim_present_test.997003568 |
| /workspace/coverage/default/40.prim_present_test.2942447805 |
| /workspace/coverage/default/41.prim_present_test.1862086492 |
| /workspace/coverage/default/42.prim_present_test.1221993260 |
| /workspace/coverage/default/43.prim_present_test.1934932339 |
| /workspace/coverage/default/44.prim_present_test.1441367327 |
| /workspace/coverage/default/45.prim_present_test.3662425011 |
| /workspace/coverage/default/46.prim_present_test.597877515 |
| /workspace/coverage/default/47.prim_present_test.3341211661 |
| /workspace/coverage/default/48.prim_present_test.3518780994 |
| /workspace/coverage/default/49.prim_present_test.2573731725 |
| /workspace/coverage/default/5.prim_present_test.1059257363 |
| /workspace/coverage/default/6.prim_present_test.3878567941 |
| /workspace/coverage/default/7.prim_present_test.2132084514 |
| /workspace/coverage/default/8.prim_present_test.3858876285 |
| /workspace/coverage/default/9.prim_present_test.3801069453 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/42.prim_present_test.1221993260 | Aug 02 04:23:24 PM PDT 24 | Aug 02 04:24:25 PM PDT 24 | 9198320000 ps | ||
| T2 | /workspace/coverage/default/19.prim_present_test.2207835041 | Aug 02 04:23:15 PM PDT 24 | Aug 02 04:24:51 PM PDT 24 | 14330680000 ps | ||
| T3 | /workspace/coverage/default/36.prim_present_test.811578183 | Aug 02 04:23:26 PM PDT 24 | Aug 02 04:23:49 PM PDT 24 | 3370320000 ps | ||
| T4 | /workspace/coverage/default/22.prim_present_test.435375872 | Aug 02 04:23:13 PM PDT 24 | Aug 02 04:24:33 PM PDT 24 | 11588420000 ps | ||
| T5 | /workspace/coverage/default/2.prim_present_test.1987391646 | Aug 02 04:23:15 PM PDT 24 | Aug 02 04:24:10 PM PDT 24 | 9228700000 ps | ||
| T6 | /workspace/coverage/default/25.prim_present_test.102226502 | Aug 02 04:23:13 PM PDT 24 | Aug 02 04:24:03 PM PDT 24 | 7262060000 ps | ||
| T7 | /workspace/coverage/default/31.prim_present_test.4055551661 | Aug 02 04:23:15 PM PDT 24 | Aug 02 04:24:28 PM PDT 24 | 11132720000 ps | ||
| T8 | /workspace/coverage/default/48.prim_present_test.3518780994 | Aug 02 04:24:25 PM PDT 24 | Aug 02 04:25:00 PM PDT 24 | 6137380000 ps | ||
| T9 | /workspace/coverage/default/9.prim_present_test.3801069453 | Aug 02 04:23:13 PM PDT 24 | Aug 02 04:24:48 PM PDT 24 | 11545020000 ps | ||
| T10 | /workspace/coverage/default/49.prim_present_test.2573731725 | Aug 02 04:23:24 PM PDT 24 | Aug 02 04:24:28 PM PDT 24 | 12408680000 ps | ||
| T11 | /workspace/coverage/default/30.prim_present_test.3464212104 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:23:47 PM PDT 24 | 4541500000 ps | ||
| T12 | /workspace/coverage/default/4.prim_present_test.997003568 | Aug 02 04:23:12 PM PDT 24 | Aug 02 04:24:05 PM PDT 24 | 7687380000 ps | ||
| T13 | /workspace/coverage/default/29.prim_present_test.1069595997 | Aug 02 04:23:15 PM PDT 24 | Aug 02 04:24:47 PM PDT 24 | 15467760000 ps | ||
| T14 | /workspace/coverage/default/35.prim_present_test.51603589 | Aug 02 04:24:27 PM PDT 24 | Aug 02 04:25:07 PM PDT 24 | 6474040000 ps | ||
| T15 | /workspace/coverage/default/6.prim_present_test.3878567941 | Aug 02 04:23:12 PM PDT 24 | Aug 02 04:24:35 PM PDT 24 | 11935620000 ps | ||
| T16 | /workspace/coverage/default/46.prim_present_test.597877515 | Aug 02 04:23:24 PM PDT 24 | Aug 02 04:23:49 PM PDT 24 | 3531520000 ps | ||
| T17 | /workspace/coverage/default/0.prim_present_test.2697671902 | Aug 02 04:23:11 PM PDT 24 | Aug 02 04:24:23 PM PDT 24 | 11993900000 ps | ||
| T18 | /workspace/coverage/default/18.prim_present_test.1651360714 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:42 PM PDT 24 | 10791100000 ps | ||
| T19 | /workspace/coverage/default/8.prim_present_test.3858876285 | Aug 02 04:23:12 PM PDT 24 | Aug 02 04:24:35 PM PDT 24 | 12581040000 ps | ||
| T20 | /workspace/coverage/default/28.prim_present_test.3934597622 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:32 PM PDT 24 | 11343520000 ps | ||
| T21 | /workspace/coverage/default/27.prim_present_test.3940621869 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:25 PM PDT 24 | 10096080000 ps | ||
| T22 | /workspace/coverage/default/37.prim_present_test.902673228 | Aug 02 04:23:24 PM PDT 24 | Aug 02 04:24:31 PM PDT 24 | 8575220000 ps | ||
| T23 | /workspace/coverage/default/24.prim_present_test.3719685049 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:33 PM PDT 24 | 12696980000 ps | ||
| T24 | /workspace/coverage/default/41.prim_present_test.1862086492 | Aug 02 04:23:23 PM PDT 24 | Aug 02 04:24:03 PM PDT 24 | 6420100000 ps | ||
| T25 | /workspace/coverage/default/7.prim_present_test.2132084514 | Aug 02 04:23:12 PM PDT 24 | Aug 02 04:23:52 PM PDT 24 | 5695940000 ps | ||
| T26 | /workspace/coverage/default/47.prim_present_test.3341211661 | Aug 02 04:24:25 PM PDT 24 | Aug 02 04:25:10 PM PDT 24 | 7683660000 ps | ||
| T27 | /workspace/coverage/default/40.prim_present_test.2942447805 | Aug 02 04:23:25 PM PDT 24 | Aug 02 04:23:49 PM PDT 24 | 3550120000 ps | ||
| T28 | /workspace/coverage/default/33.prim_present_test.1228960500 | Aug 02 04:23:24 PM PDT 24 | Aug 02 04:24:30 PM PDT 24 | 10720420000 ps | ||
| T29 | /workspace/coverage/default/3.prim_present_test.4258457175 | Aug 02 04:23:13 PM PDT 24 | Aug 02 04:23:38 PM PDT 24 | 3325680000 ps | ||
| T30 | /workspace/coverage/default/16.prim_present_test.100605662 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:09 PM PDT 24 | 7931660000 ps | ||
| T31 | /workspace/coverage/default/10.prim_present_test.1541074720 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:23:39 PM PDT 24 | 3598480000 ps | ||
| T32 | /workspace/coverage/default/15.prim_present_test.2422141797 | Aug 02 04:23:23 PM PDT 24 | Aug 02 04:25:09 PM PDT 24 | 13198560000 ps | ||
| T33 | /workspace/coverage/default/12.prim_present_test.1230144188 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:53 PM PDT 24 | 12776340000 ps | ||
| T34 | /workspace/coverage/default/21.prim_present_test.1293727833 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:12 PM PDT 24 | 8528720000 ps | ||
| T35 | /workspace/coverage/default/1.prim_present_test.375589866 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:23:57 PM PDT 24 | 5271860000 ps | ||
| T36 | /workspace/coverage/default/5.prim_present_test.1059257363 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:51 PM PDT 24 | 12137120000 ps | ||
| T37 | /workspace/coverage/default/38.prim_present_test.1907302752 | Aug 02 04:23:24 PM PDT 24 | Aug 02 04:23:52 PM PDT 24 | 4137880000 ps | ||
| T38 | /workspace/coverage/default/13.prim_present_test.740671422 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:25:05 PM PDT 24 | 13775160000 ps | ||
| T39 | /workspace/coverage/default/11.prim_present_test.2582495125 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:25:02 PM PDT 24 | 13393860000 ps | ||
| T40 | /workspace/coverage/default/32.prim_present_test.1982887124 | Aug 02 04:23:24 PM PDT 24 | Aug 02 04:24:00 PM PDT 24 | 5208620000 ps | ||
| T41 | /workspace/coverage/default/23.prim_present_test.3498235139 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:19 PM PDT 24 | 9417800000 ps | ||
| T42 | /workspace/coverage/default/14.prim_present_test.149881820 | Aug 02 04:23:13 PM PDT 24 | Aug 02 04:24:38 PM PDT 24 | 10459400000 ps | ||
| T43 | /workspace/coverage/default/45.prim_present_test.3662425011 | Aug 02 04:23:24 PM PDT 24 | Aug 02 04:24:31 PM PDT 24 | 10845040000 ps | ||
| T44 | /workspace/coverage/default/44.prim_present_test.1441367327 | Aug 02 04:23:25 PM PDT 24 | Aug 02 04:24:37 PM PDT 24 | 11159380000 ps | ||
| T45 | /workspace/coverage/default/26.prim_present_test.1879147684 | Aug 02 04:23:13 PM PDT 24 | Aug 02 04:24:50 PM PDT 24 | 14079580000 ps | ||
| T46 | /workspace/coverage/default/39.prim_present_test.1566685522 | Aug 02 04:23:26 PM PDT 24 | Aug 02 04:23:57 PM PDT 24 | 4893040000 ps | ||
| T47 | /workspace/coverage/default/20.prim_present_test.193168142 | Aug 02 04:23:15 PM PDT 24 | Aug 02 04:24:14 PM PDT 24 | 8708520000 ps | ||
| T48 | /workspace/coverage/default/34.prim_present_test.2822496502 | Aug 02 04:23:26 PM PDT 24 | Aug 02 04:24:34 PM PDT 24 | 11007480000 ps | ||
| T49 | /workspace/coverage/default/43.prim_present_test.1934932339 | Aug 02 04:23:30 PM PDT 24 | Aug 02 04:24:52 PM PDT 24 | 11846340000 ps | ||
| T50 | /workspace/coverage/default/17.prim_present_test.3150975835 | Aug 02 04:23:14 PM PDT 24 | Aug 02 04:24:46 PM PDT 24 | 13243820000 ps |
| Test location | /workspace/coverage/default/19.prim_present_test.2207835041 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 14330680000 ps |
| CPU time | 51.07 seconds |
| Started | Aug 02 04:23:15 PM PDT 24 |
| Finished | Aug 02 04:24:51 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-95af9667-aea1-43ca-98b8-9c4f1cbe6cc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207835041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2207835041 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2697671902 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11993900000 ps |
| CPU time | 39.19 seconds |
| Started | Aug 02 04:23:11 PM PDT 24 |
| Finished | Aug 02 04:24:23 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-fea160d0-299f-4890-809e-f80e313fa6f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697671902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2697671902 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.375589866 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5271860000 ps |
| CPU time | 21.89 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:23:57 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-fd088e6a-b638-4772-aabf-5f1da516a041 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375589866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.375589866 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1541074720 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3598480000 ps |
| CPU time | 13.08 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:23:39 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-7d910e3e-805e-438b-b0e0-ad82711be221 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1541074720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1541074720 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2582495125 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13393860000 ps |
| CPU time | 56.18 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:25:02 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-8bd4ad39-2771-4a22-a472-4b407a1c318b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582495125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2582495125 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1230144188 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12776340000 ps |
| CPU time | 50.97 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:53 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-b2b500f6-caaa-4639-a9c3-ac8b760a0e3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230144188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1230144188 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.740671422 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13775160000 ps |
| CPU time | 57.13 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:25:05 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-aa3a067e-7990-4a8c-8cf9-d050f746223c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=740671422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.740671422 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.149881820 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10459400000 ps |
| CPU time | 43.73 seconds |
| Started | Aug 02 04:23:13 PM PDT 24 |
| Finished | Aug 02 04:24:38 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-1ce338d7-4793-4fe8-8af4-271ac83d55f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149881820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.149881820 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2422141797 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13198560000 ps |
| CPU time | 55.27 seconds |
| Started | Aug 02 04:23:23 PM PDT 24 |
| Finished | Aug 02 04:25:09 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-01a012cd-5538-4d0a-8e25-264ab73a5ac8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422141797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2422141797 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.100605662 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7931660000 ps |
| CPU time | 29.53 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:09 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-b841b310-6acd-462a-a2dc-00c52c299acc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100605662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.100605662 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3150975835 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13243820000 ps |
| CPU time | 48.08 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:46 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-877b1d08-49fe-4811-8b2c-18f9192e25e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150975835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3150975835 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1651360714 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10791100000 ps |
| CPU time | 45.86 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:42 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-299d5f1f-e5da-4346-a414-1e3adf856e37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651360714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1651360714 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1987391646 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 9228700000 ps |
| CPU time | 29.82 seconds |
| Started | Aug 02 04:23:15 PM PDT 24 |
| Finished | Aug 02 04:24:10 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-f994f662-4193-4119-93db-bff05b56173e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987391646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1987391646 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.193168142 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8708520000 ps |
| CPU time | 30.84 seconds |
| Started | Aug 02 04:23:15 PM PDT 24 |
| Finished | Aug 02 04:24:14 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-7977de1c-a550-4a1e-a295-88af39377efe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=193168142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.193168142 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1293727833 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8528720000 ps |
| CPU time | 31.01 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:12 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-ae6ab707-415e-4581-9047-dc3ecce37aea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293727833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1293727833 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.435375872 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11588420000 ps |
| CPU time | 42.5 seconds |
| Started | Aug 02 04:23:13 PM PDT 24 |
| Finished | Aug 02 04:24:33 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-ce25e738-1b70-4423-a43f-67f58488be23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435375872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.435375872 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3498235139 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9417800000 ps |
| CPU time | 34.47 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:19 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-c8b44729-c72c-40d1-b89c-e15a64a68ae2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498235139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3498235139 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3719685049 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12696980000 ps |
| CPU time | 42.55 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:33 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-83d89c83-08bd-4b6e-8467-59b01474916b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719685049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3719685049 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.102226502 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7262060000 ps |
| CPU time | 26.07 seconds |
| Started | Aug 02 04:23:13 PM PDT 24 |
| Finished | Aug 02 04:24:03 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-436628d5-3e0d-497f-bf7c-00ef20ed8c58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102226502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.102226502 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1879147684 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14079580000 ps |
| CPU time | 51.63 seconds |
| Started | Aug 02 04:23:13 PM PDT 24 |
| Finished | Aug 02 04:24:50 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-d8bfd146-7f2c-43c2-adec-158c0b077453 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879147684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1879147684 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3940621869 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10096080000 ps |
| CPU time | 37.22 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:25 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-6091e294-440b-4d34-a8e3-2ca68008663f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940621869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3940621869 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3934597622 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11343520000 ps |
| CPU time | 40.6 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:32 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-ac1a5460-e342-41bb-a69d-ef0576cfe016 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934597622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3934597622 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1069595997 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 15467760000 ps |
| CPU time | 49.7 seconds |
| Started | Aug 02 04:23:15 PM PDT 24 |
| Finished | Aug 02 04:24:47 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-ced7fa44-f91d-4b63-aab6-19476d855431 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069595997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1069595997 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.4258457175 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3325680000 ps |
| CPU time | 13.09 seconds |
| Started | Aug 02 04:23:13 PM PDT 24 |
| Finished | Aug 02 04:23:38 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-d6e6b5fe-0686-4200-a6ec-18a0d82cc929 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258457175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.4258457175 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3464212104 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4541500000 ps |
| CPU time | 17.69 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:23:47 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-bf88f547-d349-41a3-b3df-0ac3117127ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3464212104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3464212104 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.4055551661 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11132720000 ps |
| CPU time | 38.84 seconds |
| Started | Aug 02 04:23:15 PM PDT 24 |
| Finished | Aug 02 04:24:28 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-7c9e2407-f0c3-4db9-a58c-6db59519bd8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055551661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4055551661 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1982887124 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5208620000 ps |
| CPU time | 18.85 seconds |
| Started | Aug 02 04:23:24 PM PDT 24 |
| Finished | Aug 02 04:24:00 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-14918c7c-dae1-46e0-a69b-4d32f0d1701f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982887124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1982887124 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1228960500 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10720420000 ps |
| CPU time | 35.4 seconds |
| Started | Aug 02 04:23:24 PM PDT 24 |
| Finished | Aug 02 04:24:30 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-7650019d-7b4c-4ee4-ac0f-34dca1291f90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228960500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1228960500 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2822496502 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11007480000 ps |
| CPU time | 36.12 seconds |
| Started | Aug 02 04:23:26 PM PDT 24 |
| Finished | Aug 02 04:24:34 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-381719a5-a09c-49c6-a548-fdda33e696e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822496502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2822496502 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.51603589 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6474040000 ps |
| CPU time | 21.59 seconds |
| Started | Aug 02 04:24:27 PM PDT 24 |
| Finished | Aug 02 04:25:07 PM PDT 24 |
| Peak memory | 144692 kb |
| Host | smart-bdcba38c-fa5c-45e4-b7e5-d9fb0e8dad58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51603589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.51603589 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.811578183 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3370320000 ps |
| CPU time | 12.35 seconds |
| Started | Aug 02 04:23:26 PM PDT 24 |
| Finished | Aug 02 04:23:49 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-4cf03bef-a115-4b40-86a6-b437c92707e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811578183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.811578183 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.902673228 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8575220000 ps |
| CPU time | 34.67 seconds |
| Started | Aug 02 04:23:24 PM PDT 24 |
| Finished | Aug 02 04:24:31 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-7b31a197-4901-4fbf-85c2-93293a1ba810 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902673228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.902673228 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1907302752 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4137880000 ps |
| CPU time | 14.54 seconds |
| Started | Aug 02 04:23:24 PM PDT 24 |
| Finished | Aug 02 04:23:52 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-7a98edd8-fe0f-44a7-88e1-216b87dfd51d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907302752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1907302752 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1566685522 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4893040000 ps |
| CPU time | 16.88 seconds |
| Started | Aug 02 04:23:26 PM PDT 24 |
| Finished | Aug 02 04:23:57 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-f0a94af1-3428-430d-b8ba-2022ff22a666 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566685522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1566685522 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.997003568 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7687380000 ps |
| CPU time | 28.32 seconds |
| Started | Aug 02 04:23:12 PM PDT 24 |
| Finished | Aug 02 04:24:05 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-9252c9e0-773c-49c3-a818-64892bed3293 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997003568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.997003568 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2942447805 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3550120000 ps |
| CPU time | 12.77 seconds |
| Started | Aug 02 04:23:25 PM PDT 24 |
| Finished | Aug 02 04:23:49 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-5b742738-aa12-4ea5-a140-b2561633029f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2942447805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2942447805 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1862086492 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6420100000 ps |
| CPU time | 21.95 seconds |
| Started | Aug 02 04:23:23 PM PDT 24 |
| Finished | Aug 02 04:24:03 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-0ef92468-0452-4692-a16b-17ea1fdcf443 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862086492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1862086492 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1221993260 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 9198320000 ps |
| CPU time | 32.43 seconds |
| Started | Aug 02 04:23:24 PM PDT 24 |
| Finished | Aug 02 04:24:25 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-6be7d7f8-dfcc-48de-80c2-4dba63e0de21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221993260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1221993260 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1934932339 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11846340000 ps |
| CPU time | 43.57 seconds |
| Started | Aug 02 04:23:30 PM PDT 24 |
| Finished | Aug 02 04:24:52 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-5a969f65-5364-4570-8779-0e4ccc7de481 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934932339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1934932339 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1441367327 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11159380000 ps |
| CPU time | 39.02 seconds |
| Started | Aug 02 04:23:25 PM PDT 24 |
| Finished | Aug 02 04:24:37 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-d3ccc951-87c3-480c-a06b-d7e25ac0dfce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441367327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1441367327 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3662425011 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10845040000 ps |
| CPU time | 36.31 seconds |
| Started | Aug 02 04:23:24 PM PDT 24 |
| Finished | Aug 02 04:24:31 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-e5ad55ed-3b6c-4c7a-99bc-c7564b183b14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662425011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3662425011 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.597877515 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3531520000 ps |
| CPU time | 13.16 seconds |
| Started | Aug 02 04:23:24 PM PDT 24 |
| Finished | Aug 02 04:23:49 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-cf7039e2-e0fd-4c45-bece-8fa7277fa203 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=597877515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.597877515 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3341211661 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7683660000 ps |
| CPU time | 24.94 seconds |
| Started | Aug 02 04:24:25 PM PDT 24 |
| Finished | Aug 02 04:25:10 PM PDT 24 |
| Peak memory | 143052 kb |
| Host | smart-0bb9bc31-f868-4db3-9832-0bcd42443d62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341211661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3341211661 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3518780994 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6137380000 ps |
| CPU time | 19.56 seconds |
| Started | Aug 02 04:24:25 PM PDT 24 |
| Finished | Aug 02 04:25:00 PM PDT 24 |
| Peak memory | 143052 kb |
| Host | smart-404e5bdc-ffea-491e-87c5-efb886952bda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3518780994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3518780994 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2573731725 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12408680000 ps |
| CPU time | 34.93 seconds |
| Started | Aug 02 04:23:24 PM PDT 24 |
| Finished | Aug 02 04:24:28 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-858d9ef2-7afe-4625-8e9d-762e66f3540f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573731725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2573731725 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1059257363 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 12137120000 ps |
| CPU time | 50.05 seconds |
| Started | Aug 02 04:23:14 PM PDT 24 |
| Finished | Aug 02 04:24:51 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-f34fdd14-2a53-46a2-a4ea-629514489d39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059257363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1059257363 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3878567941 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11935620000 ps |
| CPU time | 43.86 seconds |
| Started | Aug 02 04:23:12 PM PDT 24 |
| Finished | Aug 02 04:24:35 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-0e277c60-c924-400c-8809-2a10d604c448 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3878567941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3878567941 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2132084514 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5695940000 ps |
| CPU time | 21.01 seconds |
| Started | Aug 02 04:23:12 PM PDT 24 |
| Finished | Aug 02 04:23:52 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-7863cd79-3a02-4f9f-a9d8-d5f6b89042dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132084514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2132084514 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3858876285 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12581040000 ps |
| CPU time | 44.16 seconds |
| Started | Aug 02 04:23:12 PM PDT 24 |
| Finished | Aug 02 04:24:35 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-e822ce7d-6e86-487e-a357-e237b8fa22d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3858876285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3858876285 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3801069453 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11545020000 ps |
| CPU time | 49.15 seconds |
| Started | Aug 02 04:23:13 PM PDT 24 |
| Finished | Aug 02 04:24:48 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-27cc9ec3-f8a3-46f6-a6bc-a12605f0f373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3801069453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3801069453 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |