| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/15.prim_present_test.4116683204 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3307093623 |
| /workspace/coverage/default/1.prim_present_test.1953636735 |
| /workspace/coverage/default/10.prim_present_test.1451160620 |
| /workspace/coverage/default/11.prim_present_test.3336524299 |
| /workspace/coverage/default/12.prim_present_test.1422403648 |
| /workspace/coverage/default/13.prim_present_test.884549148 |
| /workspace/coverage/default/14.prim_present_test.3050826075 |
| /workspace/coverage/default/16.prim_present_test.1216123774 |
| /workspace/coverage/default/17.prim_present_test.21646260 |
| /workspace/coverage/default/18.prim_present_test.154060814 |
| /workspace/coverage/default/19.prim_present_test.957734770 |
| /workspace/coverage/default/2.prim_present_test.4002778799 |
| /workspace/coverage/default/20.prim_present_test.2125650010 |
| /workspace/coverage/default/21.prim_present_test.2545788002 |
| /workspace/coverage/default/22.prim_present_test.2072494797 |
| /workspace/coverage/default/23.prim_present_test.1548031804 |
| /workspace/coverage/default/24.prim_present_test.1221434391 |
| /workspace/coverage/default/25.prim_present_test.3196618327 |
| /workspace/coverage/default/26.prim_present_test.818432278 |
| /workspace/coverage/default/27.prim_present_test.2538128699 |
| /workspace/coverage/default/28.prim_present_test.673025093 |
| /workspace/coverage/default/29.prim_present_test.3849738616 |
| /workspace/coverage/default/3.prim_present_test.518438621 |
| /workspace/coverage/default/30.prim_present_test.701572054 |
| /workspace/coverage/default/31.prim_present_test.456412654 |
| /workspace/coverage/default/32.prim_present_test.3416956517 |
| /workspace/coverage/default/33.prim_present_test.1940866536 |
| /workspace/coverage/default/34.prim_present_test.2266552370 |
| /workspace/coverage/default/35.prim_present_test.969210964 |
| /workspace/coverage/default/36.prim_present_test.1167024496 |
| /workspace/coverage/default/37.prim_present_test.1178389419 |
| /workspace/coverage/default/38.prim_present_test.1608719329 |
| /workspace/coverage/default/39.prim_present_test.1056341313 |
| /workspace/coverage/default/4.prim_present_test.4174656862 |
| /workspace/coverage/default/40.prim_present_test.320504486 |
| /workspace/coverage/default/41.prim_present_test.3930135341 |
| /workspace/coverage/default/42.prim_present_test.2256903368 |
| /workspace/coverage/default/43.prim_present_test.1210314110 |
| /workspace/coverage/default/44.prim_present_test.3208206766 |
| /workspace/coverage/default/45.prim_present_test.294187159 |
| /workspace/coverage/default/46.prim_present_test.4120440069 |
| /workspace/coverage/default/47.prim_present_test.2505229052 |
| /workspace/coverage/default/48.prim_present_test.2416284363 |
| /workspace/coverage/default/49.prim_present_test.3352096797 |
| /workspace/coverage/default/5.prim_present_test.447769957 |
| /workspace/coverage/default/6.prim_present_test.1114008972 |
| /workspace/coverage/default/7.prim_present_test.3560096360 |
| /workspace/coverage/default/8.prim_present_test.1837904990 |
| /workspace/coverage/default/9.prim_present_test.1640898491 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/15.prim_present_test.4116683204 | Aug 03 04:20:54 PM PDT 24 | Aug 03 04:22:29 PM PDT 24 | 14961840000 ps | ||
| T2 | /workspace/coverage/default/22.prim_present_test.2072494797 | Aug 03 04:19:24 PM PDT 24 | Aug 03 04:19:53 PM PDT 24 | 3381480000 ps | ||
| T3 | /workspace/coverage/default/42.prim_present_test.2256903368 | Aug 03 04:21:33 PM PDT 24 | Aug 03 04:21:53 PM PDT 24 | 3339940000 ps | ||
| T4 | /workspace/coverage/default/38.prim_present_test.1608719329 | Aug 03 04:18:38 PM PDT 24 | Aug 03 04:20:14 PM PDT 24 | 12427900000 ps | ||
| T5 | /workspace/coverage/default/17.prim_present_test.21646260 | Aug 03 04:20:50 PM PDT 24 | Aug 03 04:21:55 PM PDT 24 | 10938660000 ps | ||
| T6 | /workspace/coverage/default/2.prim_present_test.4002778799 | Aug 03 04:20:33 PM PDT 24 | Aug 03 04:21:49 PM PDT 24 | 10075000000 ps | ||
| T7 | /workspace/coverage/default/18.prim_present_test.154060814 | Aug 03 04:20:01 PM PDT 24 | Aug 03 04:21:07 PM PDT 24 | 8898860000 ps | ||
| T8 | /workspace/coverage/default/40.prim_present_test.320504486 | Aug 03 04:23:18 PM PDT 24 | Aug 03 04:24:48 PM PDT 24 | 15278660000 ps | ||
| T9 | /workspace/coverage/default/23.prim_present_test.1548031804 | Aug 03 04:23:17 PM PDT 24 | Aug 03 04:23:42 PM PDT 24 | 3902900000 ps | ||
| T10 | /workspace/coverage/default/21.prim_present_test.2545788002 | Aug 03 04:20:50 PM PDT 24 | Aug 03 04:21:33 PM PDT 24 | 6878280000 ps | ||
| T11 | /workspace/coverage/default/10.prim_present_test.1451160620 | Aug 03 04:20:41 PM PDT 24 | Aug 03 04:22:09 PM PDT 24 | 11917640000 ps | ||
| T12 | /workspace/coverage/default/0.prim_present_test.3307093623 | Aug 03 04:18:57 PM PDT 24 | Aug 03 04:20:06 PM PDT 24 | 8368140000 ps | ||
| T13 | /workspace/coverage/default/30.prim_present_test.701572054 | Aug 03 04:21:01 PM PDT 24 | Aug 03 04:21:41 PM PDT 24 | 5416940000 ps | ||
| T14 | /workspace/coverage/default/39.prim_present_test.1056341313 | Aug 03 04:21:15 PM PDT 24 | Aug 03 04:22:35 PM PDT 24 | 13239480000 ps | ||
| T15 | /workspace/coverage/default/9.prim_present_test.1640898491 | Aug 03 04:18:51 PM PDT 24 | Aug 03 04:19:46 PM PDT 24 | 6700340000 ps | ||
| T16 | /workspace/coverage/default/37.prim_present_test.1178389419 | Aug 03 04:20:50 PM PDT 24 | Aug 03 04:21:52 PM PDT 24 | 9207620000 ps | ||
| T17 | /workspace/coverage/default/7.prim_present_test.3560096360 | Aug 03 04:18:35 PM PDT 24 | Aug 03 04:20:37 PM PDT 24 | 15300360000 ps | ||
| T18 | /workspace/coverage/default/45.prim_present_test.294187159 | Aug 03 04:18:40 PM PDT 24 | Aug 03 04:19:24 PM PDT 24 | 5699660000 ps | ||
| T19 | /workspace/coverage/default/25.prim_present_test.3196618327 | Aug 03 04:18:53 PM PDT 24 | Aug 03 04:20:36 PM PDT 24 | 12734800000 ps | ||
| T20 | /workspace/coverage/default/27.prim_present_test.2538128699 | Aug 03 04:18:38 PM PDT 24 | Aug 03 04:19:17 PM PDT 24 | 5550240000 ps | ||
| T21 | /workspace/coverage/default/13.prim_present_test.884549148 | Aug 03 04:19:21 PM PDT 24 | Aug 03 04:20:28 PM PDT 24 | 8284440000 ps | ||
| T22 | /workspace/coverage/default/31.prim_present_test.456412654 | Aug 03 04:19:41 PM PDT 24 | Aug 03 04:21:12 PM PDT 24 | 11594000000 ps | ||
| T23 | /workspace/coverage/default/6.prim_present_test.1114008972 | Aug 03 04:18:51 PM PDT 24 | Aug 03 04:20:56 PM PDT 24 | 15214180000 ps | ||
| T24 | /workspace/coverage/default/3.prim_present_test.518438621 | Aug 03 04:19:32 PM PDT 24 | Aug 03 04:20:53 PM PDT 24 | 10127080000 ps | ||
| T25 | /workspace/coverage/default/8.prim_present_test.1837904990 | Aug 03 04:18:36 PM PDT 24 | Aug 03 04:19:49 PM PDT 24 | 10332300000 ps | ||
| T26 | /workspace/coverage/default/35.prim_present_test.969210964 | Aug 03 04:19:37 PM PDT 24 | Aug 03 04:21:10 PM PDT 24 | 10972760000 ps | ||
| T27 | /workspace/coverage/default/47.prim_present_test.2505229052 | Aug 03 04:20:10 PM PDT 24 | Aug 03 04:21:23 PM PDT 24 | 8371860000 ps | ||
| T28 | /workspace/coverage/default/16.prim_present_test.1216123774 | Aug 03 04:21:17 PM PDT 24 | Aug 03 04:22:21 PM PDT 24 | 12003200000 ps | ||
| T29 | /workspace/coverage/default/49.prim_present_test.3352096797 | Aug 03 04:18:42 PM PDT 24 | Aug 03 04:19:54 PM PDT 24 | 10141340000 ps | ||
| T30 | /workspace/coverage/default/36.prim_present_test.1167024496 | Aug 03 04:24:00 PM PDT 24 | Aug 03 04:25:09 PM PDT 24 | 12850740000 ps | ||
| T31 | /workspace/coverage/default/4.prim_present_test.4174656862 | Aug 03 04:21:38 PM PDT 24 | Aug 03 04:22:01 PM PDT 24 | 3631960000 ps | ||
| T32 | /workspace/coverage/default/20.prim_present_test.2125650010 | Aug 03 04:20:56 PM PDT 24 | Aug 03 04:21:18 PM PDT 24 | 3498040000 ps | ||
| T33 | /workspace/coverage/default/14.prim_present_test.3050826075 | Aug 03 04:23:18 PM PDT 24 | Aug 03 04:24:16 PM PDT 24 | 9393000000 ps | ||
| T34 | /workspace/coverage/default/32.prim_present_test.3416956517 | Aug 03 04:20:54 PM PDT 24 | Aug 03 04:21:24 PM PDT 24 | 4628920000 ps | ||
| T35 | /workspace/coverage/default/28.prim_present_test.673025093 | Aug 03 04:21:55 PM PDT 24 | Aug 03 04:22:46 PM PDT 24 | 7358780000 ps | ||
| T36 | /workspace/coverage/default/1.prim_present_test.1953636735 | Aug 03 04:18:39 PM PDT 24 | Aug 03 04:19:53 PM PDT 24 | 9172900000 ps | ||
| T37 | /workspace/coverage/default/46.prim_present_test.4120440069 | Aug 03 04:18:40 PM PDT 24 | Aug 03 04:20:25 PM PDT 24 | 13341780000 ps | ||
| T38 | /workspace/coverage/default/11.prim_present_test.3336524299 | Aug 03 04:20:45 PM PDT 24 | Aug 03 04:22:16 PM PDT 24 | 12905300000 ps | ||
| T39 | /workspace/coverage/default/48.prim_present_test.2416284363 | Aug 03 04:20:50 PM PDT 24 | Aug 03 04:22:04 PM PDT 24 | 10931220000 ps | ||
| T40 | /workspace/coverage/default/29.prim_present_test.3849738616 | Aug 03 04:20:36 PM PDT 24 | Aug 03 04:21:44 PM PDT 24 | 8796560000 ps | ||
| T41 | /workspace/coverage/default/26.prim_present_test.818432278 | Aug 03 04:23:18 PM PDT 24 | Aug 03 04:23:42 PM PDT 24 | 3498660000 ps | ||
| T42 | /workspace/coverage/default/44.prim_present_test.3208206766 | Aug 03 04:19:48 PM PDT 24 | Aug 03 04:20:54 PM PDT 24 | 10907040000 ps | ||
| T43 | /workspace/coverage/default/5.prim_present_test.447769957 | Aug 03 04:18:42 PM PDT 24 | Aug 03 04:19:58 PM PDT 24 | 10383140000 ps | ||
| T44 | /workspace/coverage/default/43.prim_present_test.1210314110 | Aug 03 04:20:44 PM PDT 24 | Aug 03 04:21:11 PM PDT 24 | 4642560000 ps | ||
| T45 | /workspace/coverage/default/41.prim_present_test.3930135341 | Aug 03 04:21:28 PM PDT 24 | Aug 03 04:21:50 PM PDT 24 | 3217180000 ps | ||
| T46 | /workspace/coverage/default/24.prim_present_test.1221434391 | Aug 03 04:21:06 PM PDT 24 | Aug 03 04:21:55 PM PDT 24 | 7115740000 ps | ||
| T47 | /workspace/coverage/default/34.prim_present_test.2266552370 | Aug 03 04:23:33 PM PDT 24 | Aug 03 04:24:57 PM PDT 24 | 14292860000 ps | ||
| T48 | /workspace/coverage/default/33.prim_present_test.1940866536 | Aug 03 04:20:24 PM PDT 24 | Aug 03 04:21:13 PM PDT 24 | 6272540000 ps | ||
| T49 | /workspace/coverage/default/12.prim_present_test.1422403648 | Aug 03 04:18:38 PM PDT 24 | Aug 03 04:20:12 PM PDT 24 | 11828360000 ps | ||
| T50 | /workspace/coverage/default/19.prim_present_test.957734770 | Aug 03 04:18:49 PM PDT 24 | Aug 03 04:19:38 PM PDT 24 | 6261380000 ps |
| Test location | /workspace/coverage/default/15.prim_present_test.4116683204 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14961840000 ps |
| CPU time | 51.7 seconds |
| Started | Aug 03 04:20:54 PM PDT 24 |
| Finished | Aug 03 04:22:29 PM PDT 24 |
| Peak memory | 144788 kb |
| Host | smart-a780a054-85c9-4976-9b05-f3a46239bd47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4116683204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.4116683204 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3307093623 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8368140000 ps |
| CPU time | 35.27 seconds |
| Started | Aug 03 04:18:57 PM PDT 24 |
| Finished | Aug 03 04:20:06 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-89a5d837-78aa-4516-be54-a1a7cc689536 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307093623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3307093623 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1953636735 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9172900000 ps |
| CPU time | 38.89 seconds |
| Started | Aug 03 04:18:39 PM PDT 24 |
| Finished | Aug 03 04:19:53 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-3bf33513-148f-480a-8d3e-b396952aa8b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1953636735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1953636735 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1451160620 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11917640000 ps |
| CPU time | 46.61 seconds |
| Started | Aug 03 04:20:41 PM PDT 24 |
| Finished | Aug 03 04:22:09 PM PDT 24 |
| Peak memory | 143064 kb |
| Host | smart-07214ae1-dbbb-4eaa-b2c5-a6f4eb669c64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451160620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1451160620 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3336524299 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12905300000 ps |
| CPU time | 48.12 seconds |
| Started | Aug 03 04:20:45 PM PDT 24 |
| Finished | Aug 03 04:22:16 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-4ae6ba68-996d-4d81-9311-320562a07127 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3336524299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3336524299 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1422403648 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11828360000 ps |
| CPU time | 49.04 seconds |
| Started | Aug 03 04:18:38 PM PDT 24 |
| Finished | Aug 03 04:20:12 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-b4a5f99d-9f0c-4dc8-8786-7b23f4120a97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422403648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1422403648 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.884549148 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8284440000 ps |
| CPU time | 34.47 seconds |
| Started | Aug 03 04:19:21 PM PDT 24 |
| Finished | Aug 03 04:20:28 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-799555f2-a55b-4cd3-963c-ed114358897f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884549148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.884549148 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3050826075 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9393000000 ps |
| CPU time | 31.79 seconds |
| Started | Aug 03 04:23:18 PM PDT 24 |
| Finished | Aug 03 04:24:16 PM PDT 24 |
| Peak memory | 144012 kb |
| Host | smart-d17626d0-6c8d-42d5-a1e7-54d3b1551196 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050826075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3050826075 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1216123774 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12003200000 ps |
| CPU time | 35.65 seconds |
| Started | Aug 03 04:21:17 PM PDT 24 |
| Finished | Aug 03 04:22:21 PM PDT 24 |
| Peak memory | 144020 kb |
| Host | smart-49934a46-8203-493f-8da7-2d9492a4e7cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216123774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1216123774 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.21646260 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 10938660000 ps |
| CPU time | 35.74 seconds |
| Started | Aug 03 04:20:50 PM PDT 24 |
| Finished | Aug 03 04:21:55 PM PDT 24 |
| Peak memory | 143788 kb |
| Host | smart-b414b01c-e9a7-4897-971b-afe5e7147e36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21646260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.21646260 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.154060814 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8898860000 ps |
| CPU time | 34.79 seconds |
| Started | Aug 03 04:20:01 PM PDT 24 |
| Finished | Aug 03 04:21:07 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-5e4a26c8-9925-4bc0-8ef6-17fe4c024dc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154060814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.154060814 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.957734770 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6261380000 ps |
| CPU time | 25.45 seconds |
| Started | Aug 03 04:18:49 PM PDT 24 |
| Finished | Aug 03 04:19:38 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-e3cb0803-266e-4850-b097-5e57772ce390 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=957734770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.957734770 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4002778799 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 10075000000 ps |
| CPU time | 40.08 seconds |
| Started | Aug 03 04:20:33 PM PDT 24 |
| Finished | Aug 03 04:21:49 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-a585fe29-fd53-4b60-b293-c78b2d29ec67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4002778799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4002778799 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2125650010 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3498040000 ps |
| CPU time | 12.03 seconds |
| Started | Aug 03 04:20:56 PM PDT 24 |
| Finished | Aug 03 04:21:18 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-9d43c482-a451-40b8-b3b9-aa00844d1665 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125650010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2125650010 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2545788002 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6878280000 ps |
| CPU time | 23.5 seconds |
| Started | Aug 03 04:20:50 PM PDT 24 |
| Finished | Aug 03 04:21:33 PM PDT 24 |
| Peak memory | 144556 kb |
| Host | smart-6e9b6565-acb9-4dfa-9968-12fe368e0621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545788002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2545788002 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2072494797 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3381480000 ps |
| CPU time | 14.98 seconds |
| Started | Aug 03 04:19:24 PM PDT 24 |
| Finished | Aug 03 04:19:53 PM PDT 24 |
| Peak memory | 144856 kb |
| Host | smart-ebabfeac-bd2c-401f-abc7-ff8db0070a68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072494797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2072494797 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1548031804 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3902900000 ps |
| CPU time | 13.25 seconds |
| Started | Aug 03 04:23:17 PM PDT 24 |
| Finished | Aug 03 04:23:42 PM PDT 24 |
| Peak memory | 143548 kb |
| Host | smart-1a1dfb7b-41f9-4bad-b0cc-6cf35658cc23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548031804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1548031804 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1221434391 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7115740000 ps |
| CPU time | 26.57 seconds |
| Started | Aug 03 04:21:06 PM PDT 24 |
| Finished | Aug 03 04:21:55 PM PDT 24 |
| Peak memory | 144716 kb |
| Host | smart-414cdf70-1530-46b4-8f0c-2e9094e81e0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221434391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1221434391 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3196618327 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12734800000 ps |
| CPU time | 53.16 seconds |
| Started | Aug 03 04:18:53 PM PDT 24 |
| Finished | Aug 03 04:20:36 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-fdc35c25-9f4f-455d-be92-64e7f17bc6e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196618327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3196618327 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.818432278 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3498660000 ps |
| CPU time | 12.64 seconds |
| Started | Aug 03 04:23:18 PM PDT 24 |
| Finished | Aug 03 04:23:42 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-c0a15c17-3f8e-4305-ad42-0787e53c11e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818432278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.818432278 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2538128699 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5550240000 ps |
| CPU time | 21.01 seconds |
| Started | Aug 03 04:18:38 PM PDT 24 |
| Finished | Aug 03 04:19:17 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-b980a99e-b147-433d-a704-521177150f3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538128699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2538128699 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.673025093 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7358780000 ps |
| CPU time | 27.15 seconds |
| Started | Aug 03 04:21:55 PM PDT 24 |
| Finished | Aug 03 04:22:46 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-7aecfc75-737a-4c2f-a94a-fd79407474c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=673025093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.673025093 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3849738616 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8796560000 ps |
| CPU time | 34.96 seconds |
| Started | Aug 03 04:20:36 PM PDT 24 |
| Finished | Aug 03 04:21:44 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-7534864f-2cba-4296-a753-8d72d7df52a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849738616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3849738616 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.518438621 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10127080000 ps |
| CPU time | 41.92 seconds |
| Started | Aug 03 04:19:32 PM PDT 24 |
| Finished | Aug 03 04:20:53 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-af81f49a-dfb0-4c47-b42f-8fb9b45f7adc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=518438621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.518438621 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.701572054 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5416940000 ps |
| CPU time | 20.69 seconds |
| Started | Aug 03 04:21:01 PM PDT 24 |
| Finished | Aug 03 04:21:41 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-a332ccd4-c93a-42d8-b01e-6923dac7855c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701572054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.701572054 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.456412654 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11594000000 ps |
| CPU time | 47.33 seconds |
| Started | Aug 03 04:19:41 PM PDT 24 |
| Finished | Aug 03 04:21:12 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-136f3ec7-27d1-4746-8469-664a4b956150 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456412654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.456412654 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3416956517 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4628920000 ps |
| CPU time | 15.93 seconds |
| Started | Aug 03 04:20:54 PM PDT 24 |
| Finished | Aug 03 04:21:24 PM PDT 24 |
| Peak memory | 144716 kb |
| Host | smart-ecd41e45-a390-42aa-8b6f-a47b6ed792e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416956517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3416956517 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1940866536 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6272540000 ps |
| CPU time | 25.79 seconds |
| Started | Aug 03 04:20:24 PM PDT 24 |
| Finished | Aug 03 04:21:13 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-10a400a1-7482-4e43-8d63-ea617fca1337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940866536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1940866536 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2266552370 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14292860000 ps |
| CPU time | 45.67 seconds |
| Started | Aug 03 04:23:33 PM PDT 24 |
| Finished | Aug 03 04:24:57 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-10fce70b-c59b-42c6-9d3b-52bec1aa0cfc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266552370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2266552370 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.969210964 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10972760000 ps |
| CPU time | 47.6 seconds |
| Started | Aug 03 04:19:37 PM PDT 24 |
| Finished | Aug 03 04:21:10 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-5ab85e55-70f0-4824-b5c3-17274a604246 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=969210964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.969210964 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1167024496 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 12850740000 ps |
| CPU time | 37.19 seconds |
| Started | Aug 03 04:24:00 PM PDT 24 |
| Finished | Aug 03 04:25:09 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-0658e3b0-d393-4e96-8d76-8b88fdec432b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167024496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1167024496 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1178389419 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9207620000 ps |
| CPU time | 33.53 seconds |
| Started | Aug 03 04:20:50 PM PDT 24 |
| Finished | Aug 03 04:21:52 PM PDT 24 |
| Peak memory | 143592 kb |
| Host | smart-e0ef0065-514f-43a1-bcf0-1b8f1edf583f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178389419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1178389419 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1608719329 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12427900000 ps |
| CPU time | 50.14 seconds |
| Started | Aug 03 04:18:38 PM PDT 24 |
| Finished | Aug 03 04:20:14 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-0b39221d-df24-4545-8b61-773e37392745 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608719329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1608719329 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1056341313 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13239480000 ps |
| CPU time | 44.3 seconds |
| Started | Aug 03 04:21:15 PM PDT 24 |
| Finished | Aug 03 04:22:35 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-c530c769-54e4-4fe4-b99d-e09d1e1cd9d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056341313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1056341313 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4174656862 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3631960000 ps |
| CPU time | 12.48 seconds |
| Started | Aug 03 04:21:38 PM PDT 24 |
| Finished | Aug 03 04:22:01 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-7b39a2f1-fef2-4669-8f5a-41b57b6e930c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174656862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4174656862 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.320504486 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 15278660000 ps |
| CPU time | 49.13 seconds |
| Started | Aug 03 04:23:18 PM PDT 24 |
| Finished | Aug 03 04:24:48 PM PDT 24 |
| Peak memory | 144808 kb |
| Host | smart-fdb080c6-fc20-4d63-a30a-bcb546c69170 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320504486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.320504486 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3930135341 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3217180000 ps |
| CPU time | 11.95 seconds |
| Started | Aug 03 04:21:28 PM PDT 24 |
| Finished | Aug 03 04:21:50 PM PDT 24 |
| Peak memory | 143560 kb |
| Host | smart-a0651ebb-e3f9-491f-837d-4b152c4471dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930135341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3930135341 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2256903368 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3339940000 ps |
| CPU time | 10.78 seconds |
| Started | Aug 03 04:21:33 PM PDT 24 |
| Finished | Aug 03 04:21:53 PM PDT 24 |
| Peak memory | 144536 kb |
| Host | smart-cc1a26f8-4f6d-4990-9668-45026d2cdae0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256903368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2256903368 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1210314110 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4642560000 ps |
| CPU time | 14.83 seconds |
| Started | Aug 03 04:20:44 PM PDT 24 |
| Finished | Aug 03 04:21:11 PM PDT 24 |
| Peak memory | 144592 kb |
| Host | smart-b27633a5-e13c-4eae-a25a-89c6530565b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210314110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1210314110 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3208206766 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10907040000 ps |
| CPU time | 35.83 seconds |
| Started | Aug 03 04:19:48 PM PDT 24 |
| Finished | Aug 03 04:20:54 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-3bb352a5-a45f-49ea-bbe3-c75834e5de68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208206766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3208206766 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.294187159 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5699660000 ps |
| CPU time | 22.97 seconds |
| Started | Aug 03 04:18:40 PM PDT 24 |
| Finished | Aug 03 04:19:24 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-afb11ea5-b954-4c97-a8b8-2482b29b749a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294187159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.294187159 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4120440069 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13341780000 ps |
| CPU time | 54.18 seconds |
| Started | Aug 03 04:18:40 PM PDT 24 |
| Finished | Aug 03 04:20:25 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-04443a78-633e-4e23-b042-40d1f8a66b60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120440069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4120440069 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2505229052 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8371860000 ps |
| CPU time | 37.97 seconds |
| Started | Aug 03 04:20:10 PM PDT 24 |
| Finished | Aug 03 04:21:23 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-530345b5-fa56-44db-90bf-1f15afa85d8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505229052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2505229052 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2416284363 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10931220000 ps |
| CPU time | 40.04 seconds |
| Started | Aug 03 04:20:50 PM PDT 24 |
| Finished | Aug 03 04:22:04 PM PDT 24 |
| Peak memory | 143588 kb |
| Host | smart-58189f9c-c3a8-4571-84ad-1dc8365fe487 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416284363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2416284363 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3352096797 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10141340000 ps |
| CPU time | 38.4 seconds |
| Started | Aug 03 04:18:42 PM PDT 24 |
| Finished | Aug 03 04:19:54 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-2ea98f9e-eeca-4fc4-a8f7-dce1ee6442cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352096797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3352096797 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.447769957 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10383140000 ps |
| CPU time | 40.06 seconds |
| Started | Aug 03 04:18:42 PM PDT 24 |
| Finished | Aug 03 04:19:58 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-9c116a09-216f-459e-8131-e482629c14d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447769957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.447769957 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1114008972 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 15214180000 ps |
| CPU time | 64.75 seconds |
| Started | Aug 03 04:18:51 PM PDT 24 |
| Finished | Aug 03 04:20:56 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-823a3e75-8686-4ca3-9c5a-e792d7899984 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114008972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1114008972 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3560096360 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 15300360000 ps |
| CPU time | 62.98 seconds |
| Started | Aug 03 04:18:35 PM PDT 24 |
| Finished | Aug 03 04:20:37 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-227d3d64-2c38-4b51-bb8d-5bea43c2dd14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560096360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3560096360 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1837904990 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10332300000 ps |
| CPU time | 38.7 seconds |
| Started | Aug 03 04:18:36 PM PDT 24 |
| Finished | Aug 03 04:19:49 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-b42b3e70-ca72-402c-b226-7f05a6869159 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837904990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1837904990 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1640898491 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6700340000 ps |
| CPU time | 28.17 seconds |
| Started | Aug 03 04:18:51 PM PDT 24 |
| Finished | Aug 03 04:19:46 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-22cdae42-6af6-40d4-bb16-e8ff0e63f5ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640898491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1640898491 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |