Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.83 90.41 100.00 98.73 100.00 100.00


Total tests in report: 50
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
97.83 97.83 90.41 90.41 100.00 100.00 98.73 98.73 100.00 100.00 100.00 100.00 /workspace/coverage/default/11.prim_present_test.948735446


Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_present_test.1614870587
/workspace/coverage/default/1.prim_present_test.2204443591
/workspace/coverage/default/10.prim_present_test.1728022211
/workspace/coverage/default/12.prim_present_test.2294162143
/workspace/coverage/default/13.prim_present_test.4167572174
/workspace/coverage/default/14.prim_present_test.3028644881
/workspace/coverage/default/15.prim_present_test.3224092310
/workspace/coverage/default/16.prim_present_test.2487154843
/workspace/coverage/default/17.prim_present_test.3346647843
/workspace/coverage/default/18.prim_present_test.3751891422
/workspace/coverage/default/19.prim_present_test.3184311610
/workspace/coverage/default/2.prim_present_test.1424237070
/workspace/coverage/default/20.prim_present_test.3094014142
/workspace/coverage/default/21.prim_present_test.1825209970
/workspace/coverage/default/22.prim_present_test.1717794046
/workspace/coverage/default/23.prim_present_test.810195930
/workspace/coverage/default/24.prim_present_test.646151871
/workspace/coverage/default/25.prim_present_test.3604926320
/workspace/coverage/default/26.prim_present_test.759984793
/workspace/coverage/default/27.prim_present_test.953831230
/workspace/coverage/default/28.prim_present_test.1106127212
/workspace/coverage/default/29.prim_present_test.1181090790
/workspace/coverage/default/3.prim_present_test.4268252465
/workspace/coverage/default/30.prim_present_test.4181372677
/workspace/coverage/default/31.prim_present_test.58082603
/workspace/coverage/default/32.prim_present_test.1496233319
/workspace/coverage/default/33.prim_present_test.34254123
/workspace/coverage/default/34.prim_present_test.678441331
/workspace/coverage/default/35.prim_present_test.2920828778
/workspace/coverage/default/36.prim_present_test.3612652158
/workspace/coverage/default/37.prim_present_test.2754255423
/workspace/coverage/default/38.prim_present_test.147813404
/workspace/coverage/default/39.prim_present_test.655476161
/workspace/coverage/default/4.prim_present_test.2825573099
/workspace/coverage/default/40.prim_present_test.489916554
/workspace/coverage/default/41.prim_present_test.2616641956
/workspace/coverage/default/42.prim_present_test.2831229227
/workspace/coverage/default/43.prim_present_test.2964538814
/workspace/coverage/default/44.prim_present_test.2294428232
/workspace/coverage/default/45.prim_present_test.4022031368
/workspace/coverage/default/46.prim_present_test.3754805226
/workspace/coverage/default/47.prim_present_test.667645259
/workspace/coverage/default/48.prim_present_test.91737495
/workspace/coverage/default/49.prim_present_test.4200801553
/workspace/coverage/default/5.prim_present_test.1288322437
/workspace/coverage/default/6.prim_present_test.2544108945
/workspace/coverage/default/7.prim_present_test.3833720738
/workspace/coverage/default/8.prim_present_test.2146411448
/workspace/coverage/default/9.prim_present_test.3796243600




Total test records in report: 50
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/5.prim_present_test.1288322437 Aug 04 04:19:29 PM PDT 24 Aug 04 04:20:53 PM PDT 24 12158200000 ps
T2 /workspace/coverage/default/8.prim_present_test.2146411448 Aug 04 04:19:27 PM PDT 24 Aug 04 04:20:24 PM PDT 24 8441300000 ps
T3 /workspace/coverage/default/3.prim_present_test.4268252465 Aug 04 04:19:21 PM PDT 24 Aug 04 04:20:23 PM PDT 24 8914360000 ps
T4 /workspace/coverage/default/47.prim_present_test.667645259 Aug 04 04:20:42 PM PDT 24 Aug 04 04:21:47 PM PDT 24 8301180000 ps
T5 /workspace/coverage/default/42.prim_present_test.2831229227 Aug 04 04:19:31 PM PDT 24 Aug 04 04:20:00 PM PDT 24 4336280000 ps
T6 /workspace/coverage/default/49.prim_present_test.4200801553 Aug 04 04:19:32 PM PDT 24 Aug 04 04:20:14 PM PDT 24 5994780000 ps
T7 /workspace/coverage/default/20.prim_present_test.3094014142 Aug 04 04:19:28 PM PDT 24 Aug 04 04:20:42 PM PDT 24 10447000000 ps
T8 /workspace/coverage/default/9.prim_present_test.3796243600 Aug 04 04:19:22 PM PDT 24 Aug 04 04:20:49 PM PDT 24 12297080000 ps
T9 /workspace/coverage/default/11.prim_present_test.948735446 Aug 04 04:19:22 PM PDT 24 Aug 04 04:20:18 PM PDT 24 8236700000 ps
T10 /workspace/coverage/default/12.prim_present_test.2294162143 Aug 04 04:19:21 PM PDT 24 Aug 04 04:20:01 PM PDT 24 5635180000 ps
T11 /workspace/coverage/default/23.prim_present_test.810195930 Aug 04 04:19:25 PM PDT 24 Aug 04 04:19:51 PM PDT 24 3905380000 ps
T12 /workspace/coverage/default/0.prim_present_test.1614870587 Aug 04 04:19:17 PM PDT 24 Aug 04 04:20:02 PM PDT 24 7113260000 ps
T13 /workspace/coverage/default/45.prim_present_test.4022031368 Aug 04 04:19:31 PM PDT 24 Aug 04 04:21:12 PM PDT 24 14433600000 ps
T14 /workspace/coverage/default/44.prim_present_test.2294428232 Aug 04 04:20:03 PM PDT 24 Aug 04 04:20:51 PM PDT 24 7426980000 ps
T15 /workspace/coverage/default/13.prim_present_test.4167572174 Aug 04 04:19:26 PM PDT 24 Aug 04 04:21:08 PM PDT 24 15022600000 ps
T16 /workspace/coverage/default/2.prim_present_test.1424237070 Aug 04 04:19:22 PM PDT 24 Aug 04 04:19:59 PM PDT 24 5255740000 ps
T17 /workspace/coverage/default/21.prim_present_test.1825209970 Aug 04 04:19:27 PM PDT 24 Aug 04 04:19:58 PM PDT 24 3632580000 ps
T18 /workspace/coverage/default/41.prim_present_test.2616641956 Aug 04 04:19:32 PM PDT 24 Aug 04 04:20:28 PM PDT 24 8932340000 ps
T19 /workspace/coverage/default/28.prim_present_test.1106127212 Aug 04 04:19:27 PM PDT 24 Aug 04 04:20:01 PM PDT 24 3837180000 ps
T20 /workspace/coverage/default/7.prim_present_test.3833720738 Aug 04 04:19:27 PM PDT 24 Aug 04 04:21:23 PM PDT 24 14418100000 ps
T21 /workspace/coverage/default/18.prim_present_test.3751891422 Aug 04 04:19:17 PM PDT 24 Aug 04 04:19:45 PM PDT 24 4092620000 ps
T22 /workspace/coverage/default/24.prim_present_test.646151871 Aug 04 04:19:27 PM PDT 24 Aug 04 04:20:13 PM PDT 24 5413220000 ps
T23 /workspace/coverage/default/14.prim_present_test.3028644881 Aug 04 04:19:27 PM PDT 24 Aug 04 04:20:57 PM PDT 24 13269860000 ps
T24 /workspace/coverage/default/35.prim_present_test.2920828778 Aug 04 04:20:42 PM PDT 24 Aug 04 04:21:43 PM PDT 24 8120140000 ps
T25 /workspace/coverage/default/6.prim_present_test.2544108945 Aug 04 04:19:29 PM PDT 24 Aug 04 04:21:10 PM PDT 24 15028800000 ps
T26 /workspace/coverage/default/26.prim_present_test.759984793 Aug 04 04:19:25 PM PDT 24 Aug 04 04:20:09 PM PDT 24 6961980000 ps
T27 /workspace/coverage/default/4.prim_present_test.2825573099 Aug 04 04:19:28 PM PDT 24 Aug 04 04:20:42 PM PDT 24 10672680000 ps
T28 /workspace/coverage/default/19.prim_present_test.3184311610 Aug 04 04:19:26 PM PDT 24 Aug 04 04:19:48 PM PDT 24 3126040000 ps
T29 /workspace/coverage/default/36.prim_present_test.3612652158 Aug 04 04:19:58 PM PDT 24 Aug 04 04:20:36 PM PDT 24 4916600000 ps
T30 /workspace/coverage/default/37.prim_present_test.2754255423 Aug 04 04:20:32 PM PDT 24 Aug 04 04:21:15 PM PDT 24 6072280000 ps
T31 /workspace/coverage/default/48.prim_present_test.91737495 Aug 04 04:19:32 PM PDT 24 Aug 04 04:20:49 PM PDT 24 10758240000 ps
T32 /workspace/coverage/default/43.prim_present_test.2964538814 Aug 04 04:19:31 PM PDT 24 Aug 04 04:21:06 PM PDT 24 13568700000 ps
T33 /workspace/coverage/default/17.prim_present_test.3346647843 Aug 04 04:19:26 PM PDT 24 Aug 04 04:20:56 PM PDT 24 12909020000 ps
T34 /workspace/coverage/default/40.prim_present_test.489916554 Aug 04 04:19:32 PM PDT 24 Aug 04 04:21:02 PM PDT 24 13877460000 ps
T35 /workspace/coverage/default/46.prim_present_test.3754805226 Aug 04 04:20:32 PM PDT 24 Aug 04 04:21:51 PM PDT 24 10487920000 ps
T36 /workspace/coverage/default/38.prim_present_test.147813404 Aug 04 04:20:42 PM PDT 24 Aug 04 04:22:01 PM PDT 24 10461880000 ps
T37 /workspace/coverage/default/30.prim_present_test.4181372677 Aug 04 04:20:41 PM PDT 24 Aug 04 04:21:56 PM PDT 24 10181020000 ps
T38 /workspace/coverage/default/32.prim_present_test.1496233319 Aug 04 04:20:32 PM PDT 24 Aug 04 04:21:23 PM PDT 24 6568280000 ps
T39 /workspace/coverage/default/33.prim_present_test.34254123 Aug 04 04:19:18 PM PDT 24 Aug 04 04:20:00 PM PDT 24 6576340000 ps
T40 /workspace/coverage/default/39.prim_present_test.655476161 Aug 04 04:19:17 PM PDT 24 Aug 04 04:20:09 PM PDT 24 8539260000 ps
T41 /workspace/coverage/default/25.prim_present_test.3604926320 Aug 04 04:19:27 PM PDT 24 Aug 04 04:20:12 PM PDT 24 5292320000 ps
T42 /workspace/coverage/default/1.prim_present_test.2204443591 Aug 04 04:19:29 PM PDT 24 Aug 04 04:20:00 PM PDT 24 4508020000 ps
T43 /workspace/coverage/default/10.prim_present_test.1728022211 Aug 04 04:19:29 PM PDT 24 Aug 04 04:20:51 PM PDT 24 11316240000 ps
T44 /workspace/coverage/default/16.prim_present_test.2487154843 Aug 04 04:19:26 PM PDT 24 Aug 04 04:20:55 PM PDT 24 13064020000 ps
T45 /workspace/coverage/default/29.prim_present_test.1181090790 Aug 04 04:19:29 PM PDT 24 Aug 04 04:20:45 PM PDT 24 10672680000 ps
T46 /workspace/coverage/default/34.prim_present_test.678441331 Aug 04 04:20:25 PM PDT 24 Aug 04 04:20:58 PM PDT 24 3974820000 ps
T47 /workspace/coverage/default/31.prim_present_test.58082603 Aug 04 04:20:48 PM PDT 24 Aug 04 04:22:23 PM PDT 24 12265460000 ps
T48 /workspace/coverage/default/27.prim_present_test.953831230 Aug 04 04:19:27 PM PDT 24 Aug 04 04:20:56 PM PDT 24 10960360000 ps
T49 /workspace/coverage/default/15.prim_present_test.3224092310 Aug 04 04:19:25 PM PDT 24 Aug 04 04:20:52 PM PDT 24 12977840000 ps
T50 /workspace/coverage/default/22.prim_present_test.1717794046 Aug 04 04:19:27 PM PDT 24 Aug 04 04:20:24 PM PDT 24 6793960000 ps


Test location /workspace/coverage/default/11.prim_present_test.948735446
Short name T9
Test name
Test status
Simulation time 8236700000 ps
CPU time 29.06 seconds
Started Aug 04 04:19:22 PM PDT 24
Finished Aug 04 04:20:18 PM PDT 24
Peak memory 144612 kb
Host smart-f06a1fbb-fbb0-4409-8169-3c246ee66525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948735446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.948735446
Directory /workspace/11.prim_present_test/latest


Test location /workspace/coverage/default/0.prim_present_test.1614870587
Short name T12
Test name
Test status
Simulation time 7113260000 ps
CPU time 23.49 seconds
Started Aug 04 04:19:17 PM PDT 24
Finished Aug 04 04:20:02 PM PDT 24
Peak memory 144712 kb
Host smart-f74b4661-a0e1-4574-a5c4-bdd7e4feb408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614870587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1614870587
Directory /workspace/0.prim_present_test/latest


Test location /workspace/coverage/default/1.prim_present_test.2204443591
Short name T42
Test name
Test status
Simulation time 4508020000 ps
CPU time 16.92 seconds
Started Aug 04 04:19:29 PM PDT 24
Finished Aug 04 04:20:00 PM PDT 24
Peak memory 143396 kb
Host smart-4e84b6f6-1dc2-43cc-9cc2-5eadab64f1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204443591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2204443591
Directory /workspace/1.prim_present_test/latest


Test location /workspace/coverage/default/10.prim_present_test.1728022211
Short name T43
Test name
Test status
Simulation time 11316240000 ps
CPU time 43.31 seconds
Started Aug 04 04:19:29 PM PDT 24
Finished Aug 04 04:20:51 PM PDT 24
Peak memory 144684 kb
Host smart-614bd9ab-68e2-4aaa-b1d4-3c1a4d0e3af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728022211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1728022211
Directory /workspace/10.prim_present_test/latest


Test location /workspace/coverage/default/12.prim_present_test.2294162143
Short name T10
Test name
Test status
Simulation time 5635180000 ps
CPU time 20.27 seconds
Started Aug 04 04:19:21 PM PDT 24
Finished Aug 04 04:20:01 PM PDT 24
Peak memory 143880 kb
Host smart-8a923456-bb55-4f30-bb2c-398d53cc3242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294162143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2294162143
Directory /workspace/12.prim_present_test/latest


Test location /workspace/coverage/default/13.prim_present_test.4167572174
Short name T15
Test name
Test status
Simulation time 15022600000 ps
CPU time 53.46 seconds
Started Aug 04 04:19:26 PM PDT 24
Finished Aug 04 04:21:08 PM PDT 24
Peak memory 145280 kb
Host smart-fe1ff69f-fb80-44b9-a816-cfdb28fba7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167572174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.4167572174
Directory /workspace/13.prim_present_test/latest


Test location /workspace/coverage/default/14.prim_present_test.3028644881
Short name T23
Test name
Test status
Simulation time 13269860000 ps
CPU time 47.49 seconds
Started Aug 04 04:19:27 PM PDT 24
Finished Aug 04 04:20:57 PM PDT 24
Peak memory 145280 kb
Host smart-35903f49-436b-4961-bb82-fdcacf5a1d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028644881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3028644881
Directory /workspace/14.prim_present_test/latest


Test location /workspace/coverage/default/15.prim_present_test.3224092310
Short name T49
Test name
Test status
Simulation time 12977840000 ps
CPU time 45.12 seconds
Started Aug 04 04:19:25 PM PDT 24
Finished Aug 04 04:20:52 PM PDT 24
Peak memory 145308 kb
Host smart-97ea9ff2-9f49-44d9-893a-a91be34987c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224092310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3224092310
Directory /workspace/15.prim_present_test/latest


Test location /workspace/coverage/default/16.prim_present_test.2487154843
Short name T44
Test name
Test status
Simulation time 13064020000 ps
CPU time 47.23 seconds
Started Aug 04 04:19:26 PM PDT 24
Finished Aug 04 04:20:55 PM PDT 24
Peak memory 145280 kb
Host smart-517fb3cc-3dd5-4ab7-9cbe-ca70f6ea3ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487154843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2487154843
Directory /workspace/16.prim_present_test/latest


Test location /workspace/coverage/default/17.prim_present_test.3346647843
Short name T33
Test name
Test status
Simulation time 12909020000 ps
CPU time 47.55 seconds
Started Aug 04 04:19:26 PM PDT 24
Finished Aug 04 04:20:56 PM PDT 24
Peak memory 145280 kb
Host smart-573649d9-cc80-4cc9-82f9-7dffbbe21fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346647843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3346647843
Directory /workspace/17.prim_present_test/latest


Test location /workspace/coverage/default/18.prim_present_test.3751891422
Short name T21
Test name
Test status
Simulation time 4092620000 ps
CPU time 14.41 seconds
Started Aug 04 04:19:17 PM PDT 24
Finished Aug 04 04:19:45 PM PDT 24
Peak memory 144552 kb
Host smart-ce3d455c-4ecf-4b0e-8653-3ddabb41782c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751891422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3751891422
Directory /workspace/18.prim_present_test/latest


Test location /workspace/coverage/default/19.prim_present_test.3184311610
Short name T28
Test name
Test status
Simulation time 3126040000 ps
CPU time 11.82 seconds
Started Aug 04 04:19:26 PM PDT 24
Finished Aug 04 04:19:48 PM PDT 24
Peak memory 145128 kb
Host smart-0efe8ec8-7d54-469c-8952-40aa71a83e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184311610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3184311610
Directory /workspace/19.prim_present_test/latest


Test location /workspace/coverage/default/2.prim_present_test.1424237070
Short name T16
Test name
Test status
Simulation time 5255740000 ps
CPU time 18.78 seconds
Started Aug 04 04:19:22 PM PDT 24
Finished Aug 04 04:19:59 PM PDT 24
Peak memory 144676 kb
Host smart-e68f4b7f-9376-40b3-818b-b78bf56201c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424237070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1424237070
Directory /workspace/2.prim_present_test/latest


Test location /workspace/coverage/default/20.prim_present_test.3094014142
Short name T7
Test name
Test status
Simulation time 10447000000 ps
CPU time 38.91 seconds
Started Aug 04 04:19:28 PM PDT 24
Finished Aug 04 04:20:42 PM PDT 24
Peak memory 143456 kb
Host smart-f03a9b04-ff5a-4f5f-8e7b-a572a71f2a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094014142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3094014142
Directory /workspace/20.prim_present_test/latest


Test location /workspace/coverage/default/21.prim_present_test.1825209970
Short name T17
Test name
Test status
Simulation time 3632580000 ps
CPU time 15.68 seconds
Started Aug 04 04:19:27 PM PDT 24
Finished Aug 04 04:19:58 PM PDT 24
Peak memory 142380 kb
Host smart-aed83c23-0e2f-47d9-a5e2-b1bfeba9e1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825209970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1825209970
Directory /workspace/21.prim_present_test/latest


Test location /workspace/coverage/default/22.prim_present_test.1717794046
Short name T50
Test name
Test status
Simulation time 6793960000 ps
CPU time 28.64 seconds
Started Aug 04 04:19:27 PM PDT 24
Finished Aug 04 04:20:24 PM PDT 24
Peak memory 142636 kb
Host smart-3762200d-5ea9-438a-8edc-816f59a0a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717794046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1717794046
Directory /workspace/22.prim_present_test/latest


Test location /workspace/coverage/default/23.prim_present_test.810195930
Short name T11
Test name
Test status
Simulation time 3905380000 ps
CPU time 13.26 seconds
Started Aug 04 04:19:25 PM PDT 24
Finished Aug 04 04:19:51 PM PDT 24
Peak memory 145132 kb
Host smart-d9461f1c-ff33-4424-86f1-771de3eead04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810195930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.810195930
Directory /workspace/23.prim_present_test/latest


Test location /workspace/coverage/default/24.prim_present_test.646151871
Short name T22
Test name
Test status
Simulation time 5413220000 ps
CPU time 23.32 seconds
Started Aug 04 04:19:27 PM PDT 24
Finished Aug 04 04:20:13 PM PDT 24
Peak memory 142728 kb
Host smart-c933696c-fcc1-4cf3-9b5c-de13cafca3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646151871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.646151871
Directory /workspace/24.prim_present_test/latest


Test location /workspace/coverage/default/25.prim_present_test.3604926320
Short name T41
Test name
Test status
Simulation time 5292320000 ps
CPU time 23.01 seconds
Started Aug 04 04:19:27 PM PDT 24
Finished Aug 04 04:20:12 PM PDT 24
Peak memory 142504 kb
Host smart-7e757b1d-2b7d-4141-b5df-378dd546fe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604926320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3604926320
Directory /workspace/25.prim_present_test/latest


Test location /workspace/coverage/default/26.prim_present_test.759984793
Short name T26
Test name
Test status
Simulation time 6961980000 ps
CPU time 23.13 seconds
Started Aug 04 04:19:25 PM PDT 24
Finished Aug 04 04:20:09 PM PDT 24
Peak memory 145288 kb
Host smart-0119e046-c220-49c7-b2ad-0c5476cb5e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759984793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.759984793
Directory /workspace/26.prim_present_test/latest


Test location /workspace/coverage/default/27.prim_present_test.953831230
Short name T48
Test name
Test status
Simulation time 10960360000 ps
CPU time 45.53 seconds
Started Aug 04 04:19:27 PM PDT 24
Finished Aug 04 04:20:56 PM PDT 24
Peak memory 142604 kb
Host smart-b0a0ade3-b1b8-464b-97f1-49706b58b609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953831230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.953831230
Directory /workspace/27.prim_present_test/latest


Test location /workspace/coverage/default/28.prim_present_test.1106127212
Short name T19
Test name
Test status
Simulation time 3837180000 ps
CPU time 17.14 seconds
Started Aug 04 04:19:27 PM PDT 24
Finished Aug 04 04:20:01 PM PDT 24
Peak memory 142248 kb
Host smart-1ba55b6c-5eb9-4c8a-a3d1-3ee4a49113dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106127212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1106127212
Directory /workspace/28.prim_present_test/latest


Test location /workspace/coverage/default/29.prim_present_test.1181090790
Short name T45
Test name
Test status
Simulation time 10672680000 ps
CPU time 40.24 seconds
Started Aug 04 04:19:29 PM PDT 24
Finished Aug 04 04:20:45 PM PDT 24
Peak memory 143688 kb
Host smart-55d6776f-d425-47e2-849d-016af0cadda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181090790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1181090790
Directory /workspace/29.prim_present_test/latest


Test location /workspace/coverage/default/3.prim_present_test.4268252465
Short name T3
Test name
Test status
Simulation time 8914360000 ps
CPU time 32.1 seconds
Started Aug 04 04:19:21 PM PDT 24
Finished Aug 04 04:20:23 PM PDT 24
Peak memory 143720 kb
Host smart-6deb2c15-c333-458e-bfe5-9e53f7188fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268252465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.4268252465
Directory /workspace/3.prim_present_test/latest


Test location /workspace/coverage/default/30.prim_present_test.4181372677
Short name T37
Test name
Test status
Simulation time 10181020000 ps
CPU time 38.74 seconds
Started Aug 04 04:20:41 PM PDT 24
Finished Aug 04 04:21:56 PM PDT 24
Peak memory 144728 kb
Host smart-4cbb691f-9369-44ff-aed5-bc73eda33eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181372677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4181372677
Directory /workspace/30.prim_present_test/latest


Test location /workspace/coverage/default/31.prim_present_test.58082603
Short name T47
Test name
Test status
Simulation time 12265460000 ps
CPU time 49.3 seconds
Started Aug 04 04:20:48 PM PDT 24
Finished Aug 04 04:22:23 PM PDT 24
Peak memory 144828 kb
Host smart-acc35495-e8e1-4704-92e9-ce8e30b85218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58082603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.58082603
Directory /workspace/31.prim_present_test/latest


Test location /workspace/coverage/default/32.prim_present_test.1496233319
Short name T38
Test name
Test status
Simulation time 6568280000 ps
CPU time 26.99 seconds
Started Aug 04 04:20:32 PM PDT 24
Finished Aug 04 04:21:23 PM PDT 24
Peak memory 143352 kb
Host smart-9bdac9ef-78b4-49d4-9c08-6fd76f63d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496233319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1496233319
Directory /workspace/32.prim_present_test/latest


Test location /workspace/coverage/default/33.prim_present_test.34254123
Short name T39
Test name
Test status
Simulation time 6576340000 ps
CPU time 21.89 seconds
Started Aug 04 04:19:18 PM PDT 24
Finished Aug 04 04:20:00 PM PDT 24
Peak memory 144704 kb
Host smart-ae27d29b-3ee3-445b-98e8-7bad2a812de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34254123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.34254123
Directory /workspace/33.prim_present_test/latest


Test location /workspace/coverage/default/34.prim_present_test.678441331
Short name T46
Test name
Test status
Simulation time 3974820000 ps
CPU time 17.53 seconds
Started Aug 04 04:20:25 PM PDT 24
Finished Aug 04 04:20:58 PM PDT 24
Peak memory 144768 kb
Host smart-f5876a3a-e372-4d6a-9e98-543f60553a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678441331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.678441331
Directory /workspace/34.prim_present_test/latest


Test location /workspace/coverage/default/35.prim_present_test.2920828778
Short name T24
Test name
Test status
Simulation time 8120140000 ps
CPU time 32.16 seconds
Started Aug 04 04:20:42 PM PDT 24
Finished Aug 04 04:21:43 PM PDT 24
Peak memory 144876 kb
Host smart-4e9f2929-4ad1-45a5-b767-6f8778a41ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920828778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2920828778
Directory /workspace/35.prim_present_test/latest


Test location /workspace/coverage/default/36.prim_present_test.3612652158
Short name T29
Test name
Test status
Simulation time 4916600000 ps
CPU time 20.51 seconds
Started Aug 04 04:19:58 PM PDT 24
Finished Aug 04 04:20:36 PM PDT 24
Peak memory 144916 kb
Host smart-bbba9f98-67f0-4192-94f5-9e27313c7fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612652158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3612652158
Directory /workspace/36.prim_present_test/latest


Test location /workspace/coverage/default/37.prim_present_test.2754255423
Short name T30
Test name
Test status
Simulation time 6072280000 ps
CPU time 22.57 seconds
Started Aug 04 04:20:32 PM PDT 24
Finished Aug 04 04:21:15 PM PDT 24
Peak memory 144516 kb
Host smart-ba72e2ee-03d6-4c74-b133-c3d943cf8dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754255423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2754255423
Directory /workspace/37.prim_present_test/latest


Test location /workspace/coverage/default/38.prim_present_test.147813404
Short name T36
Test name
Test status
Simulation time 10461880000 ps
CPU time 41.28 seconds
Started Aug 04 04:20:42 PM PDT 24
Finished Aug 04 04:22:01 PM PDT 24
Peak memory 144876 kb
Host smart-f90807c7-fcbf-48d8-9263-378107098acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147813404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.147813404
Directory /workspace/38.prim_present_test/latest


Test location /workspace/coverage/default/39.prim_present_test.655476161
Short name T40
Test name
Test status
Simulation time 8539260000 ps
CPU time 27.76 seconds
Started Aug 04 04:19:17 PM PDT 24
Finished Aug 04 04:20:09 PM PDT 24
Peak memory 144704 kb
Host smart-720579b2-ba2f-4b0f-84a4-69977623bd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655476161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.655476161
Directory /workspace/39.prim_present_test/latest


Test location /workspace/coverage/default/4.prim_present_test.2825573099
Short name T27
Test name
Test status
Simulation time 10672680000 ps
CPU time 39.12 seconds
Started Aug 04 04:19:28 PM PDT 24
Finished Aug 04 04:20:42 PM PDT 24
Peak memory 143300 kb
Host smart-c8052872-c715-44a0-af6f-efb7fdcdcd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825573099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2825573099
Directory /workspace/4.prim_present_test/latest


Test location /workspace/coverage/default/40.prim_present_test.489916554
Short name T34
Test name
Test status
Simulation time 13877460000 ps
CPU time 48.17 seconds
Started Aug 04 04:19:32 PM PDT 24
Finished Aug 04 04:21:02 PM PDT 24
Peak memory 144772 kb
Host smart-f0737026-a3f6-497f-a8ac-c9ee296de257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489916554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.489916554
Directory /workspace/40.prim_present_test/latest


Test location /workspace/coverage/default/41.prim_present_test.2616641956
Short name T18
Test name
Test status
Simulation time 8932340000 ps
CPU time 29.82 seconds
Started Aug 04 04:19:32 PM PDT 24
Finished Aug 04 04:20:28 PM PDT 24
Peak memory 144776 kb
Host smart-e1e230f8-2af9-4e28-91bf-50ea940cd0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616641956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2616641956
Directory /workspace/41.prim_present_test/latest


Test location /workspace/coverage/default/42.prim_present_test.2831229227
Short name T5
Test name
Test status
Simulation time 4336280000 ps
CPU time 15.31 seconds
Started Aug 04 04:19:31 PM PDT 24
Finished Aug 04 04:20:00 PM PDT 24
Peak memory 143700 kb
Host smart-a6ffc6eb-b29c-4ea6-a6f9-dab4717e89ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831229227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2831229227
Directory /workspace/42.prim_present_test/latest


Test location /workspace/coverage/default/43.prim_present_test.2964538814
Short name T32
Test name
Test status
Simulation time 13568700000 ps
CPU time 50.44 seconds
Started Aug 04 04:19:31 PM PDT 24
Finished Aug 04 04:21:06 PM PDT 24
Peak memory 143128 kb
Host smart-ef249a2f-3270-4610-9f3a-67541fb998e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964538814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2964538814
Directory /workspace/43.prim_present_test/latest


Test location /workspace/coverage/default/44.prim_present_test.2294428232
Short name T14
Test name
Test status
Simulation time 7426980000 ps
CPU time 26.32 seconds
Started Aug 04 04:20:03 PM PDT 24
Finished Aug 04 04:20:51 PM PDT 24
Peak memory 144876 kb
Host smart-8ec25673-3e44-4a8c-9fd5-44502986430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294428232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2294428232
Directory /workspace/44.prim_present_test/latest


Test location /workspace/coverage/default/45.prim_present_test.4022031368
Short name T13
Test name
Test status
Simulation time 14433600000 ps
CPU time 53.31 seconds
Started Aug 04 04:19:31 PM PDT 24
Finished Aug 04 04:21:12 PM PDT 24
Peak memory 143100 kb
Host smart-587bf478-328a-4045-9f95-4059a0c861a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022031368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4022031368
Directory /workspace/45.prim_present_test/latest


Test location /workspace/coverage/default/46.prim_present_test.3754805226
Short name T35
Test name
Test status
Simulation time 10487920000 ps
CPU time 41.52 seconds
Started Aug 04 04:20:32 PM PDT 24
Finished Aug 04 04:21:51 PM PDT 24
Peak memory 143228 kb
Host smart-0fae1807-fcb1-4e2e-ae39-7414bfe91bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754805226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3754805226
Directory /workspace/46.prim_present_test/latest


Test location /workspace/coverage/default/47.prim_present_test.667645259
Short name T4
Test name
Test status
Simulation time 8301180000 ps
CPU time 33.94 seconds
Started Aug 04 04:20:42 PM PDT 24
Finished Aug 04 04:21:47 PM PDT 24
Peak memory 144876 kb
Host smart-5a2ab21d-2b3b-47be-98d0-061993fb2713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667645259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.667645259
Directory /workspace/47.prim_present_test/latest


Test location /workspace/coverage/default/48.prim_present_test.91737495
Short name T31
Test name
Test status
Simulation time 10758240000 ps
CPU time 40.66 seconds
Started Aug 04 04:19:32 PM PDT 24
Finished Aug 04 04:20:49 PM PDT 24
Peak memory 144728 kb
Host smart-c620a6b8-ec85-433a-976f-175a5a485e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91737495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.91737495
Directory /workspace/48.prim_present_test/latest


Test location /workspace/coverage/default/49.prim_present_test.4200801553
Short name T6
Test name
Test status
Simulation time 5994780000 ps
CPU time 22.35 seconds
Started Aug 04 04:19:32 PM PDT 24
Finished Aug 04 04:20:14 PM PDT 24
Peak memory 144684 kb
Host smart-451ae549-8c6e-4570-be42-5fe108b5687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200801553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4200801553
Directory /workspace/49.prim_present_test/latest


Test location /workspace/coverage/default/5.prim_present_test.1288322437
Short name T1
Test name
Test status
Simulation time 12158200000 ps
CPU time 44.69 seconds
Started Aug 04 04:19:29 PM PDT 24
Finished Aug 04 04:20:53 PM PDT 24
Peak memory 144684 kb
Host smart-3bc2c271-2b9e-4621-bbc7-62351af6649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288322437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1288322437
Directory /workspace/5.prim_present_test/latest


Test location /workspace/coverage/default/6.prim_present_test.2544108945
Short name T25
Test name
Test status
Simulation time 15028800000 ps
CPU time 54.5 seconds
Started Aug 04 04:19:29 PM PDT 24
Finished Aug 04 04:21:10 PM PDT 24
Peak memory 143264 kb
Host smart-d30991ab-f4be-4256-8b2c-3f3e27eecc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544108945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2544108945
Directory /workspace/6.prim_present_test/latest


Test location /workspace/coverage/default/7.prim_present_test.3833720738
Short name T20
Test name
Test status
Simulation time 14418100000 ps
CPU time 60.29 seconds
Started Aug 04 04:19:27 PM PDT 24
Finished Aug 04 04:21:23 PM PDT 24
Peak memory 142456 kb
Host smart-911e2454-db98-4c04-a345-fe5129be9b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833720738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3833720738
Directory /workspace/7.prim_present_test/latest


Test location /workspace/coverage/default/8.prim_present_test.2146411448
Short name T2
Test name
Test status
Simulation time 8441300000 ps
CPU time 30.17 seconds
Started Aug 04 04:19:27 PM PDT 24
Finished Aug 04 04:20:24 PM PDT 24
Peak memory 145280 kb
Host smart-356385b7-90bd-48b8-b5e7-0e6b9279edd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146411448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2146411448
Directory /workspace/8.prim_present_test/latest


Test location /workspace/coverage/default/9.prim_present_test.3796243600
Short name T8
Test name
Test status
Simulation time 12297080000 ps
CPU time 45.67 seconds
Started Aug 04 04:19:22 PM PDT 24
Finished Aug 04 04:20:49 PM PDT 24
Peak memory 144692 kb
Host smart-1682fd53-831e-4f0a-8559-e2b4d537f03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796243600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3796243600
Directory /workspace/9.prim_present_test/latest
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