| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/18.prim_present_test.2608374305 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3648893550 |
| /workspace/coverage/default/1.prim_present_test.1972828747 |
| /workspace/coverage/default/10.prim_present_test.2581716618 |
| /workspace/coverage/default/11.prim_present_test.2847049303 |
| /workspace/coverage/default/12.prim_present_test.4244640301 |
| /workspace/coverage/default/13.prim_present_test.3916712661 |
| /workspace/coverage/default/14.prim_present_test.476167033 |
| /workspace/coverage/default/15.prim_present_test.1352239452 |
| /workspace/coverage/default/16.prim_present_test.1395402206 |
| /workspace/coverage/default/17.prim_present_test.3097418872 |
| /workspace/coverage/default/19.prim_present_test.3803160437 |
| /workspace/coverage/default/2.prim_present_test.3114415981 |
| /workspace/coverage/default/20.prim_present_test.1060869264 |
| /workspace/coverage/default/21.prim_present_test.915972601 |
| /workspace/coverage/default/22.prim_present_test.1266540262 |
| /workspace/coverage/default/23.prim_present_test.1515719157 |
| /workspace/coverage/default/24.prim_present_test.2072206998 |
| /workspace/coverage/default/25.prim_present_test.207315061 |
| /workspace/coverage/default/26.prim_present_test.1068992251 |
| /workspace/coverage/default/27.prim_present_test.3043157823 |
| /workspace/coverage/default/28.prim_present_test.173968082 |
| /workspace/coverage/default/29.prim_present_test.768528741 |
| /workspace/coverage/default/3.prim_present_test.3853410865 |
| /workspace/coverage/default/30.prim_present_test.3926072624 |
| /workspace/coverage/default/31.prim_present_test.3032973791 |
| /workspace/coverage/default/32.prim_present_test.2957648955 |
| /workspace/coverage/default/33.prim_present_test.2607911383 |
| /workspace/coverage/default/34.prim_present_test.1192709133 |
| /workspace/coverage/default/35.prim_present_test.2871412815 |
| /workspace/coverage/default/36.prim_present_test.3471430007 |
| /workspace/coverage/default/37.prim_present_test.1039780421 |
| /workspace/coverage/default/38.prim_present_test.2713143843 |
| /workspace/coverage/default/39.prim_present_test.3325752337 |
| /workspace/coverage/default/4.prim_present_test.1569469139 |
| /workspace/coverage/default/40.prim_present_test.1776114434 |
| /workspace/coverage/default/41.prim_present_test.789111087 |
| /workspace/coverage/default/42.prim_present_test.769581799 |
| /workspace/coverage/default/43.prim_present_test.681875296 |
| /workspace/coverage/default/44.prim_present_test.358964912 |
| /workspace/coverage/default/45.prim_present_test.2538646669 |
| /workspace/coverage/default/46.prim_present_test.3820896932 |
| /workspace/coverage/default/47.prim_present_test.3123333532 |
| /workspace/coverage/default/48.prim_present_test.2143574304 |
| /workspace/coverage/default/49.prim_present_test.2865339149 |
| /workspace/coverage/default/5.prim_present_test.3163482496 |
| /workspace/coverage/default/6.prim_present_test.1150018523 |
| /workspace/coverage/default/7.prim_present_test.484690607 |
| /workspace/coverage/default/8.prim_present_test.3929914349 |
| /workspace/coverage/default/9.prim_present_test.3046567248 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/3.prim_present_test.3853410865 | Aug 05 04:17:25 PM PDT 24 | Aug 05 04:18:44 PM PDT 24 | 12170600000 ps | ||
| T2 | /workspace/coverage/default/35.prim_present_test.2871412815 | Aug 05 04:17:27 PM PDT 24 | Aug 05 04:18:59 PM PDT 24 | 13369680000 ps | ||
| T3 | /workspace/coverage/default/18.prim_present_test.2608374305 | Aug 05 04:22:13 PM PDT 24 | Aug 05 04:22:40 PM PDT 24 | 3341180000 ps | ||
| T4 | /workspace/coverage/default/22.prim_present_test.1266540262 | Aug 05 04:22:00 PM PDT 24 | Aug 05 04:23:26 PM PDT 24 | 13371540000 ps | ||
| T5 | /workspace/coverage/default/36.prim_present_test.3471430007 | Aug 05 04:22:55 PM PDT 24 | Aug 05 04:24:36 PM PDT 24 | 14241400000 ps | ||
| T6 | /workspace/coverage/default/28.prim_present_test.173968082 | Aug 05 04:21:41 PM PDT 24 | Aug 05 04:23:16 PM PDT 24 | 13855760000 ps | ||
| T7 | /workspace/coverage/default/31.prim_present_test.3032973791 | Aug 05 04:22:12 PM PDT 24 | Aug 05 04:23:31 PM PDT 24 | 11416680000 ps | ||
| T8 | /workspace/coverage/default/41.prim_present_test.789111087 | Aug 05 04:18:56 PM PDT 24 | Aug 05 04:20:00 PM PDT 24 | 9402920000 ps | ||
| T9 | /workspace/coverage/default/9.prim_present_test.3046567248 | Aug 05 04:16:55 PM PDT 24 | Aug 05 04:17:50 PM PDT 24 | 8078600000 ps | ||
| T10 | /workspace/coverage/default/34.prim_present_test.1192709133 | Aug 05 04:17:28 PM PDT 24 | Aug 05 04:18:44 PM PDT 24 | 10926880000 ps | ||
| T11 | /workspace/coverage/default/7.prim_present_test.484690607 | Aug 05 04:16:54 PM PDT 24 | Aug 05 04:18:11 PM PDT 24 | 12284060000 ps | ||
| T12 | /workspace/coverage/default/39.prim_present_test.3325752337 | Aug 05 04:18:28 PM PDT 24 | Aug 05 04:19:20 PM PDT 24 | 7260820000 ps | ||
| T13 | /workspace/coverage/default/19.prim_present_test.3803160437 | Aug 05 04:18:28 PM PDT 24 | Aug 05 04:19:40 PM PDT 24 | 10132040000 ps | ||
| T14 | /workspace/coverage/default/30.prim_present_test.3926072624 | Aug 05 04:18:31 PM PDT 24 | Aug 05 04:20:12 PM PDT 24 | 13768960000 ps | ||
| T15 | /workspace/coverage/default/29.prim_present_test.768528741 | Aug 05 04:19:08 PM PDT 24 | Aug 05 04:20:28 PM PDT 24 | 11026080000 ps | ||
| T16 | /workspace/coverage/default/8.prim_present_test.3929914349 | Aug 05 04:16:56 PM PDT 24 | Aug 05 04:18:23 PM PDT 24 | 12861900000 ps | ||
| T17 | /workspace/coverage/default/10.prim_present_test.2581716618 | Aug 05 04:16:56 PM PDT 24 | Aug 05 04:17:48 PM PDT 24 | 7192620000 ps | ||
| T18 | /workspace/coverage/default/2.prim_present_test.3114415981 | Aug 05 04:16:54 PM PDT 24 | Aug 05 04:18:27 PM PDT 24 | 14601620000 ps | ||
| T19 | /workspace/coverage/default/6.prim_present_test.1150018523 | Aug 05 04:18:24 PM PDT 24 | Aug 05 04:18:58 PM PDT 24 | 5005880000 ps | ||
| T20 | /workspace/coverage/default/45.prim_present_test.2538646669 | Aug 05 04:22:40 PM PDT 24 | Aug 05 04:23:09 PM PDT 24 | 4043640000 ps | ||
| T21 | /workspace/coverage/default/33.prim_present_test.2607911383 | Aug 05 04:22:00 PM PDT 24 | Aug 05 04:23:01 PM PDT 24 | 9210100000 ps | ||
| T22 | /workspace/coverage/default/37.prim_present_test.1039780421 | Aug 05 04:20:19 PM PDT 24 | Aug 05 04:21:11 PM PDT 24 | 7353200000 ps | ||
| T23 | /workspace/coverage/default/25.prim_present_test.207315061 | Aug 05 04:22:14 PM PDT 24 | Aug 05 04:23:47 PM PDT 24 | 14165760000 ps | ||
| T24 | /workspace/coverage/default/48.prim_present_test.2143574304 | Aug 05 04:21:32 PM PDT 24 | Aug 05 04:21:59 PM PDT 24 | 4952560000 ps | ||
| T25 | /workspace/coverage/default/13.prim_present_test.3916712661 | Aug 05 04:18:09 PM PDT 24 | Aug 05 04:19:23 PM PDT 24 | 11419160000 ps | ||
| T26 | /workspace/coverage/default/40.prim_present_test.1776114434 | Aug 05 04:17:34 PM PDT 24 | Aug 05 04:18:16 PM PDT 24 | 5749880000 ps | ||
| T27 | /workspace/coverage/default/46.prim_present_test.3820896932 | Aug 05 04:20:25 PM PDT 24 | Aug 05 04:22:08 PM PDT 24 | 13582960000 ps | ||
| T28 | /workspace/coverage/default/42.prim_present_test.769581799 | Aug 05 04:20:26 PM PDT 24 | Aug 05 04:20:59 PM PDT 24 | 4043640000 ps | ||
| T29 | /workspace/coverage/default/15.prim_present_test.1352239452 | Aug 05 04:21:56 PM PDT 24 | Aug 05 04:22:15 PM PDT 24 | 3713180000 ps | ||
| T30 | /workspace/coverage/default/24.prim_present_test.2072206998 | Aug 05 04:18:14 PM PDT 24 | Aug 05 04:18:58 PM PDT 24 | 6346320000 ps | ||
| T31 | /workspace/coverage/default/49.prim_present_test.2865339149 | Aug 05 04:17:19 PM PDT 24 | Aug 05 04:17:49 PM PDT 24 | 4361700000 ps | ||
| T32 | /workspace/coverage/default/16.prim_present_test.1395402206 | Aug 05 04:18:16 PM PDT 24 | Aug 05 04:19:44 PM PDT 24 | 12513460000 ps | ||
| T33 | /workspace/coverage/default/32.prim_present_test.2957648955 | Aug 05 04:22:53 PM PDT 24 | Aug 05 04:24:19 PM PDT 24 | 11256720000 ps | ||
| T34 | /workspace/coverage/default/44.prim_present_test.358964912 | Aug 05 04:21:41 PM PDT 24 | Aug 05 04:22:11 PM PDT 24 | 4406340000 ps | ||
| T35 | /workspace/coverage/default/47.prim_present_test.3123333532 | Aug 05 04:21:33 PM PDT 24 | Aug 05 04:22:24 PM PDT 24 | 8889560000 ps | ||
| T36 | /workspace/coverage/default/17.prim_present_test.3097418872 | Aug 05 04:18:21 PM PDT 24 | Aug 05 04:20:06 PM PDT 24 | 13705100000 ps | ||
| T37 | /workspace/coverage/default/26.prim_present_test.1068992251 | Aug 05 04:18:32 PM PDT 24 | Aug 05 04:19:52 PM PDT 24 | 10287040000 ps | ||
| T38 | /workspace/coverage/default/38.prim_present_test.2713143843 | Aug 05 04:17:45 PM PDT 24 | Aug 05 04:19:00 PM PDT 24 | 11955460000 ps | ||
| T39 | /workspace/coverage/default/20.prim_present_test.1060869264 | Aug 05 04:18:32 PM PDT 24 | Aug 05 04:19:00 PM PDT 24 | 3582360000 ps | ||
| T40 | /workspace/coverage/default/14.prim_present_test.476167033 | Aug 05 04:21:57 PM PDT 24 | Aug 05 04:22:33 PM PDT 24 | 5255120000 ps | ||
| T41 | /workspace/coverage/default/21.prim_present_test.915972601 | Aug 05 04:22:13 PM PDT 24 | Aug 05 04:23:13 PM PDT 24 | 8076740000 ps | ||
| T42 | /workspace/coverage/default/23.prim_present_test.1515719157 | Aug 05 04:21:42 PM PDT 24 | Aug 05 04:22:16 PM PDT 24 | 5715160000 ps | ||
| T43 | /workspace/coverage/default/0.prim_present_test.3648893550 | Aug 05 04:16:54 PM PDT 24 | Aug 05 04:18:10 PM PDT 24 | 11680800000 ps | ||
| T44 | /workspace/coverage/default/1.prim_present_test.1972828747 | Aug 05 04:16:55 PM PDT 24 | Aug 05 04:17:33 PM PDT 24 | 6120020000 ps | ||
| T45 | /workspace/coverage/default/12.prim_present_test.4244640301 | Aug 05 04:16:56 PM PDT 24 | Aug 05 04:17:23 PM PDT 24 | 3802460000 ps | ||
| T46 | /workspace/coverage/default/43.prim_present_test.681875296 | Aug 05 04:22:54 PM PDT 24 | Aug 05 04:24:26 PM PDT 24 | 12567400000 ps | ||
| T47 | /workspace/coverage/default/5.prim_present_test.3163482496 | Aug 05 04:16:55 PM PDT 24 | Aug 05 04:18:17 PM PDT 24 | 12210280000 ps | ||
| T48 | /workspace/coverage/default/11.prim_present_test.2847049303 | Aug 05 04:16:55 PM PDT 24 | Aug 05 04:18:06 PM PDT 24 | 10500320000 ps | ||
| T49 | /workspace/coverage/default/4.prim_present_test.1569469139 | Aug 05 04:16:55 PM PDT 24 | Aug 05 04:17:26 PM PDT 24 | 4259400000 ps | ||
| T50 | /workspace/coverage/default/27.prim_present_test.3043157823 | Aug 05 04:22:40 PM PDT 24 | Aug 05 04:23:35 PM PDT 24 | 7604300000 ps |
| Test location | /workspace/coverage/default/18.prim_present_test.2608374305 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3341180000 ps |
| CPU time | 13.6 seconds |
| Started | Aug 05 04:22:13 PM PDT 24 |
| Finished | Aug 05 04:22:40 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-6a972692-1b37-4589-8c82-44d91aacb772 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608374305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2608374305 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3648893550 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11680800000 ps |
| CPU time | 40.99 seconds |
| Started | Aug 05 04:16:54 PM PDT 24 |
| Finished | Aug 05 04:18:10 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-2ec1c156-f7f0-46a0-abc4-3974b861ddff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648893550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3648893550 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1972828747 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6120020000 ps |
| CPU time | 21.13 seconds |
| Started | Aug 05 04:16:55 PM PDT 24 |
| Finished | Aug 05 04:17:33 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-112a4ed4-22ba-4b76-9eb2-e7c6e3bf0dde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972828747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1972828747 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2581716618 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7192620000 ps |
| CPU time | 27.57 seconds |
| Started | Aug 05 04:16:56 PM PDT 24 |
| Finished | Aug 05 04:17:48 PM PDT 24 |
| Peak memory | 144792 kb |
| Host | smart-65c34be8-9434-4566-a255-7443052c3dc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581716618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2581716618 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2847049303 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10500320000 ps |
| CPU time | 37.79 seconds |
| Started | Aug 05 04:16:55 PM PDT 24 |
| Finished | Aug 05 04:18:06 PM PDT 24 |
| Peak memory | 144624 kb |
| Host | smart-a3eb3a26-ade2-49bb-a904-7a29f3aeab91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847049303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2847049303 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4244640301 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3802460000 ps |
| CPU time | 14.22 seconds |
| Started | Aug 05 04:16:56 PM PDT 24 |
| Finished | Aug 05 04:17:23 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-5bd2478e-84c0-4912-a4b5-b2ab3760079f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4244640301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4244640301 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3916712661 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11419160000 ps |
| CPU time | 39.56 seconds |
| Started | Aug 05 04:18:09 PM PDT 24 |
| Finished | Aug 05 04:19:23 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-5f588b5b-778d-4e2a-b511-942351f75dd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916712661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3916712661 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.476167033 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5255120000 ps |
| CPU time | 19.19 seconds |
| Started | Aug 05 04:21:57 PM PDT 24 |
| Finished | Aug 05 04:22:33 PM PDT 24 |
| Peak memory | 144740 kb |
| Host | smart-d1072d9a-9c2c-411f-b155-820b74e9eaf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=476167033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.476167033 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1352239452 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3713180000 ps |
| CPU time | 10.57 seconds |
| Started | Aug 05 04:21:56 PM PDT 24 |
| Finished | Aug 05 04:22:15 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-1b8ab032-fb05-4da7-90c5-dffecdd61af0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352239452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1352239452 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1395402206 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12513460000 ps |
| CPU time | 46.9 seconds |
| Started | Aug 05 04:18:16 PM PDT 24 |
| Finished | Aug 05 04:19:44 PM PDT 24 |
| Peak memory | 144840 kb |
| Host | smart-b7a9c4f3-0cf6-453b-a8ea-02f32a9568b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395402206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1395402206 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3097418872 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13705100000 ps |
| CPU time | 54.63 seconds |
| Started | Aug 05 04:18:21 PM PDT 24 |
| Finished | Aug 05 04:20:06 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-3ed885d6-e481-464f-9e5b-a3e83b408771 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097418872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3097418872 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3803160437 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10132040000 ps |
| CPU time | 37.62 seconds |
| Started | Aug 05 04:18:28 PM PDT 24 |
| Finished | Aug 05 04:19:40 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-c679f965-6677-49df-96a9-0a60e8307d99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803160437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3803160437 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3114415981 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14601620000 ps |
| CPU time | 50.67 seconds |
| Started | Aug 05 04:16:54 PM PDT 24 |
| Finished | Aug 05 04:18:27 PM PDT 24 |
| Peak memory | 144036 kb |
| Host | smart-99386461-f894-42a5-92dc-62bc8cdacc8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114415981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3114415981 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1060869264 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3582360000 ps |
| CPU time | 15.07 seconds |
| Started | Aug 05 04:18:32 PM PDT 24 |
| Finished | Aug 05 04:19:00 PM PDT 24 |
| Peak memory | 144484 kb |
| Host | smart-55eaa365-14ce-48a3-a7e8-963c50e3194c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060869264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1060869264 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.915972601 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8076740000 ps |
| CPU time | 31.41 seconds |
| Started | Aug 05 04:22:13 PM PDT 24 |
| Finished | Aug 05 04:23:13 PM PDT 24 |
| Peak memory | 144676 kb |
| Host | smart-beebbc37-ba85-48d5-9d96-5af6087ff24f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915972601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.915972601 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1266540262 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13371540000 ps |
| CPU time | 46 seconds |
| Started | Aug 05 04:22:00 PM PDT 24 |
| Finished | Aug 05 04:23:26 PM PDT 24 |
| Peak memory | 143360 kb |
| Host | smart-0a5af9ad-8447-4382-a1dd-aedc22250a8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266540262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1266540262 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1515719157 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5715160000 ps |
| CPU time | 18.44 seconds |
| Started | Aug 05 04:21:42 PM PDT 24 |
| Finished | Aug 05 04:22:16 PM PDT 24 |
| Peak memory | 144452 kb |
| Host | smart-06873363-c9e2-4426-b4c3-4e911daae5ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515719157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1515719157 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2072206998 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6346320000 ps |
| CPU time | 24.01 seconds |
| Started | Aug 05 04:18:14 PM PDT 24 |
| Finished | Aug 05 04:18:58 PM PDT 24 |
| Peak memory | 144620 kb |
| Host | smart-0151e604-b250-4a55-baac-5761d9aa1bf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072206998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2072206998 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.207315061 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14165760000 ps |
| CPU time | 49.32 seconds |
| Started | Aug 05 04:22:14 PM PDT 24 |
| Finished | Aug 05 04:23:47 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-329f0e7c-36fe-4c58-8c91-1b421191172a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=207315061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.207315061 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1068992251 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10287040000 ps |
| CPU time | 42.03 seconds |
| Started | Aug 05 04:18:32 PM PDT 24 |
| Finished | Aug 05 04:19:52 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-1076dc00-3436-49a0-8231-b2b4725e375b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068992251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1068992251 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3043157823 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7604300000 ps |
| CPU time | 28.16 seconds |
| Started | Aug 05 04:22:40 PM PDT 24 |
| Finished | Aug 05 04:23:35 PM PDT 24 |
| Peak memory | 143680 kb |
| Host | smart-dd75070a-aa96-4cf5-b635-ae8a0cc84a71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3043157823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3043157823 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.173968082 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13855760000 ps |
| CPU time | 50.34 seconds |
| Started | Aug 05 04:21:41 PM PDT 24 |
| Finished | Aug 05 04:23:16 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-216faa8b-4a33-41e3-8b6f-abf21b18e5cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173968082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.173968082 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.768528741 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11026080000 ps |
| CPU time | 41.88 seconds |
| Started | Aug 05 04:19:08 PM PDT 24 |
| Finished | Aug 05 04:20:28 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-2ef64608-4668-4314-b214-9bb18b3adf0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768528741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.768528741 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3853410865 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12170600000 ps |
| CPU time | 42.49 seconds |
| Started | Aug 05 04:17:25 PM PDT 24 |
| Finished | Aug 05 04:18:44 PM PDT 24 |
| Peak memory | 143976 kb |
| Host | smart-a7fb237d-2e72-40f1-abcb-c36513c7c86d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3853410865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3853410865 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3926072624 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13768960000 ps |
| CPU time | 52.93 seconds |
| Started | Aug 05 04:18:31 PM PDT 24 |
| Finished | Aug 05 04:20:12 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-c6c3cbbb-84f0-42e1-b8bb-1b4f284b7157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926072624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3926072624 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3032973791 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11416680000 ps |
| CPU time | 41.42 seconds |
| Started | Aug 05 04:22:12 PM PDT 24 |
| Finished | Aug 05 04:23:31 PM PDT 24 |
| Peak memory | 144616 kb |
| Host | smart-b8bdcd03-486d-42d3-833c-74061ec354c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032973791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3032973791 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2957648955 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11256720000 ps |
| CPU time | 41.7 seconds |
| Started | Aug 05 04:22:53 PM PDT 24 |
| Finished | Aug 05 04:24:19 PM PDT 24 |
| Peak memory | 144780 kb |
| Host | smart-bbee6458-f2e1-4c1a-b06e-ef0e528557a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2957648955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2957648955 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2607911383 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9210100000 ps |
| CPU time | 32.91 seconds |
| Started | Aug 05 04:22:00 PM PDT 24 |
| Finished | Aug 05 04:23:01 PM PDT 24 |
| Peak memory | 143340 kb |
| Host | smart-b8faf04b-8390-4170-b1c8-c35161df66dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607911383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2607911383 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1192709133 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10926880000 ps |
| CPU time | 40.34 seconds |
| Started | Aug 05 04:17:28 PM PDT 24 |
| Finished | Aug 05 04:18:44 PM PDT 24 |
| Peak memory | 145268 kb |
| Host | smart-6d2ab7bf-779e-4420-9af5-fafff9c17907 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192709133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1192709133 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2871412815 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13369680000 ps |
| CPU time | 48.52 seconds |
| Started | Aug 05 04:17:27 PM PDT 24 |
| Finished | Aug 05 04:18:59 PM PDT 24 |
| Peak memory | 145268 kb |
| Host | smart-40462e3a-2fcd-4d5d-b141-0ffb5cc7e013 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871412815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2871412815 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3471430007 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14241400000 ps |
| CPU time | 51.86 seconds |
| Started | Aug 05 04:22:55 PM PDT 24 |
| Finished | Aug 05 04:24:36 PM PDT 24 |
| Peak memory | 144784 kb |
| Host | smart-6ed9e2ba-9221-4242-8c80-f8c7e892eae2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3471430007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3471430007 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1039780421 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7353200000 ps |
| CPU time | 27.49 seconds |
| Started | Aug 05 04:20:19 PM PDT 24 |
| Finished | Aug 05 04:21:11 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-273bac3b-54a3-4d6b-b032-b680ca04413a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039780421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1039780421 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2713143843 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11955460000 ps |
| CPU time | 40.82 seconds |
| Started | Aug 05 04:17:45 PM PDT 24 |
| Finished | Aug 05 04:19:00 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-27f6d9d4-8090-40a5-9fcd-d19607a1466e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713143843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2713143843 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3325752337 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7260820000 ps |
| CPU time | 27.92 seconds |
| Started | Aug 05 04:18:28 PM PDT 24 |
| Finished | Aug 05 04:19:20 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-621eee52-923d-49ce-a688-45e4e5f31b0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325752337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3325752337 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1569469139 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4259400000 ps |
| CPU time | 16.64 seconds |
| Started | Aug 05 04:16:55 PM PDT 24 |
| Finished | Aug 05 04:17:26 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-ef81bb3d-b775-4d6e-8485-2a1019d98223 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1569469139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1569469139 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1776114434 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5749880000 ps |
| CPU time | 22.56 seconds |
| Started | Aug 05 04:17:34 PM PDT 24 |
| Finished | Aug 05 04:18:16 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-2066097b-8ba3-49db-8be6-db727106ffbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1776114434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1776114434 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.789111087 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9402920000 ps |
| CPU time | 34.19 seconds |
| Started | Aug 05 04:18:56 PM PDT 24 |
| Finished | Aug 05 04:20:00 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-1e1ed126-5cf6-48dd-a3d9-e3a3c51aaed1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789111087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.789111087 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.769581799 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4043640000 ps |
| CPU time | 17.27 seconds |
| Started | Aug 05 04:20:26 PM PDT 24 |
| Finished | Aug 05 04:20:59 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-d2531780-6901-4879-8526-71ac41384be8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=769581799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.769581799 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.681875296 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12567400000 ps |
| CPU time | 48.22 seconds |
| Started | Aug 05 04:22:54 PM PDT 24 |
| Finished | Aug 05 04:24:26 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-0cae1e32-5811-44e5-8f1b-fe0979e8620a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681875296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.681875296 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.358964912 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4406340000 ps |
| CPU time | 16.22 seconds |
| Started | Aug 05 04:21:41 PM PDT 24 |
| Finished | Aug 05 04:22:11 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-e39c17ff-9ec1-48b2-a23d-1a5064593404 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358964912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.358964912 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2538646669 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4043640000 ps |
| CPU time | 14.95 seconds |
| Started | Aug 05 04:22:40 PM PDT 24 |
| Finished | Aug 05 04:23:09 PM PDT 24 |
| Peak memory | 144092 kb |
| Host | smart-7e6e79ae-6823-4858-8098-069e852dc69d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538646669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2538646669 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3820896932 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13582960000 ps |
| CPU time | 54.32 seconds |
| Started | Aug 05 04:20:25 PM PDT 24 |
| Finished | Aug 05 04:22:08 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-4cea0f45-00a4-4f8b-acb2-f5751c7171fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3820896932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3820896932 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3123333532 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8889560000 ps |
| CPU time | 27.87 seconds |
| Started | Aug 05 04:21:33 PM PDT 24 |
| Finished | Aug 05 04:22:24 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-92676824-8d6c-4812-b2e1-e4ba403e9f7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123333532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3123333532 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2143574304 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4952560000 ps |
| CPU time | 15.07 seconds |
| Started | Aug 05 04:21:32 PM PDT 24 |
| Finished | Aug 05 04:21:59 PM PDT 24 |
| Peak memory | 144032 kb |
| Host | smart-1d24d361-3d14-4c42-910b-75fd1dfc9136 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2143574304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2143574304 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2865339149 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4361700000 ps |
| CPU time | 15.4 seconds |
| Started | Aug 05 04:17:19 PM PDT 24 |
| Finished | Aug 05 04:17:49 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-9ade66c2-90ea-4141-966f-a1fa2709e564 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865339149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2865339149 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3163482496 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12210280000 ps |
| CPU time | 43.99 seconds |
| Started | Aug 05 04:16:55 PM PDT 24 |
| Finished | Aug 05 04:18:17 PM PDT 24 |
| Peak memory | 144624 kb |
| Host | smart-747add27-6c1a-4360-b7a2-bbd338bef72b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163482496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3163482496 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1150018523 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5005880000 ps |
| CPU time | 18.69 seconds |
| Started | Aug 05 04:18:24 PM PDT 24 |
| Finished | Aug 05 04:18:58 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-0f3bbb73-a2ce-4216-9af9-d2f99821296b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150018523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1150018523 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.484690607 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12284060000 ps |
| CPU time | 42.08 seconds |
| Started | Aug 05 04:16:54 PM PDT 24 |
| Finished | Aug 05 04:18:11 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-fa997487-3ae7-4b18-b694-f3b977175ab0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484690607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.484690607 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3929914349 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12861900000 ps |
| CPU time | 46.06 seconds |
| Started | Aug 05 04:16:56 PM PDT 24 |
| Finished | Aug 05 04:18:23 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-27304122-6531-409e-804e-0b1626ed1fea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929914349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3929914349 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3046567248 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8078600000 ps |
| CPU time | 29.07 seconds |
| Started | Aug 05 04:16:55 PM PDT 24 |
| Finished | Aug 05 04:17:50 PM PDT 24 |
| Peak memory | 143972 kb |
| Host | smart-dbf9f122-6ccf-4e6d-9d13-b66505eb813f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046567248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3046567248 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |