| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.238402813 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.308689447 |
| /workspace/coverage/default/10.prim_present_test.934862946 |
| /workspace/coverage/default/11.prim_present_test.1621289755 |
| /workspace/coverage/default/12.prim_present_test.4207143368 |
| /workspace/coverage/default/13.prim_present_test.4115034856 |
| /workspace/coverage/default/14.prim_present_test.4278546542 |
| /workspace/coverage/default/15.prim_present_test.205471943 |
| /workspace/coverage/default/16.prim_present_test.1422630665 |
| /workspace/coverage/default/17.prim_present_test.4050326030 |
| /workspace/coverage/default/18.prim_present_test.2185501627 |
| /workspace/coverage/default/19.prim_present_test.2678649671 |
| /workspace/coverage/default/2.prim_present_test.1620414933 |
| /workspace/coverage/default/20.prim_present_test.3321716560 |
| /workspace/coverage/default/21.prim_present_test.62816817 |
| /workspace/coverage/default/22.prim_present_test.3503701996 |
| /workspace/coverage/default/23.prim_present_test.1786616929 |
| /workspace/coverage/default/24.prim_present_test.2946788863 |
| /workspace/coverage/default/25.prim_present_test.3352958393 |
| /workspace/coverage/default/26.prim_present_test.1510660869 |
| /workspace/coverage/default/27.prim_present_test.42773186 |
| /workspace/coverage/default/28.prim_present_test.3639841843 |
| /workspace/coverage/default/29.prim_present_test.2117665745 |
| /workspace/coverage/default/3.prim_present_test.2483127865 |
| /workspace/coverage/default/30.prim_present_test.290099961 |
| /workspace/coverage/default/31.prim_present_test.2534528548 |
| /workspace/coverage/default/32.prim_present_test.3130409067 |
| /workspace/coverage/default/33.prim_present_test.665860643 |
| /workspace/coverage/default/34.prim_present_test.199764683 |
| /workspace/coverage/default/35.prim_present_test.3618622857 |
| /workspace/coverage/default/36.prim_present_test.1611858449 |
| /workspace/coverage/default/37.prim_present_test.2016732512 |
| /workspace/coverage/default/38.prim_present_test.1050859319 |
| /workspace/coverage/default/39.prim_present_test.1383413513 |
| /workspace/coverage/default/4.prim_present_test.301912114 |
| /workspace/coverage/default/40.prim_present_test.3843334611 |
| /workspace/coverage/default/41.prim_present_test.1427057158 |
| /workspace/coverage/default/42.prim_present_test.1315172413 |
| /workspace/coverage/default/43.prim_present_test.877667296 |
| /workspace/coverage/default/44.prim_present_test.631236230 |
| /workspace/coverage/default/45.prim_present_test.4027733121 |
| /workspace/coverage/default/46.prim_present_test.4271897572 |
| /workspace/coverage/default/47.prim_present_test.2772766223 |
| /workspace/coverage/default/48.prim_present_test.2149049738 |
| /workspace/coverage/default/49.prim_present_test.1000236249 |
| /workspace/coverage/default/5.prim_present_test.2610240703 |
| /workspace/coverage/default/6.prim_present_test.3715285848 |
| /workspace/coverage/default/7.prim_present_test.3743464357 |
| /workspace/coverage/default/8.prim_present_test.4025678251 |
| /workspace/coverage/default/9.prim_present_test.2440149453 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/34.prim_present_test.199764683 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:51:39 PM PDT 24 | 12205320000 ps | ||
| T2 | /workspace/coverage/default/2.prim_present_test.1620414933 | Aug 06 06:50:15 PM PDT 24 | Aug 06 06:51:24 PM PDT 24 | 11670260000 ps | ||
| T3 | /workspace/coverage/default/4.prim_present_test.301912114 | Aug 06 06:50:17 PM PDT 24 | Aug 06 06:51:42 PM PDT 24 | 12227020000 ps | ||
| T4 | /workspace/coverage/default/7.prim_present_test.3743464357 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:51:37 PM PDT 24 | 13641240000 ps | ||
| T5 | /workspace/coverage/default/36.prim_present_test.1611858449 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:51:53 PM PDT 24 | 14483820000 ps | ||
| T6 | /workspace/coverage/default/0.prim_present_test.238402813 | Aug 06 06:50:16 PM PDT 24 | Aug 06 06:51:34 PM PDT 24 | 12597780000 ps | ||
| T7 | /workspace/coverage/default/11.prim_present_test.1621289755 | Aug 06 06:50:19 PM PDT 24 | Aug 06 06:50:51 PM PDT 24 | 4204220000 ps | ||
| T8 | /workspace/coverage/default/6.prim_present_test.3715285848 | Aug 06 06:50:14 PM PDT 24 | Aug 06 06:51:41 PM PDT 24 | 15221000000 ps | ||
| T9 | /workspace/coverage/default/49.prim_present_test.1000236249 | Aug 06 06:50:37 PM PDT 24 | Aug 06 06:51:45 PM PDT 24 | 11395600000 ps | ||
| T10 | /workspace/coverage/default/10.prim_present_test.934862946 | Aug 06 06:50:16 PM PDT 24 | Aug 06 06:51:42 PM PDT 24 | 12137120000 ps | ||
| T11 | /workspace/coverage/default/39.prim_present_test.1383413513 | Aug 06 06:50:23 PM PDT 24 | Aug 06 06:52:10 PM PDT 24 | 15207360000 ps | ||
| T12 | /workspace/coverage/default/30.prim_present_test.290099961 | Aug 06 06:50:22 PM PDT 24 | Aug 06 06:51:47 PM PDT 24 | 12407440000 ps | ||
| T13 | /workspace/coverage/default/22.prim_present_test.3503701996 | Aug 06 06:50:19 PM PDT 24 | Aug 06 06:51:56 PM PDT 24 | 12990240000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.1427057158 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:51:03 PM PDT 24 | 6040660000 ps | ||
| T15 | /workspace/coverage/default/15.prim_present_test.205471943 | Aug 06 06:50:19 PM PDT 24 | Aug 06 06:52:07 PM PDT 24 | 14804360000 ps | ||
| T16 | /workspace/coverage/default/12.prim_present_test.4207143368 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:50:44 PM PDT 24 | 3831600000 ps | ||
| T17 | /workspace/coverage/default/35.prim_present_test.3618622857 | Aug 06 06:50:22 PM PDT 24 | Aug 06 06:50:56 PM PDT 24 | 4524760000 ps | ||
| T18 | /workspace/coverage/default/27.prim_present_test.42773186 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:51:17 PM PDT 24 | 9792900000 ps | ||
| T19 | /workspace/coverage/default/5.prim_present_test.2610240703 | Aug 06 06:50:14 PM PDT 24 | Aug 06 06:51:40 PM PDT 24 | 14602240000 ps | ||
| T20 | /workspace/coverage/default/29.prim_present_test.2117665745 | Aug 06 06:50:15 PM PDT 24 | Aug 06 06:51:37 PM PDT 24 | 11500380000 ps | ||
| T21 | /workspace/coverage/default/8.prim_present_test.4025678251 | Aug 06 06:50:16 PM PDT 24 | Aug 06 06:51:19 PM PDT 24 | 8781060000 ps | ||
| T22 | /workspace/coverage/default/14.prim_present_test.4278546542 | Aug 06 06:50:15 PM PDT 24 | Aug 06 06:50:34 PM PDT 24 | 3113640000 ps | ||
| T23 | /workspace/coverage/default/3.prim_present_test.2483127865 | Aug 06 06:50:23 PM PDT 24 | Aug 06 06:51:41 PM PDT 24 | 10709260000 ps | ||
| T24 | /workspace/coverage/default/21.prim_present_test.62816817 | Aug 06 06:50:19 PM PDT 24 | Aug 06 06:51:39 PM PDT 24 | 10567280000 ps | ||
| T25 | /workspace/coverage/default/45.prim_present_test.4027733121 | Aug 06 06:50:19 PM PDT 24 | Aug 06 06:51:59 PM PDT 24 | 15455980000 ps | ||
| T26 | /workspace/coverage/default/38.prim_present_test.1050859319 | Aug 06 06:50:23 PM PDT 24 | Aug 06 06:52:01 PM PDT 24 | 13888620000 ps | ||
| T27 | /workspace/coverage/default/47.prim_present_test.2772766223 | Aug 06 06:50:38 PM PDT 24 | Aug 06 06:52:01 PM PDT 24 | 14339360000 ps | ||
| T28 | /workspace/coverage/default/42.prim_present_test.1315172413 | Aug 06 06:50:23 PM PDT 24 | Aug 06 06:52:01 PM PDT 24 | 13775160000 ps | ||
| T29 | /workspace/coverage/default/17.prim_present_test.4050326030 | Aug 06 06:50:15 PM PDT 24 | Aug 06 06:51:42 PM PDT 24 | 14311460000 ps | ||
| T30 | /workspace/coverage/default/43.prim_present_test.877667296 | Aug 06 06:50:17 PM PDT 24 | Aug 06 06:50:43 PM PDT 24 | 3774560000 ps | ||
| T31 | /workspace/coverage/default/26.prim_present_test.1510660869 | Aug 06 06:50:14 PM PDT 24 | Aug 06 06:51:24 PM PDT 24 | 12390700000 ps | ||
| T32 | /workspace/coverage/default/20.prim_present_test.3321716560 | Aug 06 06:50:19 PM PDT 24 | Aug 06 06:50:49 PM PDT 24 | 4688440000 ps | ||
| T33 | /workspace/coverage/default/28.prim_present_test.3639841843 | Aug 06 06:50:16 PM PDT 24 | Aug 06 06:51:10 PM PDT 24 | 7106440000 ps | ||
| T34 | /workspace/coverage/default/23.prim_present_test.1786616929 | Aug 06 06:50:16 PM PDT 24 | Aug 06 06:51:23 PM PDT 24 | 9708580000 ps | ||
| T35 | /workspace/coverage/default/31.prim_present_test.2534528548 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:51:35 PM PDT 24 | 12094960000 ps | ||
| T36 | /workspace/coverage/default/1.prim_present_test.308689447 | Aug 06 06:50:20 PM PDT 24 | Aug 06 06:50:43 PM PDT 24 | 3658620000 ps | ||
| T37 | /workspace/coverage/default/25.prim_present_test.3352958393 | Aug 06 06:50:15 PM PDT 24 | Aug 06 06:50:39 PM PDT 24 | 3465800000 ps | ||
| T38 | /workspace/coverage/default/33.prim_present_test.665860643 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:51:28 PM PDT 24 | 10652840000 ps | ||
| T39 | /workspace/coverage/default/19.prim_present_test.2678649671 | Aug 06 06:50:15 PM PDT 24 | Aug 06 06:51:26 PM PDT 24 | 10558600000 ps | ||
| T40 | /workspace/coverage/default/46.prim_present_test.4271897572 | Aug 06 06:50:17 PM PDT 24 | Aug 06 06:50:43 PM PDT 24 | 3655520000 ps | ||
| T41 | /workspace/coverage/default/40.prim_present_test.3843334611 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:50:46 PM PDT 24 | 4075260000 ps | ||
| T42 | /workspace/coverage/default/44.prim_present_test.631236230 | Aug 06 06:50:19 PM PDT 24 | Aug 06 06:50:41 PM PDT 24 | 3383340000 ps | ||
| T43 | /workspace/coverage/default/16.prim_present_test.1422630665 | Aug 06 06:50:15 PM PDT 24 | Aug 06 06:51:23 PM PDT 24 | 11046540000 ps | ||
| T44 | /workspace/coverage/default/18.prim_present_test.2185501627 | Aug 06 06:50:17 PM PDT 24 | Aug 06 06:50:48 PM PDT 24 | 4499960000 ps | ||
| T45 | /workspace/coverage/default/24.prim_present_test.2946788863 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:50:48 PM PDT 24 | 4111220000 ps | ||
| T46 | /workspace/coverage/default/48.prim_present_test.2149049738 | Aug 06 06:50:38 PM PDT 24 | Aug 06 06:51:24 PM PDT 24 | 7961420000 ps | ||
| T47 | /workspace/coverage/default/9.prim_present_test.2440149453 | Aug 06 06:50:16 PM PDT 24 | Aug 06 06:50:52 PM PDT 24 | 5902400000 ps | ||
| T48 | /workspace/coverage/default/32.prim_present_test.3130409067 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:50:46 PM PDT 24 | 3659860000 ps | ||
| T49 | /workspace/coverage/default/13.prim_present_test.4115034856 | Aug 06 06:50:18 PM PDT 24 | Aug 06 06:51:12 PM PDT 24 | 7795880000 ps | ||
| T50 | /workspace/coverage/default/37.prim_present_test.2016732512 | Aug 06 06:50:23 PM PDT 24 | Aug 06 06:51:50 PM PDT 24 | 11953600000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.238402813 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12597780000 ps |
| CPU time | 41.19 seconds |
| Started | Aug 06 06:50:16 PM PDT 24 |
| Finished | Aug 06 06:51:34 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-827ce746-63c1-42a0-a22b-0c9bdfdb530e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=238402813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.238402813 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.308689447 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3658620000 ps |
| CPU time | 12.36 seconds |
| Started | Aug 06 06:50:20 PM PDT 24 |
| Finished | Aug 06 06:50:43 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-0b191a80-1e61-45f5-9812-6feb33d80c56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308689447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.308689447 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.934862946 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12137120000 ps |
| CPU time | 43.79 seconds |
| Started | Aug 06 06:50:16 PM PDT 24 |
| Finished | Aug 06 06:51:42 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-1a99bc17-d109-4242-b9a4-67d98e0539d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=934862946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.934862946 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1621289755 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4204220000 ps |
| CPU time | 15.98 seconds |
| Started | Aug 06 06:50:19 PM PDT 24 |
| Finished | Aug 06 06:50:51 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-9a005749-0ff3-4fc9-88df-d1e02c19b37e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1621289755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1621289755 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4207143368 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3831600000 ps |
| CPU time | 13.8 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:50:44 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-a5d3e707-f2be-4b8f-a645-0e6cb64e621b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4207143368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4207143368 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.4115034856 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7795880000 ps |
| CPU time | 27.51 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:51:12 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-8735c01d-9bc4-4651-a83f-463171b4bcf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115034856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.4115034856 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4278546542 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3113640000 ps |
| CPU time | 10.39 seconds |
| Started | Aug 06 06:50:15 PM PDT 24 |
| Finished | Aug 06 06:50:34 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-67b65c34-cfcb-4f67-985c-30cc3064d9aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278546542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4278546542 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.205471943 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 14804360000 ps |
| CPU time | 54.64 seconds |
| Started | Aug 06 06:50:19 PM PDT 24 |
| Finished | Aug 06 06:52:07 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-88653140-56e1-4bb2-a9e4-68465f0f289f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205471943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.205471943 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1422630665 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11046540000 ps |
| CPU time | 36.25 seconds |
| Started | Aug 06 06:50:15 PM PDT 24 |
| Finished | Aug 06 06:51:23 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-3ef4054c-d3f1-4a66-b5b7-c24d3a4485c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422630665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1422630665 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4050326030 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14311460000 ps |
| CPU time | 47.19 seconds |
| Started | Aug 06 06:50:15 PM PDT 24 |
| Finished | Aug 06 06:51:42 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-4ba868c9-bd28-4af1-8c06-79f57148a621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050326030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4050326030 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2185501627 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4499960000 ps |
| CPU time | 16.6 seconds |
| Started | Aug 06 06:50:17 PM PDT 24 |
| Finished | Aug 06 06:50:48 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-1c77fcd8-f8d5-47e7-86f4-e5062c960a11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2185501627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2185501627 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2678649671 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10558600000 ps |
| CPU time | 36.68 seconds |
| Started | Aug 06 06:50:15 PM PDT 24 |
| Finished | Aug 06 06:51:26 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-1159d5fd-0217-4dfb-8b39-1db78aecc8f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678649671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2678649671 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1620414933 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11670260000 ps |
| CPU time | 37 seconds |
| Started | Aug 06 06:50:15 PM PDT 24 |
| Finished | Aug 06 06:51:24 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-76c4597b-c150-4add-b8a2-94a124b50655 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1620414933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1620414933 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3321716560 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4688440000 ps |
| CPU time | 16.04 seconds |
| Started | Aug 06 06:50:19 PM PDT 24 |
| Finished | Aug 06 06:50:49 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-f1c38cf0-7a8e-492a-975d-6039c26d6792 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321716560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3321716560 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.62816817 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10567280000 ps |
| CPU time | 39.57 seconds |
| Started | Aug 06 06:50:19 PM PDT 24 |
| Finished | Aug 06 06:51:39 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-b68026c1-dc6f-45cb-89ab-99ee576c15e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62816817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.62816817 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3503701996 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12990240000 ps |
| CPU time | 48.83 seconds |
| Started | Aug 06 06:50:19 PM PDT 24 |
| Finished | Aug 06 06:51:56 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-e8c74dce-a2bd-4b8b-bf73-39b6174e69d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503701996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3503701996 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1786616929 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9708580000 ps |
| CPU time | 36.01 seconds |
| Started | Aug 06 06:50:16 PM PDT 24 |
| Finished | Aug 06 06:51:23 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-9bd21bb2-6d8b-456f-b752-bed79e9eba42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786616929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1786616929 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2946788863 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4111220000 ps |
| CPU time | 14.7 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:50:48 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-447c381e-2cf9-4bdc-a0a8-728948685467 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2946788863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2946788863 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3352958393 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3465800000 ps |
| CPU time | 12.86 seconds |
| Started | Aug 06 06:50:15 PM PDT 24 |
| Finished | Aug 06 06:50:39 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-0aa3f97f-9c8a-4c4b-8b5e-94d723bbe5d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352958393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3352958393 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1510660869 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12390700000 ps |
| CPU time | 37.32 seconds |
| Started | Aug 06 06:50:14 PM PDT 24 |
| Finished | Aug 06 06:51:24 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-5890eb5f-2921-4de8-8f8f-4193f31b0ead |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510660869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1510660869 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.42773186 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9792900000 ps |
| CPU time | 31.65 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:51:17 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-dc1d47d3-ff31-45e7-aeda-d362a06b671d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42773186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.42773186 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3639841843 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7106440000 ps |
| CPU time | 26.72 seconds |
| Started | Aug 06 06:50:16 PM PDT 24 |
| Finished | Aug 06 06:51:10 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-af275c24-bf09-4581-b142-1973d462a08e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639841843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3639841843 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2117665745 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11500380000 ps |
| CPU time | 42.08 seconds |
| Started | Aug 06 06:50:15 PM PDT 24 |
| Finished | Aug 06 06:51:37 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-4ef15b0e-bfc9-4706-923a-106eed0b6fdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117665745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2117665745 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2483127865 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10709260000 ps |
| CPU time | 39.91 seconds |
| Started | Aug 06 06:50:23 PM PDT 24 |
| Finished | Aug 06 06:51:41 PM PDT 24 |
| Peak memory | 144456 kb |
| Host | smart-ddab8fa8-05b9-4d96-8356-dc720bf57f1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483127865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2483127865 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.290099961 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12407440000 ps |
| CPU time | 44.49 seconds |
| Started | Aug 06 06:50:22 PM PDT 24 |
| Finished | Aug 06 06:51:47 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-b767644f-ec03-4a96-95ba-7bedfd00d9f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290099961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.290099961 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2534528548 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12094960000 ps |
| CPU time | 39.74 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:51:35 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-371083c0-636a-422e-9ed0-2afbdf30bc73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534528548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2534528548 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3130409067 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3659860000 ps |
| CPU time | 14.53 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:50:46 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-490771d1-69bd-4456-9c55-cab7fb275b88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130409067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3130409067 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.665860643 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10652840000 ps |
| CPU time | 36.34 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:51:28 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-7926bcd9-1a2f-458f-b284-f449bf8dadc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665860643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.665860643 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.199764683 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12205320000 ps |
| CPU time | 42.54 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:51:39 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-80edc8ce-f97c-4348-85e5-0d24b483d75b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=199764683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.199764683 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3618622857 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4524760000 ps |
| CPU time | 17.85 seconds |
| Started | Aug 06 06:50:22 PM PDT 24 |
| Finished | Aug 06 06:50:56 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-29cfa682-a43b-4fd2-b3bb-bc1cbf7e2a4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618622857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3618622857 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1611858449 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14483820000 ps |
| CPU time | 49.83 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:51:53 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-38bb4eb2-0f56-4a62-98fc-4d682ab9566f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611858449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1611858449 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2016732512 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11953600000 ps |
| CPU time | 44.39 seconds |
| Started | Aug 06 06:50:23 PM PDT 24 |
| Finished | Aug 06 06:51:50 PM PDT 24 |
| Peak memory | 144592 kb |
| Host | smart-9a866770-30e8-4610-9bc7-ff05c8000d4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016732512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2016732512 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1050859319 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13888620000 ps |
| CPU time | 50.82 seconds |
| Started | Aug 06 06:50:23 PM PDT 24 |
| Finished | Aug 06 06:52:01 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-56c17d2a-97b1-43e7-8ee0-62eef17c9671 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050859319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1050859319 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1383413513 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 15207360000 ps |
| CPU time | 55.45 seconds |
| Started | Aug 06 06:50:23 PM PDT 24 |
| Finished | Aug 06 06:52:10 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-73c1bc42-5143-4d03-8bb1-3501b5a93a79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1383413513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1383413513 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.301912114 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12227020000 ps |
| CPU time | 44.81 seconds |
| Started | Aug 06 06:50:17 PM PDT 24 |
| Finished | Aug 06 06:51:42 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-fa81eb17-3b6b-42e1-8235-aba72670b159 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301912114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.301912114 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3843334611 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4075260000 ps |
| CPU time | 14.3 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:50:46 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-dd942be4-1268-4527-bfdd-2291385fbc7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843334611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3843334611 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1427057158 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6040660000 ps |
| CPU time | 22.57 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:51:03 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-dc4b334d-c26a-44d1-8902-94eecafeea4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427057158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1427057158 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1315172413 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 13775160000 ps |
| CPU time | 50.04 seconds |
| Started | Aug 06 06:50:23 PM PDT 24 |
| Finished | Aug 06 06:52:01 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-e6dd6935-8b2e-4f09-b3ff-46430a326051 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315172413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1315172413 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.877667296 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3774560000 ps |
| CPU time | 13.19 seconds |
| Started | Aug 06 06:50:17 PM PDT 24 |
| Finished | Aug 06 06:50:43 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-6efd8e9e-c636-49cf-9d70-973570d12920 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877667296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.877667296 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.631236230 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3383340000 ps |
| CPU time | 11.89 seconds |
| Started | Aug 06 06:50:19 PM PDT 24 |
| Finished | Aug 06 06:50:41 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-b5795370-0a1f-4161-b93e-0366608664e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631236230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.631236230 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4027733121 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 15455980000 ps |
| CPU time | 52.72 seconds |
| Started | Aug 06 06:50:19 PM PDT 24 |
| Finished | Aug 06 06:51:59 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-d1c1ed33-eadd-40c3-a7ea-c1eb5e8eb476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027733121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4027733121 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4271897572 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3655520000 ps |
| CPU time | 13.03 seconds |
| Started | Aug 06 06:50:17 PM PDT 24 |
| Finished | Aug 06 06:50:43 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-2aff9d37-e986-417c-a2d6-f3eb970b8dbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271897572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4271897572 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2772766223 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14339360000 ps |
| CPU time | 44.64 seconds |
| Started | Aug 06 06:50:38 PM PDT 24 |
| Finished | Aug 06 06:52:01 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-5a0b171b-34a5-4953-9f88-8147ee2e1fbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772766223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2772766223 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2149049738 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7961420000 ps |
| CPU time | 25.07 seconds |
| Started | Aug 06 06:50:38 PM PDT 24 |
| Finished | Aug 06 06:51:24 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-def5790f-9bd7-4de7-b872-d0c204ca412f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2149049738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2149049738 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1000236249 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11395600000 ps |
| CPU time | 36.21 seconds |
| Started | Aug 06 06:50:37 PM PDT 24 |
| Finished | Aug 06 06:51:45 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-a7a6db14-9f87-4089-a011-c17d3bcbd606 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000236249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1000236249 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2610240703 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14602240000 ps |
| CPU time | 45.31 seconds |
| Started | Aug 06 06:50:14 PM PDT 24 |
| Finished | Aug 06 06:51:40 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-7e0b2b76-8d4e-435f-81c7-b2d5ba9ad4b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610240703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2610240703 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3715285848 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 15221000000 ps |
| CPU time | 46.56 seconds |
| Started | Aug 06 06:50:14 PM PDT 24 |
| Finished | Aug 06 06:51:41 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-05ea7d1d-1bdd-4651-8b5d-31094144a456 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715285848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3715285848 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3743464357 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13641240000 ps |
| CPU time | 42.04 seconds |
| Started | Aug 06 06:50:18 PM PDT 24 |
| Finished | Aug 06 06:51:37 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-5687afec-26e3-4d49-8b3f-9b5c0fa225ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3743464357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3743464357 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4025678251 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8781060000 ps |
| CPU time | 32.27 seconds |
| Started | Aug 06 06:50:16 PM PDT 24 |
| Finished | Aug 06 06:51:19 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-a1a35d6c-e355-4d48-902a-265d50092a0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025678251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4025678251 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2440149453 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5902400000 ps |
| CPU time | 19.29 seconds |
| Started | Aug 06 06:50:16 PM PDT 24 |
| Finished | Aug 06 06:50:52 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-45248f08-d70a-4d6e-ba6c-a5cacc2d47ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440149453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2440149453 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |