| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.3198719967 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1591745892 |
| /workspace/coverage/default/1.prim_present_test.1537783533 |
| /workspace/coverage/default/10.prim_present_test.695937279 |
| /workspace/coverage/default/12.prim_present_test.3674671940 |
| /workspace/coverage/default/13.prim_present_test.1768010923 |
| /workspace/coverage/default/14.prim_present_test.3594842765 |
| /workspace/coverage/default/15.prim_present_test.1710801633 |
| /workspace/coverage/default/16.prim_present_test.4182242883 |
| /workspace/coverage/default/17.prim_present_test.3330356166 |
| /workspace/coverage/default/18.prim_present_test.3596416270 |
| /workspace/coverage/default/19.prim_present_test.2087574116 |
| /workspace/coverage/default/2.prim_present_test.1755705928 |
| /workspace/coverage/default/20.prim_present_test.980468173 |
| /workspace/coverage/default/21.prim_present_test.1941427693 |
| /workspace/coverage/default/22.prim_present_test.1965200033 |
| /workspace/coverage/default/23.prim_present_test.3353756775 |
| /workspace/coverage/default/24.prim_present_test.2548531747 |
| /workspace/coverage/default/25.prim_present_test.901360734 |
| /workspace/coverage/default/26.prim_present_test.3370265702 |
| /workspace/coverage/default/27.prim_present_test.3817422222 |
| /workspace/coverage/default/28.prim_present_test.2610491836 |
| /workspace/coverage/default/29.prim_present_test.1182507962 |
| /workspace/coverage/default/3.prim_present_test.3818033893 |
| /workspace/coverage/default/30.prim_present_test.3163722324 |
| /workspace/coverage/default/31.prim_present_test.3779639076 |
| /workspace/coverage/default/32.prim_present_test.3266832279 |
| /workspace/coverage/default/33.prim_present_test.4074622053 |
| /workspace/coverage/default/34.prim_present_test.2859322781 |
| /workspace/coverage/default/35.prim_present_test.4292259419 |
| /workspace/coverage/default/36.prim_present_test.69436505 |
| /workspace/coverage/default/37.prim_present_test.1274674888 |
| /workspace/coverage/default/38.prim_present_test.4216531824 |
| /workspace/coverage/default/39.prim_present_test.3524154847 |
| /workspace/coverage/default/4.prim_present_test.398844809 |
| /workspace/coverage/default/40.prim_present_test.867780557 |
| /workspace/coverage/default/41.prim_present_test.1613283100 |
| /workspace/coverage/default/42.prim_present_test.2144332424 |
| /workspace/coverage/default/43.prim_present_test.1625343630 |
| /workspace/coverage/default/44.prim_present_test.846588499 |
| /workspace/coverage/default/45.prim_present_test.3443087441 |
| /workspace/coverage/default/46.prim_present_test.3590541691 |
| /workspace/coverage/default/47.prim_present_test.1810370714 |
| /workspace/coverage/default/48.prim_present_test.2985870002 |
| /workspace/coverage/default/49.prim_present_test.3823608515 |
| /workspace/coverage/default/5.prim_present_test.1233282794 |
| /workspace/coverage/default/6.prim_present_test.2205234128 |
| /workspace/coverage/default/7.prim_present_test.1595871336 |
| /workspace/coverage/default/8.prim_present_test.2334956607 |
| /workspace/coverage/default/9.prim_present_test.39793221 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/29.prim_present_test.1182507962 | Aug 07 04:21:29 PM PDT 24 | Aug 07 04:22:22 PM PDT 24 | 8547320000 ps | ||
| T2 | /workspace/coverage/default/47.prim_present_test.1810370714 | Aug 07 04:24:20 PM PDT 24 | Aug 07 04:25:57 PM PDT 24 | 15467760000 ps | ||
| T3 | /workspace/coverage/default/6.prim_present_test.2205234128 | Aug 07 04:24:55 PM PDT 24 | Aug 07 04:25:30 PM PDT 24 | 6307880000 ps | ||
| T4 | /workspace/coverage/default/13.prim_present_test.1768010923 | Aug 07 04:24:06 PM PDT 24 | Aug 07 04:24:49 PM PDT 24 | 5947660000 ps | ||
| T5 | /workspace/coverage/default/4.prim_present_test.398844809 | Aug 07 04:20:12 PM PDT 24 | Aug 07 04:21:15 PM PDT 24 | 9280780000 ps | ||
| T6 | /workspace/coverage/default/14.prim_present_test.3594842765 | Aug 07 04:24:09 PM PDT 24 | Aug 07 04:25:21 PM PDT 24 | 11682660000 ps | ||
| T7 | /workspace/coverage/default/11.prim_present_test.3198719967 | Aug 07 04:24:47 PM PDT 24 | Aug 07 04:25:49 PM PDT 24 | 9745160000 ps | ||
| T8 | /workspace/coverage/default/23.prim_present_test.3353756775 | Aug 07 04:22:28 PM PDT 24 | Aug 07 04:23:42 PM PDT 24 | 10359580000 ps | ||
| T9 | /workspace/coverage/default/45.prim_present_test.3443087441 | Aug 07 04:24:29 PM PDT 24 | Aug 07 04:25:31 PM PDT 24 | 11085600000 ps | ||
| T10 | /workspace/coverage/default/32.prim_present_test.3266832279 | Aug 07 04:22:17 PM PDT 24 | Aug 07 04:22:52 PM PDT 24 | 4659300000 ps | ||
| T11 | /workspace/coverage/default/2.prim_present_test.1755705928 | Aug 07 04:23:09 PM PDT 24 | Aug 07 04:24:14 PM PDT 24 | 8433860000 ps | ||
| T12 | /workspace/coverage/default/44.prim_present_test.846588499 | Aug 07 04:24:35 PM PDT 24 | Aug 07 04:25:04 PM PDT 24 | 3845240000 ps | ||
| T13 | /workspace/coverage/default/5.prim_present_test.1233282794 | Aug 07 04:21:59 PM PDT 24 | Aug 07 04:23:29 PM PDT 24 | 12845160000 ps | ||
| T14 | /workspace/coverage/default/15.prim_present_test.1710801633 | Aug 07 04:20:02 PM PDT 24 | Aug 07 04:21:40 PM PDT 24 | 15436760000 ps | ||
| T15 | /workspace/coverage/default/17.prim_present_test.3330356166 | Aug 07 04:22:32 PM PDT 24 | Aug 07 04:23:10 PM PDT 24 | 5239000000 ps | ||
| T16 | /workspace/coverage/default/20.prim_present_test.980468173 | Aug 07 04:22:11 PM PDT 24 | Aug 07 04:23:02 PM PDT 24 | 6801400000 ps | ||
| T17 | /workspace/coverage/default/39.prim_present_test.3524154847 | Aug 07 04:25:00 PM PDT 24 | Aug 07 04:25:23 PM PDT 24 | 4201120000 ps | ||
| T18 | /workspace/coverage/default/30.prim_present_test.3163722324 | Aug 07 04:22:10 PM PDT 24 | Aug 07 04:23:25 PM PDT 24 | 9889000000 ps | ||
| T19 | /workspace/coverage/default/7.prim_present_test.1595871336 | Aug 07 04:24:48 PM PDT 24 | Aug 07 04:25:50 PM PDT 24 | 10788620000 ps | ||
| T20 | /workspace/coverage/default/12.prim_present_test.3674671940 | Aug 07 04:22:27 PM PDT 24 | Aug 07 04:24:12 PM PDT 24 | 14245120000 ps | ||
| T21 | /workspace/coverage/default/16.prim_present_test.4182242883 | Aug 07 04:20:28 PM PDT 24 | Aug 07 04:21:13 PM PDT 24 | 6552780000 ps | ||
| T22 | /workspace/coverage/default/49.prim_present_test.3823608515 | Aug 07 04:24:25 PM PDT 24 | Aug 07 04:25:11 PM PDT 24 | 7252760000 ps | ||
| T23 | /workspace/coverage/default/27.prim_present_test.3817422222 | Aug 07 04:20:39 PM PDT 24 | Aug 07 04:22:11 PM PDT 24 | 12998300000 ps | ||
| T24 | /workspace/coverage/default/36.prim_present_test.69436505 | Aug 07 04:24:20 PM PDT 24 | Aug 07 04:25:53 PM PDT 24 | 14679740000 ps | ||
| T25 | /workspace/coverage/default/48.prim_present_test.2985870002 | Aug 07 04:24:19 PM PDT 24 | Aug 07 04:25:44 PM PDT 24 | 14424920000 ps | ||
| T26 | /workspace/coverage/default/37.prim_present_test.1274674888 | Aug 07 04:24:20 PM PDT 24 | Aug 07 04:25:23 PM PDT 24 | 11293920000 ps | ||
| T27 | /workspace/coverage/default/10.prim_present_test.695937279 | Aug 07 04:22:51 PM PDT 24 | Aug 07 04:24:36 PM PDT 24 | 14591700000 ps | ||
| T28 | /workspace/coverage/default/40.prim_present_test.867780557 | Aug 07 04:22:22 PM PDT 24 | Aug 07 04:23:44 PM PDT 24 | 13160120000 ps | ||
| T29 | /workspace/coverage/default/31.prim_present_test.3779639076 | Aug 07 04:22:16 PM PDT 24 | Aug 07 04:23:40 PM PDT 24 | 12290260000 ps | ||
| T30 | /workspace/coverage/default/43.prim_present_test.1625343630 | Aug 07 04:24:30 PM PDT 24 | Aug 07 04:25:29 PM PDT 24 | 10368260000 ps | ||
| T31 | /workspace/coverage/default/34.prim_present_test.2859322781 | Aug 07 04:24:22 PM PDT 24 | Aug 07 04:25:21 PM PDT 24 | 10742740000 ps | ||
| T32 | /workspace/coverage/default/28.prim_present_test.2610491836 | Aug 07 04:25:00 PM PDT 24 | Aug 07 04:25:22 PM PDT 24 | 4052320000 ps | ||
| T33 | /workspace/coverage/default/41.prim_present_test.1613283100 | Aug 07 04:24:35 PM PDT 24 | Aug 07 04:25:30 PM PDT 24 | 7729540000 ps | ||
| T34 | /workspace/coverage/default/26.prim_present_test.3370265702 | Aug 07 04:24:47 PM PDT 24 | Aug 07 04:25:23 PM PDT 24 | 6913620000 ps | ||
| T35 | /workspace/coverage/default/25.prim_present_test.901360734 | Aug 07 04:24:47 PM PDT 24 | Aug 07 04:26:00 PM PDT 24 | 11364600000 ps | ||
| T36 | /workspace/coverage/default/24.prim_present_test.2548531747 | Aug 07 04:24:47 PM PDT 24 | Aug 07 04:25:28 PM PDT 24 | 6188220000 ps | ||
| T37 | /workspace/coverage/default/3.prim_present_test.3818033893 | Aug 07 04:21:55 PM PDT 24 | Aug 07 04:22:17 PM PDT 24 | 3409380000 ps | ||
| T38 | /workspace/coverage/default/8.prim_present_test.2334956607 | Aug 07 04:20:29 PM PDT 24 | Aug 07 04:21:02 PM PDT 24 | 4764700000 ps | ||
| T39 | /workspace/coverage/default/18.prim_present_test.3596416270 | Aug 07 04:22:34 PM PDT 24 | Aug 07 04:24:02 PM PDT 24 | 12533920000 ps | ||
| T40 | /workspace/coverage/default/42.prim_present_test.2144332424 | Aug 07 04:22:19 PM PDT 24 | Aug 07 04:23:56 PM PDT 24 | 14245740000 ps | ||
| T41 | /workspace/coverage/default/0.prim_present_test.1591745892 | Aug 07 04:21:54 PM PDT 24 | Aug 07 04:22:58 PM PDT 24 | 8539260000 ps | ||
| T42 | /workspace/coverage/default/1.prim_present_test.1537783533 | Aug 07 04:23:13 PM PDT 24 | Aug 07 04:24:37 PM PDT 24 | 11847580000 ps | ||
| T43 | /workspace/coverage/default/22.prim_present_test.1965200033 | Aug 07 04:24:46 PM PDT 24 | Aug 07 04:26:16 PM PDT 24 | 14383380000 ps | ||
| T44 | /workspace/coverage/default/19.prim_present_test.2087574116 | Aug 07 04:23:11 PM PDT 24 | Aug 07 04:23:56 PM PDT 24 | 6311600000 ps | ||
| T45 | /workspace/coverage/default/9.prim_present_test.39793221 | Aug 07 04:19:36 PM PDT 24 | Aug 07 04:21:24 PM PDT 24 | 15402040000 ps | ||
| T46 | /workspace/coverage/default/46.prim_present_test.3590541691 | Aug 07 04:24:21 PM PDT 24 | Aug 07 04:25:14 PM PDT 24 | 7464800000 ps | ||
| T47 | /workspace/coverage/default/33.prim_present_test.4074622053 | Aug 07 04:23:15 PM PDT 24 | Aug 07 04:23:56 PM PDT 24 | 5506220000 ps | ||
| T48 | /workspace/coverage/default/35.prim_present_test.4292259419 | Aug 07 04:25:33 PM PDT 24 | Aug 07 04:26:46 PM PDT 24 | 10161180000 ps | ||
| T49 | /workspace/coverage/default/21.prim_present_test.1941427693 | Aug 07 04:24:47 PM PDT 24 | Aug 07 04:26:16 PM PDT 24 | 14379040000 ps | ||
| T50 | /workspace/coverage/default/38.prim_present_test.4216531824 | Aug 07 04:24:34 PM PDT 24 | Aug 07 04:25:53 PM PDT 24 | 11255480000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.3198719967 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9745160000 ps |
| CPU time | 33.07 seconds |
| Started | Aug 07 04:24:47 PM PDT 24 |
| Finished | Aug 07 04:25:49 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-bd1f8f9b-595e-4f76-97ac-8013432b48b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198719967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3198719967 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1591745892 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8539260000 ps |
| CPU time | 33.79 seconds |
| Started | Aug 07 04:21:54 PM PDT 24 |
| Finished | Aug 07 04:22:58 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-c5c995a5-fe0f-465f-b680-3be270e4007e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591745892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1591745892 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1537783533 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11847580000 ps |
| CPU time | 44.6 seconds |
| Started | Aug 07 04:23:13 PM PDT 24 |
| Finished | Aug 07 04:24:37 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-32ac6dcd-8c4d-4c82-92dc-6c6a8bef0daa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537783533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1537783533 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.695937279 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14591700000 ps |
| CPU time | 55.25 seconds |
| Started | Aug 07 04:22:51 PM PDT 24 |
| Finished | Aug 07 04:24:36 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-1ca01e34-46c5-4a16-b549-1f9d4183c3b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695937279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.695937279 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3674671940 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14245120000 ps |
| CPU time | 54.33 seconds |
| Started | Aug 07 04:22:27 PM PDT 24 |
| Finished | Aug 07 04:24:12 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-a3358aaf-ff0e-4049-8f98-b6c9f5638034 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3674671940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3674671940 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1768010923 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5947660000 ps |
| CPU time | 23.06 seconds |
| Started | Aug 07 04:24:06 PM PDT 24 |
| Finished | Aug 07 04:24:49 PM PDT 24 |
| Peak memory | 143384 kb |
| Host | smart-57222134-8fce-4c88-9af1-3334542e789d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768010923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1768010923 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3594842765 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11682660000 ps |
| CPU time | 38.94 seconds |
| Started | Aug 07 04:24:09 PM PDT 24 |
| Finished | Aug 07 04:25:21 PM PDT 24 |
| Peak memory | 144692 kb |
| Host | smart-ebe22c9d-abe7-471f-8ad2-952eb4d0d64a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594842765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3594842765 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1710801633 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 15436760000 ps |
| CPU time | 51.48 seconds |
| Started | Aug 07 04:20:02 PM PDT 24 |
| Finished | Aug 07 04:21:40 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-f0b40128-0b18-4c60-9c7c-0dd3c30e2d19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710801633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1710801633 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.4182242883 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 6552780000 ps |
| CPU time | 24.13 seconds |
| Started | Aug 07 04:20:28 PM PDT 24 |
| Finished | Aug 07 04:21:13 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-61f7ea1e-4021-4f46-8a30-21ee51715ebb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182242883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.4182242883 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3330356166 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5239000000 ps |
| CPU time | 20.1 seconds |
| Started | Aug 07 04:22:32 PM PDT 24 |
| Finished | Aug 07 04:23:10 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-ad4b06f1-5119-4cd7-88bf-5f96bc56a38a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330356166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3330356166 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3596416270 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12533920000 ps |
| CPU time | 46.53 seconds |
| Started | Aug 07 04:22:34 PM PDT 24 |
| Finished | Aug 07 04:24:02 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-aecf4f9f-80d3-4b89-9a4a-a0a68e40ec77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596416270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3596416270 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2087574116 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6311600000 ps |
| CPU time | 23.79 seconds |
| Started | Aug 07 04:23:11 PM PDT 24 |
| Finished | Aug 07 04:23:56 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-e4a47d03-cf68-4738-9ebb-9131366ad66d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087574116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2087574116 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1755705928 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8433860000 ps |
| CPU time | 34.16 seconds |
| Started | Aug 07 04:23:09 PM PDT 24 |
| Finished | Aug 07 04:24:14 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-8d0b9550-05f3-401e-9068-e809acc87b60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755705928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1755705928 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.980468173 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6801400000 ps |
| CPU time | 26.99 seconds |
| Started | Aug 07 04:22:11 PM PDT 24 |
| Finished | Aug 07 04:23:02 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-c892e6d1-4783-43d2-8d9d-155f0c75d323 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980468173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.980468173 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1941427693 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14379040000 ps |
| CPU time | 47.3 seconds |
| Started | Aug 07 04:24:47 PM PDT 24 |
| Finished | Aug 07 04:26:16 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-02d463e1-e34d-42d7-b56a-e580d622d1f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941427693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1941427693 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1965200033 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14383380000 ps |
| CPU time | 47.77 seconds |
| Started | Aug 07 04:24:46 PM PDT 24 |
| Finished | Aug 07 04:26:16 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-6d9a9ac6-5563-4da9-9cee-b23ce5f28f39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965200033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1965200033 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3353756775 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10359580000 ps |
| CPU time | 39.09 seconds |
| Started | Aug 07 04:22:28 PM PDT 24 |
| Finished | Aug 07 04:23:42 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-26436f70-6dc0-4b59-9913-53278efe37a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3353756775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3353756775 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2548531747 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6188220000 ps |
| CPU time | 21.5 seconds |
| Started | Aug 07 04:24:47 PM PDT 24 |
| Finished | Aug 07 04:25:28 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-a7d52972-b81b-4c8a-aaf8-b4a70a8fef4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2548531747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2548531747 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.901360734 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11364600000 ps |
| CPU time | 38.59 seconds |
| Started | Aug 07 04:24:47 PM PDT 24 |
| Finished | Aug 07 04:26:00 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-be887a68-d750-4562-ac91-bb421ea6a4c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901360734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.901360734 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3370265702 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6913620000 ps |
| CPU time | 20.09 seconds |
| Started | Aug 07 04:24:47 PM PDT 24 |
| Finished | Aug 07 04:25:23 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-ef26c06f-83c2-4beb-b495-cad41de53f59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370265702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3370265702 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3817422222 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12998300000 ps |
| CPU time | 49.46 seconds |
| Started | Aug 07 04:20:39 PM PDT 24 |
| Finished | Aug 07 04:22:11 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-666fcc53-ba83-432d-a6c1-fc922f552eab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817422222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3817422222 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2610491836 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4052320000 ps |
| CPU time | 12.39 seconds |
| Started | Aug 07 04:25:00 PM PDT 24 |
| Finished | Aug 07 04:25:22 PM PDT 24 |
| Peak memory | 144760 kb |
| Host | smart-a91a02fc-46f9-4702-bd11-78fb1f8c25c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610491836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2610491836 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1182507962 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 8547320000 ps |
| CPU time | 28.93 seconds |
| Started | Aug 07 04:21:29 PM PDT 24 |
| Finished | Aug 07 04:22:22 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-a69104bf-6dbe-48b5-80a9-60465e49cc62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182507962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1182507962 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3818033893 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3409380000 ps |
| CPU time | 12.17 seconds |
| Started | Aug 07 04:21:55 PM PDT 24 |
| Finished | Aug 07 04:22:17 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-a0dfa33c-4510-4638-90e3-f941a4920daa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3818033893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3818033893 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3163722324 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9889000000 ps |
| CPU time | 39.37 seconds |
| Started | Aug 07 04:22:10 PM PDT 24 |
| Finished | Aug 07 04:23:25 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-30b0e614-5516-4939-9afa-b40bdc9fa0ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163722324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3163722324 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3779639076 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 12290260000 ps |
| CPU time | 44.38 seconds |
| Started | Aug 07 04:22:16 PM PDT 24 |
| Finished | Aug 07 04:23:40 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-5f29cfdc-5edf-429e-a706-4f7d9289d1b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779639076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3779639076 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3266832279 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4659300000 ps |
| CPU time | 18.33 seconds |
| Started | Aug 07 04:22:17 PM PDT 24 |
| Finished | Aug 07 04:22:52 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-fcbdb7ee-655e-4243-82a8-d65987bf3720 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266832279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3266832279 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.4074622053 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5506220000 ps |
| CPU time | 21.32 seconds |
| Started | Aug 07 04:23:15 PM PDT 24 |
| Finished | Aug 07 04:23:56 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-93477f5a-81b7-4d63-abab-674991a8b26f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074622053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.4074622053 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2859322781 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10742740000 ps |
| CPU time | 32.22 seconds |
| Started | Aug 07 04:24:22 PM PDT 24 |
| Finished | Aug 07 04:25:21 PM PDT 24 |
| Peak memory | 143864 kb |
| Host | smart-d58540c3-070d-432b-8355-38463a153d8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859322781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2859322781 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4292259419 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10161180000 ps |
| CPU time | 38.37 seconds |
| Started | Aug 07 04:25:33 PM PDT 24 |
| Finished | Aug 07 04:26:46 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-a76ecb66-6e9b-4392-8aac-87590bea3457 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292259419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4292259419 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.69436505 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 14679740000 ps |
| CPU time | 49.51 seconds |
| Started | Aug 07 04:24:20 PM PDT 24 |
| Finished | Aug 07 04:25:53 PM PDT 24 |
| Peak memory | 143760 kb |
| Host | smart-ce87a6ce-baa4-4a2d-bcb4-d5dfc51bcc13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69436505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.69436505 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1274674888 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11293920000 ps |
| CPU time | 34.74 seconds |
| Started | Aug 07 04:24:20 PM PDT 24 |
| Finished | Aug 07 04:25:23 PM PDT 24 |
| Peak memory | 144552 kb |
| Host | smart-41f9c691-4ba7-4f1e-a46d-296fd3f08cc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274674888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1274674888 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.4216531824 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11255480000 ps |
| CPU time | 41.38 seconds |
| Started | Aug 07 04:24:34 PM PDT 24 |
| Finished | Aug 07 04:25:53 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-8270931d-fa97-4be0-a6cf-6e35a2f9b228 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216531824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.4216531824 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3524154847 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4201120000 ps |
| CPU time | 12.55 seconds |
| Started | Aug 07 04:25:00 PM PDT 24 |
| Finished | Aug 07 04:25:23 PM PDT 24 |
| Peak memory | 144444 kb |
| Host | smart-4b984cff-bc6c-4632-9248-27029c6b22d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524154847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3524154847 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.398844809 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 9280780000 ps |
| CPU time | 33.76 seconds |
| Started | Aug 07 04:20:12 PM PDT 24 |
| Finished | Aug 07 04:21:15 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-43de4619-e172-41da-87bb-3e9df18d78e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398844809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.398844809 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.867780557 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 13160120000 ps |
| CPU time | 43.96 seconds |
| Started | Aug 07 04:22:22 PM PDT 24 |
| Finished | Aug 07 04:23:44 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-889e8fbd-14b1-47f6-9c3d-4108fec78e09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=867780557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.867780557 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1613283100 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7729540000 ps |
| CPU time | 29.13 seconds |
| Started | Aug 07 04:24:35 PM PDT 24 |
| Finished | Aug 07 04:25:30 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-cf6c6fed-192d-43aa-b55a-45cc1c11120f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613283100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1613283100 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2144332424 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14245740000 ps |
| CPU time | 51.71 seconds |
| Started | Aug 07 04:22:19 PM PDT 24 |
| Finished | Aug 07 04:23:56 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-4fe7249b-bdf0-44a6-8f33-499feb56753f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144332424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2144332424 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1625343630 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10368260000 ps |
| CPU time | 32.31 seconds |
| Started | Aug 07 04:24:30 PM PDT 24 |
| Finished | Aug 07 04:25:29 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-9f096eb7-5260-49fa-8c0e-27fbbee6fee2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625343630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1625343630 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.846588499 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3845240000 ps |
| CPU time | 15.26 seconds |
| Started | Aug 07 04:24:35 PM PDT 24 |
| Finished | Aug 07 04:25:04 PM PDT 24 |
| Peak memory | 144836 kb |
| Host | smart-3336f927-fc66-4444-b784-40491d1f8452 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=846588499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.846588499 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3443087441 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11085600000 ps |
| CPU time | 34.1 seconds |
| Started | Aug 07 04:24:29 PM PDT 24 |
| Finished | Aug 07 04:25:31 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-fb5ee80d-0b48-41b2-9c70-49a95f82714e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443087441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3443087441 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3590541691 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7464800000 ps |
| CPU time | 27.58 seconds |
| Started | Aug 07 04:24:21 PM PDT 24 |
| Finished | Aug 07 04:25:14 PM PDT 24 |
| Peak memory | 144016 kb |
| Host | smart-be05467e-9616-441d-b845-9bf5c2ae606f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590541691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3590541691 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1810370714 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15467760000 ps |
| CPU time | 52.45 seconds |
| Started | Aug 07 04:24:20 PM PDT 24 |
| Finished | Aug 07 04:25:57 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-b4a206d1-fe16-49a0-9e9e-f6e74cea6a16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1810370714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1810370714 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2985870002 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 14424920000 ps |
| CPU time | 46.07 seconds |
| Started | Aug 07 04:24:19 PM PDT 24 |
| Finished | Aug 07 04:25:44 PM PDT 24 |
| Peak memory | 143880 kb |
| Host | smart-408e1ab8-9bce-4013-9d1b-f9ab4dafc77a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985870002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2985870002 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3823608515 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7252760000 ps |
| CPU time | 25 seconds |
| Started | Aug 07 04:24:25 PM PDT 24 |
| Finished | Aug 07 04:25:11 PM PDT 24 |
| Peak memory | 144172 kb |
| Host | smart-b61a7440-57fd-488c-ae93-30f5a17e69ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823608515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3823608515 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1233282794 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12845160000 ps |
| CPU time | 47.95 seconds |
| Started | Aug 07 04:21:59 PM PDT 24 |
| Finished | Aug 07 04:23:29 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-9832fad7-e594-4ccd-9f0a-3eaabe754f2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233282794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1233282794 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2205234128 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6307880000 ps |
| CPU time | 18.64 seconds |
| Started | Aug 07 04:24:55 PM PDT 24 |
| Finished | Aug 07 04:25:30 PM PDT 24 |
| Peak memory | 144512 kb |
| Host | smart-afa00f73-41f3-4e31-8d62-93696f62f855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205234128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2205234128 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1595871336 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10788620000 ps |
| CPU time | 33.57 seconds |
| Started | Aug 07 04:24:48 PM PDT 24 |
| Finished | Aug 07 04:25:50 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-67e31d3d-a739-4ef2-82e1-fc12c9a62945 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1595871336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1595871336 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2334956607 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4764700000 ps |
| CPU time | 18.08 seconds |
| Started | Aug 07 04:20:29 PM PDT 24 |
| Finished | Aug 07 04:21:02 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-5a8ba409-a4fd-46bc-965c-bfcd1e9c5c91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334956607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2334956607 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.39793221 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 15402040000 ps |
| CPU time | 57.03 seconds |
| Started | Aug 07 04:19:36 PM PDT 24 |
| Finished | Aug 07 04:21:24 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-7e95ab88-9db6-4e3f-b5c0-617f26ae0264 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39793221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.39793221 |
| Directory | /workspace/9.prim_present_test/latest |
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