| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.3173990501 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3514515830 |
| /workspace/coverage/default/1.prim_present_test.3030458524 |
| /workspace/coverage/default/11.prim_present_test.3291941315 |
| /workspace/coverage/default/12.prim_present_test.518326678 |
| /workspace/coverage/default/13.prim_present_test.623685953 |
| /workspace/coverage/default/14.prim_present_test.3988373536 |
| /workspace/coverage/default/15.prim_present_test.3580110028 |
| /workspace/coverage/default/16.prim_present_test.1276393829 |
| /workspace/coverage/default/17.prim_present_test.3723528022 |
| /workspace/coverage/default/18.prim_present_test.1444149937 |
| /workspace/coverage/default/19.prim_present_test.3026739561 |
| /workspace/coverage/default/2.prim_present_test.4231298491 |
| /workspace/coverage/default/20.prim_present_test.2211570497 |
| /workspace/coverage/default/21.prim_present_test.3144771807 |
| /workspace/coverage/default/22.prim_present_test.1051208716 |
| /workspace/coverage/default/23.prim_present_test.1951594378 |
| /workspace/coverage/default/24.prim_present_test.139139746 |
| /workspace/coverage/default/25.prim_present_test.1256417307 |
| /workspace/coverage/default/26.prim_present_test.2800950069 |
| /workspace/coverage/default/27.prim_present_test.2146659355 |
| /workspace/coverage/default/28.prim_present_test.2917468845 |
| /workspace/coverage/default/29.prim_present_test.1024793740 |
| /workspace/coverage/default/3.prim_present_test.2127018407 |
| /workspace/coverage/default/30.prim_present_test.3493041365 |
| /workspace/coverage/default/31.prim_present_test.623102840 |
| /workspace/coverage/default/32.prim_present_test.2452963915 |
| /workspace/coverage/default/33.prim_present_test.3915820685 |
| /workspace/coverage/default/34.prim_present_test.1519287643 |
| /workspace/coverage/default/35.prim_present_test.70846780 |
| /workspace/coverage/default/36.prim_present_test.392199791 |
| /workspace/coverage/default/37.prim_present_test.1112075737 |
| /workspace/coverage/default/38.prim_present_test.628762460 |
| /workspace/coverage/default/39.prim_present_test.378864321 |
| /workspace/coverage/default/4.prim_present_test.2693927342 |
| /workspace/coverage/default/40.prim_present_test.904557144 |
| /workspace/coverage/default/41.prim_present_test.2071996685 |
| /workspace/coverage/default/42.prim_present_test.1853460867 |
| /workspace/coverage/default/43.prim_present_test.1963667166 |
| /workspace/coverage/default/44.prim_present_test.1588866749 |
| /workspace/coverage/default/45.prim_present_test.2078621211 |
| /workspace/coverage/default/46.prim_present_test.1542979178 |
| /workspace/coverage/default/47.prim_present_test.3608453553 |
| /workspace/coverage/default/48.prim_present_test.407224945 |
| /workspace/coverage/default/49.prim_present_test.2302297356 |
| /workspace/coverage/default/5.prim_present_test.3441810304 |
| /workspace/coverage/default/6.prim_present_test.3935791291 |
| /workspace/coverage/default/7.prim_present_test.4069332 |
| /workspace/coverage/default/8.prim_present_test.572146889 |
| /workspace/coverage/default/9.prim_present_test.2720474498 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_present_test.1444149937 | Aug 08 05:04:56 PM PDT 24 | Aug 08 05:06:24 PM PDT 24 | 14664240000 ps | ||
| T2 | /workspace/coverage/default/17.prim_present_test.3723528022 | Aug 08 05:04:57 PM PDT 24 | Aug 08 05:05:50 PM PDT 24 | 7514400000 ps | ||
| T3 | /workspace/coverage/default/24.prim_present_test.139139746 | Aug 08 05:04:56 PM PDT 24 | Aug 08 05:05:17 PM PDT 24 | 3329400000 ps | ||
| T4 | /workspace/coverage/default/40.prim_present_test.904557144 | Aug 08 05:04:51 PM PDT 24 | Aug 08 05:06:09 PM PDT 24 | 12267320000 ps | ||
| T5 | /workspace/coverage/default/31.prim_present_test.623102840 | Aug 08 05:05:02 PM PDT 24 | Aug 08 05:05:30 PM PDT 24 | 4465240000 ps | ||
| T6 | /workspace/coverage/default/33.prim_present_test.3915820685 | Aug 08 05:04:56 PM PDT 24 | Aug 08 05:06:23 PM PDT 24 | 13847080000 ps | ||
| T7 | /workspace/coverage/default/6.prim_present_test.3935791291 | Aug 08 05:04:58 PM PDT 24 | Aug 08 05:06:06 PM PDT 24 | 8878400000 ps | ||
| T8 | /workspace/coverage/default/2.prim_present_test.4231298491 | Aug 08 05:05:00 PM PDT 24 | Aug 08 05:06:22 PM PDT 24 | 10734060000 ps | ||
| T9 | /workspace/coverage/default/5.prim_present_test.3441810304 | Aug 08 05:05:06 PM PDT 24 | Aug 08 05:06:21 PM PDT 24 | 11815960000 ps | ||
| T10 | /workspace/coverage/default/10.prim_present_test.3173990501 | Aug 08 05:05:04 PM PDT 24 | Aug 08 05:06:31 PM PDT 24 | 13314500000 ps | ||
| T11 | /workspace/coverage/default/28.prim_present_test.2917468845 | Aug 08 05:04:40 PM PDT 24 | Aug 08 05:05:37 PM PDT 24 | 7830600000 ps | ||
| T12 | /workspace/coverage/default/29.prim_present_test.1024793740 | Aug 08 05:04:55 PM PDT 24 | Aug 08 05:06:17 PM PDT 24 | 11698780000 ps | ||
| T13 | /workspace/coverage/default/39.prim_present_test.378864321 | Aug 08 05:04:47 PM PDT 24 | Aug 08 05:05:14 PM PDT 24 | 3952500000 ps | ||
| T14 | /workspace/coverage/default/16.prim_present_test.1276393829 | Aug 08 05:05:06 PM PDT 24 | Aug 08 05:05:39 PM PDT 24 | 4916600000 ps | ||
| T15 | /workspace/coverage/default/46.prim_present_test.1542979178 | Aug 08 05:05:05 PM PDT 24 | Aug 08 05:06:13 PM PDT 24 | 9707340000 ps | ||
| T16 | /workspace/coverage/default/38.prim_present_test.628762460 | Aug 08 05:04:52 PM PDT 24 | Aug 08 05:05:38 PM PDT 24 | 8024040000 ps | ||
| T17 | /workspace/coverage/default/41.prim_present_test.2071996685 | Aug 08 05:05:00 PM PDT 24 | Aug 08 05:06:16 PM PDT 24 | 11276560000 ps | ||
| T18 | /workspace/coverage/default/44.prim_present_test.1588866749 | Aug 08 05:04:57 PM PDT 24 | Aug 08 05:06:00 PM PDT 24 | 9461820000 ps | ||
| T19 | /workspace/coverage/default/45.prim_present_test.2078621211 | Aug 08 05:04:46 PM PDT 24 | Aug 08 05:06:33 PM PDT 24 | 15379100000 ps | ||
| T20 | /workspace/coverage/default/8.prim_present_test.572146889 | Aug 08 05:04:46 PM PDT 24 | Aug 08 05:05:33 PM PDT 24 | 7260820000 ps | ||
| T21 | /workspace/coverage/default/13.prim_present_test.623685953 | Aug 08 05:04:58 PM PDT 24 | Aug 08 05:06:32 PM PDT 24 | 13697040000 ps | ||
| T22 | /workspace/coverage/default/48.prim_present_test.407224945 | Aug 08 05:04:45 PM PDT 24 | Aug 08 05:05:24 PM PDT 24 | 5495060000 ps | ||
| T23 | /workspace/coverage/default/42.prim_present_test.1853460867 | Aug 08 05:04:48 PM PDT 24 | Aug 08 05:05:26 PM PDT 24 | 6301680000 ps | ||
| T24 | /workspace/coverage/default/34.prim_present_test.1519287643 | Aug 08 05:04:53 PM PDT 24 | Aug 08 05:05:57 PM PDT 24 | 9745160000 ps | ||
| T25 | /workspace/coverage/default/15.prim_present_test.3580110028 | Aug 08 05:05:06 PM PDT 24 | Aug 08 05:05:54 PM PDT 24 | 6738160000 ps | ||
| T26 | /workspace/coverage/default/9.prim_present_test.2720474498 | Aug 08 05:04:56 PM PDT 24 | Aug 08 05:06:29 PM PDT 24 | 11752720000 ps | ||
| T27 | /workspace/coverage/default/27.prim_present_test.2146659355 | Aug 08 05:04:44 PM PDT 24 | Aug 08 05:05:44 PM PDT 24 | 10109720000 ps | ||
| T28 | /workspace/coverage/default/30.prim_present_test.3493041365 | Aug 08 05:04:50 PM PDT 24 | Aug 08 05:05:13 PM PDT 24 | 3972340000 ps | ||
| T29 | /workspace/coverage/default/25.prim_present_test.1256417307 | Aug 08 05:04:44 PM PDT 24 | Aug 08 05:05:55 PM PDT 24 | 10747080000 ps | ||
| T30 | /workspace/coverage/default/49.prim_present_test.2302297356 | Aug 08 05:05:00 PM PDT 24 | Aug 08 05:05:29 PM PDT 24 | 3517260000 ps | ||
| T31 | /workspace/coverage/default/32.prim_present_test.2452963915 | Aug 08 05:04:41 PM PDT 24 | Aug 08 05:05:14 PM PDT 24 | 4479500000 ps | ||
| T32 | /workspace/coverage/default/35.prim_present_test.70846780 | Aug 08 05:05:09 PM PDT 24 | Aug 08 05:06:32 PM PDT 24 | 13216540000 ps | ||
| T33 | /workspace/coverage/default/37.prim_present_test.1112075737 | Aug 08 05:04:48 PM PDT 24 | Aug 08 05:06:33 PM PDT 24 | 14452200000 ps | ||
| T34 | /workspace/coverage/default/0.prim_present_test.3514515830 | Aug 08 05:04:59 PM PDT 24 | Aug 08 05:06:29 PM PDT 24 | 13966120000 ps | ||
| T35 | /workspace/coverage/default/23.prim_present_test.1951594378 | Aug 08 05:04:52 PM PDT 24 | Aug 08 05:05:18 PM PDT 24 | 3664200000 ps | ||
| T36 | /workspace/coverage/default/43.prim_present_test.1963667166 | Aug 08 05:05:01 PM PDT 24 | Aug 08 05:06:34 PM PDT 24 | 14361060000 ps | ||
| T37 | /workspace/coverage/default/26.prim_present_test.2800950069 | Aug 08 05:04:47 PM PDT 24 | Aug 08 05:05:18 PM PDT 24 | 4871960000 ps | ||
| T38 | /workspace/coverage/default/12.prim_present_test.518326678 | Aug 08 05:05:00 PM PDT 24 | Aug 08 05:06:35 PM PDT 24 | 15070340000 ps | ||
| T39 | /workspace/coverage/default/36.prim_present_test.392199791 | Aug 08 05:04:54 PM PDT 24 | Aug 08 05:06:08 PM PDT 24 | 9188400000 ps | ||
| T40 | /workspace/coverage/default/1.prim_present_test.3030458524 | Aug 08 05:04:57 PM PDT 24 | Aug 08 05:06:30 PM PDT 24 | 13863820000 ps | ||
| T41 | /workspace/coverage/default/11.prim_present_test.3291941315 | Aug 08 05:04:59 PM PDT 24 | Aug 08 05:06:17 PM PDT 24 | 12236320000 ps | ||
| T42 | /workspace/coverage/default/3.prim_present_test.2127018407 | Aug 08 05:05:01 PM PDT 24 | Aug 08 05:05:32 PM PDT 24 | 4469580000 ps | ||
| T43 | /workspace/coverage/default/7.prim_present_test.4069332 | Aug 08 05:04:53 PM PDT 24 | Aug 08 05:06:24 PM PDT 24 | 13029920000 ps | ||
| T44 | /workspace/coverage/default/4.prim_present_test.2693927342 | Aug 08 05:05:03 PM PDT 24 | Aug 08 05:06:13 PM PDT 24 | 11091800000 ps | ||
| T45 | /workspace/coverage/default/19.prim_present_test.3026739561 | Aug 08 05:04:54 PM PDT 24 | Aug 08 05:05:39 PM PDT 24 | 6806980000 ps | ||
| T46 | /workspace/coverage/default/47.prim_present_test.3608453553 | Aug 08 05:04:55 PM PDT 24 | Aug 08 05:05:47 PM PDT 24 | 6485200000 ps | ||
| T47 | /workspace/coverage/default/14.prim_present_test.3988373536 | Aug 08 05:04:58 PM PDT 24 | Aug 08 05:06:29 PM PDT 24 | 12884220000 ps | ||
| T48 | /workspace/coverage/default/22.prim_present_test.1051208716 | Aug 08 05:04:45 PM PDT 24 | Aug 08 05:05:52 PM PDT 24 | 9575900000 ps | ||
| T49 | /workspace/coverage/default/21.prim_present_test.3144771807 | Aug 08 05:04:46 PM PDT 24 | Aug 08 05:05:39 PM PDT 24 | 8095960000 ps | ||
| T50 | /workspace/coverage/default/20.prim_present_test.2211570497 | Aug 08 05:04:46 PM PDT 24 | Aug 08 05:05:59 PM PDT 24 | 9742060000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.3173990501 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13314500000 ps |
| CPU time | 45.88 seconds |
| Started | Aug 08 05:05:04 PM PDT 24 |
| Finished | Aug 08 05:06:31 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-fff1d422-b770-418c-bf3e-1e071bce0f66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173990501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3173990501 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3514515830 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13966120000 ps |
| CPU time | 48.03 seconds |
| Started | Aug 08 05:04:59 PM PDT 24 |
| Finished | Aug 08 05:06:29 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-8b42f439-3a10-4eae-87be-3233d18b2eb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514515830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3514515830 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3030458524 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13863820000 ps |
| CPU time | 48.76 seconds |
| Started | Aug 08 05:04:57 PM PDT 24 |
| Finished | Aug 08 05:06:30 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-5db2ae3b-de84-4774-ae08-edeae125f754 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3030458524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3030458524 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3291941315 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12236320000 ps |
| CPU time | 41.31 seconds |
| Started | Aug 08 05:04:59 PM PDT 24 |
| Finished | Aug 08 05:06:17 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-e315677d-6deb-4198-b673-41b48e6a554a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291941315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3291941315 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.518326678 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 15070340000 ps |
| CPU time | 50.38 seconds |
| Started | Aug 08 05:05:00 PM PDT 24 |
| Finished | Aug 08 05:06:35 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-3ac1c9a8-ba07-417c-bc53-951df3fc774c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=518326678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.518326678 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.623685953 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13697040000 ps |
| CPU time | 48.74 seconds |
| Started | Aug 08 05:04:58 PM PDT 24 |
| Finished | Aug 08 05:06:32 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-5942a457-55f5-405e-a0a6-9827060dbe8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623685953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.623685953 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3988373536 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12884220000 ps |
| CPU time | 47.16 seconds |
| Started | Aug 08 05:04:58 PM PDT 24 |
| Finished | Aug 08 05:06:29 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-20fbfce6-6548-420a-a664-0ac73d8994ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3988373536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3988373536 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3580110028 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6738160000 ps |
| CPU time | 25.54 seconds |
| Started | Aug 08 05:05:06 PM PDT 24 |
| Finished | Aug 08 05:05:54 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-158deb54-259f-4d9f-b542-51cc3829b5b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580110028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3580110028 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1276393829 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4916600000 ps |
| CPU time | 17.35 seconds |
| Started | Aug 08 05:05:06 PM PDT 24 |
| Finished | Aug 08 05:05:39 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-b03f2051-4ac5-415d-89a9-4397b262d5dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276393829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1276393829 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3723528022 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7514400000 ps |
| CPU time | 28.27 seconds |
| Started | Aug 08 05:04:57 PM PDT 24 |
| Finished | Aug 08 05:05:50 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-3f7fc9a3-fae2-486e-873e-0f0365ac6625 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723528022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3723528022 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1444149937 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14664240000 ps |
| CPU time | 46.93 seconds |
| Started | Aug 08 05:04:56 PM PDT 24 |
| Finished | Aug 08 05:06:24 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-b3e64c3e-ebd7-4354-bef0-952950a596e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1444149937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1444149937 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3026739561 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6806980000 ps |
| CPU time | 24.18 seconds |
| Started | Aug 08 05:04:54 PM PDT 24 |
| Finished | Aug 08 05:05:39 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-c3c3e516-5751-4621-b80e-89a0de7446a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026739561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3026739561 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4231298491 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10734060000 ps |
| CPU time | 43 seconds |
| Started | Aug 08 05:05:00 PM PDT 24 |
| Finished | Aug 08 05:06:22 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-6109124e-6784-45af-9468-fecc4a2d77f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231298491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4231298491 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2211570497 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 9742060000 ps |
| CPU time | 37.99 seconds |
| Started | Aug 08 05:04:46 PM PDT 24 |
| Finished | Aug 08 05:05:59 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-dde5c069-1e0c-4e7c-afae-45078b4cc3c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211570497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2211570497 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3144771807 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8095960000 ps |
| CPU time | 28.38 seconds |
| Started | Aug 08 05:04:46 PM PDT 24 |
| Finished | Aug 08 05:05:39 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-ddf5cd0c-4dd1-4186-8f81-421ed48797e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3144771807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3144771807 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1051208716 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9575900000 ps |
| CPU time | 35.62 seconds |
| Started | Aug 08 05:04:45 PM PDT 24 |
| Finished | Aug 08 05:05:52 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-749abe7c-f6f6-49e4-991d-98ebca2e7c61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051208716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1051208716 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1951594378 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3664200000 ps |
| CPU time | 14.02 seconds |
| Started | Aug 08 05:04:52 PM PDT 24 |
| Finished | Aug 08 05:05:18 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-c6085fbf-3e06-4f23-82e2-6df37c9e375a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951594378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1951594378 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.139139746 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3329400000 ps |
| CPU time | 11.17 seconds |
| Started | Aug 08 05:04:56 PM PDT 24 |
| Finished | Aug 08 05:05:17 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-978dd5eb-4aa3-416a-a433-087baf7933bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=139139746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.139139746 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1256417307 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10747080000 ps |
| CPU time | 37.28 seconds |
| Started | Aug 08 05:04:44 PM PDT 24 |
| Finished | Aug 08 05:05:55 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-886775cd-6cd0-4227-affc-f29862f71e15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1256417307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1256417307 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2800950069 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4871960000 ps |
| CPU time | 16.41 seconds |
| Started | Aug 08 05:04:47 PM PDT 24 |
| Finished | Aug 08 05:05:18 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-3962a2c7-9289-429e-a7e8-b3e3246f1a01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800950069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2800950069 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2146659355 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10109720000 ps |
| CPU time | 32.37 seconds |
| Started | Aug 08 05:04:44 PM PDT 24 |
| Finished | Aug 08 05:05:44 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-84e33d40-d039-48e6-8fde-902b3d3de278 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146659355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2146659355 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2917468845 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7830600000 ps |
| CPU time | 29.93 seconds |
| Started | Aug 08 05:04:40 PM PDT 24 |
| Finished | Aug 08 05:05:37 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-7eaa5441-7a64-4bc6-92eb-89f96fa891bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917468845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2917468845 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1024793740 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11698780000 ps |
| CPU time | 43.7 seconds |
| Started | Aug 08 05:04:55 PM PDT 24 |
| Finished | Aug 08 05:06:17 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-bd6ceeca-c1a1-4ce1-8d2e-8e99be62c842 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024793740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1024793740 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2127018407 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4469580000 ps |
| CPU time | 16.25 seconds |
| Started | Aug 08 05:05:01 PM PDT 24 |
| Finished | Aug 08 05:05:32 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-493c1ce2-d38b-4af1-acf8-1a985c0ee42d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127018407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2127018407 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3493041365 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3972340000 ps |
| CPU time | 12.33 seconds |
| Started | Aug 08 05:04:50 PM PDT 24 |
| Finished | Aug 08 05:05:13 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-b1bc4758-c73c-4efb-8058-bd6ab6be2ede |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493041365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3493041365 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.623102840 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4465240000 ps |
| CPU time | 15.34 seconds |
| Started | Aug 08 05:05:02 PM PDT 24 |
| Finished | Aug 08 05:05:30 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-3b7dd61b-9c3f-479b-9902-761b9e692337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623102840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.623102840 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2452963915 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4479500000 ps |
| CPU time | 17.32 seconds |
| Started | Aug 08 05:04:41 PM PDT 24 |
| Finished | Aug 08 05:05:14 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-fac590db-568c-45bb-bd0f-81a824a853cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452963915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2452963915 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3915820685 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13847080000 ps |
| CPU time | 46.7 seconds |
| Started | Aug 08 05:04:56 PM PDT 24 |
| Finished | Aug 08 05:06:23 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-502ed08b-2409-4587-8752-0bc1f901e167 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915820685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3915820685 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1519287643 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9745160000 ps |
| CPU time | 34.3 seconds |
| Started | Aug 08 05:04:53 PM PDT 24 |
| Finished | Aug 08 05:05:57 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-3b631c96-3f3b-483a-98bc-87cd4c536a83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519287643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1519287643 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.70846780 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13216540000 ps |
| CPU time | 44.74 seconds |
| Started | Aug 08 05:05:09 PM PDT 24 |
| Finished | Aug 08 05:06:32 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-1d2f04e8-ea75-4f9e-93f0-3bd03fe75c13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70846780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.70846780 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.392199791 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9188400000 ps |
| CPU time | 38.45 seconds |
| Started | Aug 08 05:04:54 PM PDT 24 |
| Finished | Aug 08 05:06:08 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-f4d8fa2c-be66-48d6-b77c-04b02a29fb30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392199791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.392199791 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1112075737 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14452200000 ps |
| CPU time | 54.64 seconds |
| Started | Aug 08 05:04:48 PM PDT 24 |
| Finished | Aug 08 05:06:33 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-d3e78504-7831-4449-ac1c-565a1f224c87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112075737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1112075737 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.628762460 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8024040000 ps |
| CPU time | 25.27 seconds |
| Started | Aug 08 05:04:52 PM PDT 24 |
| Finished | Aug 08 05:05:38 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-6e3ac496-e565-47b6-b7c0-b43ebfb637f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628762460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.628762460 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.378864321 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3952500000 ps |
| CPU time | 14.63 seconds |
| Started | Aug 08 05:04:47 PM PDT 24 |
| Finished | Aug 08 05:05:14 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-5cfb36e9-9540-45dd-ae18-653b7c471f32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378864321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.378864321 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2693927342 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11091800000 ps |
| CPU time | 37.58 seconds |
| Started | Aug 08 05:05:03 PM PDT 24 |
| Finished | Aug 08 05:06:13 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-9cbca025-6e78-450b-a870-e907bd905267 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693927342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2693927342 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.904557144 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12267320000 ps |
| CPU time | 41.55 seconds |
| Started | Aug 08 05:04:51 PM PDT 24 |
| Finished | Aug 08 05:06:09 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-ccc15bfa-b53a-42b8-a9af-8c70d7972a33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=904557144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.904557144 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2071996685 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11276560000 ps |
| CPU time | 40.06 seconds |
| Started | Aug 08 05:05:00 PM PDT 24 |
| Finished | Aug 08 05:06:16 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-b6b2d34d-8e7e-4f10-8430-22ebb6a0c189 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071996685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2071996685 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1853460867 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6301680000 ps |
| CPU time | 20.58 seconds |
| Started | Aug 08 05:04:48 PM PDT 24 |
| Finished | Aug 08 05:05:26 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-70ac03b4-d62a-456e-b72c-794da5c8535f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853460867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1853460867 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1963667166 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14361060000 ps |
| CPU time | 49.62 seconds |
| Started | Aug 08 05:05:01 PM PDT 24 |
| Finished | Aug 08 05:06:34 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-07014195-a8b6-453f-8ab6-7cc63b8eadd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963667166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1963667166 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1588866749 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9461820000 ps |
| CPU time | 32.99 seconds |
| Started | Aug 08 05:04:57 PM PDT 24 |
| Finished | Aug 08 05:06:00 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-043297d3-a8cd-4b8a-9147-88ee054ef047 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1588866749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1588866749 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2078621211 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 15379100000 ps |
| CPU time | 56.44 seconds |
| Started | Aug 08 05:04:46 PM PDT 24 |
| Finished | Aug 08 05:06:33 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-8fb69141-a8e3-4071-97ea-4f410b7e0d9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078621211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2078621211 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1542979178 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9707340000 ps |
| CPU time | 35.66 seconds |
| Started | Aug 08 05:05:05 PM PDT 24 |
| Finished | Aug 08 05:06:13 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-0fd0bbc6-d637-4362-a523-138a0cefca4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1542979178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1542979178 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3608453553 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6485200000 ps |
| CPU time | 26.88 seconds |
| Started | Aug 08 05:04:55 PM PDT 24 |
| Finished | Aug 08 05:05:47 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-177650ca-1837-4fbd-abc3-6d8eb3a664a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608453553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3608453553 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.407224945 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5495060000 ps |
| CPU time | 20.19 seconds |
| Started | Aug 08 05:04:45 PM PDT 24 |
| Finished | Aug 08 05:05:24 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-1e618d4a-22a0-4843-b8d6-8b6da4fe3869 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407224945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.407224945 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2302297356 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3517260000 ps |
| CPU time | 14.93 seconds |
| Started | Aug 08 05:05:00 PM PDT 24 |
| Finished | Aug 08 05:05:29 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-296ae7e9-2e08-4588-a80b-63c9ee51f0b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302297356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2302297356 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3441810304 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11815960000 ps |
| CPU time | 39.79 seconds |
| Started | Aug 08 05:05:06 PM PDT 24 |
| Finished | Aug 08 05:06:21 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-a2ebb640-de52-4818-b680-88aa37c15aec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3441810304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3441810304 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3935791291 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8878400000 ps |
| CPU time | 35.57 seconds |
| Started | Aug 08 05:04:58 PM PDT 24 |
| Finished | Aug 08 05:06:06 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-cfbb8bd6-7a94-4c9f-89c1-4f1a58d729f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935791291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3935791291 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.4069332 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13029920000 ps |
| CPU time | 47.18 seconds |
| Started | Aug 08 05:04:53 PM PDT 24 |
| Finished | Aug 08 05:06:24 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-6f559943-8228-4e7c-a5bf-bab70d151799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4069332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.4069332 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.572146889 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7260820000 ps |
| CPU time | 24.62 seconds |
| Started | Aug 08 05:04:46 PM PDT 24 |
| Finished | Aug 08 05:05:33 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-592949ae-48b4-4d98-ab87-94b8900e6ad2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572146889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.572146889 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2720474498 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11752720000 ps |
| CPU time | 48.41 seconds |
| Started | Aug 08 05:04:56 PM PDT 24 |
| Finished | Aug 08 05:06:29 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-5af54f5b-2a30-4473-9236-adaa79245834 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720474498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2720474498 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |