| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2115850362 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.1134926919 |
| /workspace/coverage/default/10.prim_present_test.1391384139 |
| /workspace/coverage/default/11.prim_present_test.3975521806 |
| /workspace/coverage/default/12.prim_present_test.4005676934 |
| /workspace/coverage/default/13.prim_present_test.2281266264 |
| /workspace/coverage/default/14.prim_present_test.393465374 |
| /workspace/coverage/default/15.prim_present_test.3588204701 |
| /workspace/coverage/default/16.prim_present_test.1052958453 |
| /workspace/coverage/default/17.prim_present_test.978255476 |
| /workspace/coverage/default/18.prim_present_test.3489943704 |
| /workspace/coverage/default/19.prim_present_test.1632460105 |
| /workspace/coverage/default/2.prim_present_test.830525120 |
| /workspace/coverage/default/20.prim_present_test.1145799528 |
| /workspace/coverage/default/21.prim_present_test.3603795594 |
| /workspace/coverage/default/22.prim_present_test.1888929788 |
| /workspace/coverage/default/23.prim_present_test.3878476772 |
| /workspace/coverage/default/24.prim_present_test.895038308 |
| /workspace/coverage/default/25.prim_present_test.4166190404 |
| /workspace/coverage/default/26.prim_present_test.4019151022 |
| /workspace/coverage/default/27.prim_present_test.967411395 |
| /workspace/coverage/default/28.prim_present_test.2801797042 |
| /workspace/coverage/default/29.prim_present_test.3954122428 |
| /workspace/coverage/default/3.prim_present_test.1493780169 |
| /workspace/coverage/default/30.prim_present_test.37586325 |
| /workspace/coverage/default/31.prim_present_test.3501344718 |
| /workspace/coverage/default/32.prim_present_test.734929995 |
| /workspace/coverage/default/33.prim_present_test.2028768665 |
| /workspace/coverage/default/34.prim_present_test.345552804 |
| /workspace/coverage/default/35.prim_present_test.2921303721 |
| /workspace/coverage/default/36.prim_present_test.3828209922 |
| /workspace/coverage/default/37.prim_present_test.1854204218 |
| /workspace/coverage/default/38.prim_present_test.335710957 |
| /workspace/coverage/default/39.prim_present_test.605109519 |
| /workspace/coverage/default/4.prim_present_test.1053476652 |
| /workspace/coverage/default/40.prim_present_test.387142354 |
| /workspace/coverage/default/41.prim_present_test.1191515774 |
| /workspace/coverage/default/42.prim_present_test.3064436682 |
| /workspace/coverage/default/43.prim_present_test.515307800 |
| /workspace/coverage/default/44.prim_present_test.2055392715 |
| /workspace/coverage/default/45.prim_present_test.155159124 |
| /workspace/coverage/default/46.prim_present_test.3999874933 |
| /workspace/coverage/default/47.prim_present_test.3114420773 |
| /workspace/coverage/default/48.prim_present_test.1627774571 |
| /workspace/coverage/default/49.prim_present_test.2471826117 |
| /workspace/coverage/default/5.prim_present_test.1036644299 |
| /workspace/coverage/default/6.prim_present_test.2251794873 |
| /workspace/coverage/default/7.prim_present_test.765898274 |
| /workspace/coverage/default/8.prim_present_test.3409049740 |
| /workspace/coverage/default/9.prim_present_test.3909115295 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/32.prim_present_test.734929995 | Aug 09 06:35:45 PM PDT 24 | Aug 09 06:37:31 PM PDT 24 | 15044300000 ps | ||
| T2 | /workspace/coverage/default/48.prim_present_test.1627774571 | Aug 09 06:35:55 PM PDT 24 | Aug 09 06:37:36 PM PDT 24 | 14649980000 ps | ||
| T3 | /workspace/coverage/default/14.prim_present_test.393465374 | Aug 09 06:35:37 PM PDT 24 | Aug 09 06:36:34 PM PDT 24 | 7495800000 ps | ||
| T4 | /workspace/coverage/default/47.prim_present_test.3114420773 | Aug 09 06:35:55 PM PDT 24 | Aug 09 06:37:27 PM PDT 24 | 12032340000 ps | ||
| T5 | /workspace/coverage/default/23.prim_present_test.3878476772 | Aug 09 06:35:45 PM PDT 24 | Aug 09 06:37:44 PM PDT 24 | 15176360000 ps | ||
| T6 | /workspace/coverage/default/5.prim_present_test.1036644299 | Aug 09 06:35:34 PM PDT 24 | Aug 09 06:36:54 PM PDT 24 | 12052800000 ps | ||
| T7 | /workspace/coverage/default/13.prim_present_test.2281266264 | Aug 09 06:35:35 PM PDT 24 | Aug 09 06:36:15 PM PDT 24 | 5895580000 ps | ||
| T8 | /workspace/coverage/default/24.prim_present_test.895038308 | Aug 09 06:35:47 PM PDT 24 | Aug 09 06:36:17 PM PDT 24 | 4109360000 ps | ||
| T9 | /workspace/coverage/default/0.prim_present_test.2115850362 | Aug 09 06:35:27 PM PDT 24 | Aug 09 06:36:50 PM PDT 24 | 12018080000 ps | ||
| T10 | /workspace/coverage/default/25.prim_present_test.4166190404 | Aug 09 06:35:46 PM PDT 24 | Aug 09 06:37:25 PM PDT 24 | 15114980000 ps | ||
| T11 | /workspace/coverage/default/1.prim_present_test.1134926919 | Aug 09 06:35:26 PM PDT 24 | Aug 09 06:35:49 PM PDT 24 | 3135340000 ps | ||
| T12 | /workspace/coverage/default/6.prim_present_test.2251794873 | Aug 09 06:35:35 PM PDT 24 | Aug 09 06:36:37 PM PDT 24 | 7983120000 ps | ||
| T13 | /workspace/coverage/default/45.prim_present_test.155159124 | Aug 09 06:35:59 PM PDT 24 | Aug 09 06:36:20 PM PDT 24 | 3689620000 ps | ||
| T14 | /workspace/coverage/default/44.prim_present_test.2055392715 | Aug 09 06:36:00 PM PDT 24 | Aug 09 06:37:01 PM PDT 24 | 8511980000 ps | ||
| T15 | /workspace/coverage/default/9.prim_present_test.3909115295 | Aug 09 06:35:36 PM PDT 24 | Aug 09 06:36:59 PM PDT 24 | 9768100000 ps | ||
| T16 | /workspace/coverage/default/36.prim_present_test.3828209922 | Aug 09 06:35:47 PM PDT 24 | Aug 09 06:37:28 PM PDT 24 | 15319580000 ps | ||
| T17 | /workspace/coverage/default/38.prim_present_test.335710957 | Aug 09 06:35:56 PM PDT 24 | Aug 09 06:36:50 PM PDT 24 | 9433920000 ps | ||
| T18 | /workspace/coverage/default/46.prim_present_test.3999874933 | Aug 09 06:35:56 PM PDT 24 | Aug 09 06:37:22 PM PDT 24 | 9412840000 ps | ||
| T19 | /workspace/coverage/default/49.prim_present_test.2471826117 | Aug 09 06:35:57 PM PDT 24 | Aug 09 06:37:37 PM PDT 24 | 14117400000 ps | ||
| T20 | /workspace/coverage/default/20.prim_present_test.1145799528 | Aug 09 06:35:46 PM PDT 24 | Aug 09 06:36:40 PM PDT 24 | 8585140000 ps | ||
| T21 | /workspace/coverage/default/43.prim_present_test.515307800 | Aug 09 06:35:54 PM PDT 24 | Aug 09 06:36:25 PM PDT 24 | 3450920000 ps | ||
| T22 | /workspace/coverage/default/42.prim_present_test.3064436682 | Aug 09 06:35:57 PM PDT 24 | Aug 09 06:37:09 PM PDT 24 | 12625060000 ps | ||
| T23 | /workspace/coverage/default/19.prim_present_test.1632460105 | Aug 09 06:35:38 PM PDT 24 | Aug 09 06:36:55 PM PDT 24 | 14062220000 ps | ||
| T24 | /workspace/coverage/default/28.prim_present_test.2801797042 | Aug 09 06:35:45 PM PDT 24 | Aug 09 06:36:20 PM PDT 24 | 6606720000 ps | ||
| T25 | /workspace/coverage/default/31.prim_present_test.3501344718 | Aug 09 06:35:46 PM PDT 24 | Aug 09 06:36:53 PM PDT 24 | 8374340000 ps | ||
| T26 | /workspace/coverage/default/39.prim_present_test.605109519 | Aug 09 06:35:55 PM PDT 24 | Aug 09 06:36:31 PM PDT 24 | 5127400000 ps | ||
| T27 | /workspace/coverage/default/34.prim_present_test.345552804 | Aug 09 06:35:45 PM PDT 24 | Aug 09 06:37:06 PM PDT 24 | 12216480000 ps | ||
| T28 | /workspace/coverage/default/12.prim_present_test.4005676934 | Aug 09 06:35:36 PM PDT 24 | Aug 09 06:36:44 PM PDT 24 | 9507700000 ps | ||
| T29 | /workspace/coverage/default/30.prim_present_test.37586325 | Aug 09 06:35:46 PM PDT 24 | Aug 09 06:37:19 PM PDT 24 | 10873560000 ps | ||
| T30 | /workspace/coverage/default/3.prim_present_test.1493780169 | Aug 09 06:35:27 PM PDT 24 | Aug 09 06:35:50 PM PDT 24 | 3693960000 ps | ||
| T31 | /workspace/coverage/default/10.prim_present_test.1391384139 | Aug 09 06:35:35 PM PDT 24 | Aug 09 06:36:22 PM PDT 24 | 7420160000 ps | ||
| T32 | /workspace/coverage/default/41.prim_present_test.1191515774 | Aug 09 06:35:54 PM PDT 24 | Aug 09 06:37:37 PM PDT 24 | 13964880000 ps | ||
| T33 | /workspace/coverage/default/33.prim_present_test.2028768665 | Aug 09 06:35:47 PM PDT 24 | Aug 09 06:37:40 PM PDT 24 | 14896120000 ps | ||
| T34 | /workspace/coverage/default/37.prim_present_test.1854204218 | Aug 09 06:35:47 PM PDT 24 | Aug 09 06:37:01 PM PDT 24 | 10835740000 ps | ||
| T35 | /workspace/coverage/default/35.prim_present_test.2921303721 | Aug 09 06:35:47 PM PDT 24 | Aug 09 06:37:14 PM PDT 24 | 14653700000 ps | ||
| T36 | /workspace/coverage/default/15.prim_present_test.3588204701 | Aug 09 06:35:34 PM PDT 24 | Aug 09 06:36:16 PM PDT 24 | 6956400000 ps | ||
| T37 | /workspace/coverage/default/16.prim_present_test.1052958453 | Aug 09 06:35:37 PM PDT 24 | Aug 09 06:36:51 PM PDT 24 | 10869840000 ps | ||
| T38 | /workspace/coverage/default/11.prim_present_test.3975521806 | Aug 09 06:35:37 PM PDT 24 | Aug 09 06:37:18 PM PDT 24 | 13464540000 ps | ||
| T39 | /workspace/coverage/default/18.prim_present_test.3489943704 | Aug 09 06:35:36 PM PDT 24 | Aug 09 06:36:27 PM PDT 24 | 8911260000 ps | ||
| T40 | /workspace/coverage/default/27.prim_present_test.967411395 | Aug 09 06:35:46 PM PDT 24 | Aug 09 06:36:54 PM PDT 24 | 9933020000 ps | ||
| T41 | /workspace/coverage/default/17.prim_present_test.978255476 | Aug 09 06:35:36 PM PDT 24 | Aug 09 06:36:14 PM PDT 24 | 4720680000 ps | ||
| T42 | /workspace/coverage/default/40.prim_present_test.387142354 | Aug 09 06:35:57 PM PDT 24 | Aug 09 06:37:09 PM PDT 24 | 12176800000 ps | ||
| T43 | /workspace/coverage/default/22.prim_present_test.1888929788 | Aug 09 06:35:46 PM PDT 24 | Aug 09 06:37:07 PM PDT 24 | 11780000000 ps | ||
| T44 | /workspace/coverage/default/21.prim_present_test.3603795594 | Aug 09 06:35:44 PM PDT 24 | Aug 09 06:37:15 PM PDT 24 | 13044180000 ps | ||
| T45 | /workspace/coverage/default/29.prim_present_test.3954122428 | Aug 09 06:35:46 PM PDT 24 | Aug 09 06:37:27 PM PDT 24 | 14573100000 ps | ||
| T46 | /workspace/coverage/default/8.prim_present_test.3409049740 | Aug 09 06:35:37 PM PDT 24 | Aug 09 06:36:00 PM PDT 24 | 4031240000 ps | ||
| T47 | /workspace/coverage/default/2.prim_present_test.830525120 | Aug 09 06:35:26 PM PDT 24 | Aug 09 06:36:40 PM PDT 24 | 13338060000 ps | ||
| T48 | /workspace/coverage/default/7.prim_present_test.765898274 | Aug 09 06:35:36 PM PDT 24 | Aug 09 06:37:16 PM PDT 24 | 13981620000 ps | ||
| T49 | /workspace/coverage/default/26.prim_present_test.4019151022 | Aug 09 06:35:45 PM PDT 24 | Aug 09 06:37:04 PM PDT 24 | 13114240000 ps | ||
| T50 | /workspace/coverage/default/4.prim_present_test.1053476652 | Aug 09 06:35:37 PM PDT 24 | Aug 09 06:37:14 PM PDT 24 | 12909020000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2115850362 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12018080000 ps |
| CPU time | 43.94 seconds |
| Started | Aug 09 06:35:27 PM PDT 24 |
| Finished | Aug 09 06:36:50 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-47e41391-447c-4dbc-b439-867407e52a3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115850362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2115850362 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1134926919 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3135340000 ps |
| CPU time | 11.87 seconds |
| Started | Aug 09 06:35:26 PM PDT 24 |
| Finished | Aug 09 06:35:49 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-ce0b3f92-ada7-4829-ad9d-5c95251af182 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1134926919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1134926919 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1391384139 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7420160000 ps |
| CPU time | 25.42 seconds |
| Started | Aug 09 06:35:35 PM PDT 24 |
| Finished | Aug 09 06:36:22 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-540a90eb-ec08-4ca1-8010-013e2e3e1960 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391384139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1391384139 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3975521806 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13464540000 ps |
| CPU time | 51.24 seconds |
| Started | Aug 09 06:35:37 PM PDT 24 |
| Finished | Aug 09 06:37:18 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-258adec2-1d20-4fbb-90a3-c4329923ad5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3975521806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3975521806 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4005676934 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9507700000 ps |
| CPU time | 35.97 seconds |
| Started | Aug 09 06:35:36 PM PDT 24 |
| Finished | Aug 09 06:36:44 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-bcb57194-3319-42d2-8d5e-8b21b2987176 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005676934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4005676934 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2281266264 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5895580000 ps |
| CPU time | 21.12 seconds |
| Started | Aug 09 06:35:35 PM PDT 24 |
| Finished | Aug 09 06:36:15 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-ea208852-7a1b-4c8f-944f-6433dabace71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281266264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2281266264 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.393465374 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7495800000 ps |
| CPU time | 28.95 seconds |
| Started | Aug 09 06:35:37 PM PDT 24 |
| Finished | Aug 09 06:36:34 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-ec2f08bd-11f4-46af-b08e-00bb42c1b46a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393465374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.393465374 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3588204701 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6956400000 ps |
| CPU time | 23.07 seconds |
| Started | Aug 09 06:35:34 PM PDT 24 |
| Finished | Aug 09 06:36:16 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-5a912ecf-370b-42d6-8f9c-279885077d70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588204701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3588204701 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1052958453 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10869840000 ps |
| CPU time | 38.52 seconds |
| Started | Aug 09 06:35:37 PM PDT 24 |
| Finished | Aug 09 06:36:51 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-5ce3329b-61e7-4b6a-90a5-6a5ff0535971 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052958453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1052958453 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.978255476 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4720680000 ps |
| CPU time | 19.89 seconds |
| Started | Aug 09 06:35:36 PM PDT 24 |
| Finished | Aug 09 06:36:14 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-f9677f3d-4604-432f-bb99-e78980dfd41e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=978255476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.978255476 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3489943704 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8911260000 ps |
| CPU time | 27.79 seconds |
| Started | Aug 09 06:35:36 PM PDT 24 |
| Finished | Aug 09 06:36:27 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-baecfbcb-dbc1-4ac1-a1aa-71a3f98c72d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489943704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3489943704 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1632460105 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14062220000 ps |
| CPU time | 41.24 seconds |
| Started | Aug 09 06:35:38 PM PDT 24 |
| Finished | Aug 09 06:36:55 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-81500053-f06a-4d16-b5ac-1b587dcd11e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632460105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1632460105 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.830525120 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13338060000 ps |
| CPU time | 39.49 seconds |
| Started | Aug 09 06:35:26 PM PDT 24 |
| Finished | Aug 09 06:36:40 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-101f00c0-3220-48a8-a44c-424436e6b333 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830525120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.830525120 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1145799528 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8585140000 ps |
| CPU time | 28.74 seconds |
| Started | Aug 09 06:35:46 PM PDT 24 |
| Finished | Aug 09 06:36:40 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-65eaefd8-483f-48eb-b0a7-caea59c4b45a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145799528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1145799528 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3603795594 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13044180000 ps |
| CPU time | 46.95 seconds |
| Started | Aug 09 06:35:44 PM PDT 24 |
| Finished | Aug 09 06:37:15 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-e1805014-e6b7-4c84-858f-9e9fc5188991 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603795594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3603795594 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1888929788 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11780000000 ps |
| CPU time | 42.41 seconds |
| Started | Aug 09 06:35:46 PM PDT 24 |
| Finished | Aug 09 06:37:07 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-283d3382-4160-4d2c-a347-d1709b7c1fdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888929788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1888929788 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3878476772 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 15176360000 ps |
| CPU time | 61.66 seconds |
| Started | Aug 09 06:35:45 PM PDT 24 |
| Finished | Aug 09 06:37:44 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-4b01f2cf-1dc1-466c-a0dc-c7593ac744cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3878476772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3878476772 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.895038308 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4109360000 ps |
| CPU time | 15.95 seconds |
| Started | Aug 09 06:35:47 PM PDT 24 |
| Finished | Aug 09 06:36:17 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-374b05da-b53a-459d-ab2a-6e433876731c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895038308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.895038308 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4166190404 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 15114980000 ps |
| CPU time | 52.74 seconds |
| Started | Aug 09 06:35:46 PM PDT 24 |
| Finished | Aug 09 06:37:25 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-d111eb8d-bcb6-4b08-8d03-6a6eddb855e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166190404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4166190404 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.4019151022 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13114240000 ps |
| CPU time | 42.62 seconds |
| Started | Aug 09 06:35:45 PM PDT 24 |
| Finished | Aug 09 06:37:04 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-6ad35a56-e094-4c02-877d-ea18c95b5be0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019151022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.4019151022 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.967411395 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9933020000 ps |
| CPU time | 36.44 seconds |
| Started | Aug 09 06:35:46 PM PDT 24 |
| Finished | Aug 09 06:36:54 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-b1e8bea5-3024-49ff-8796-5d042fa2836f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=967411395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.967411395 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2801797042 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6606720000 ps |
| CPU time | 18.71 seconds |
| Started | Aug 09 06:35:45 PM PDT 24 |
| Finished | Aug 09 06:36:20 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-7b37fbd5-ad1f-4e56-bfb6-f6cc0abe8c39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801797042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2801797042 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3954122428 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14573100000 ps |
| CPU time | 53.3 seconds |
| Started | Aug 09 06:35:46 PM PDT 24 |
| Finished | Aug 09 06:37:27 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-6f53c3bb-ad1f-4bd2-bfc4-1c3e01cdc826 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954122428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3954122428 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1493780169 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3693960000 ps |
| CPU time | 12.7 seconds |
| Started | Aug 09 06:35:27 PM PDT 24 |
| Finished | Aug 09 06:35:50 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-75d6e23b-95fd-4123-a83b-7e3d00c8b26c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493780169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1493780169 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.37586325 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10873560000 ps |
| CPU time | 48.51 seconds |
| Started | Aug 09 06:35:46 PM PDT 24 |
| Finished | Aug 09 06:37:19 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-7ae538d1-d149-4362-a96f-6bc26ae31073 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37586325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.37586325 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3501344718 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8374340000 ps |
| CPU time | 34.8 seconds |
| Started | Aug 09 06:35:46 PM PDT 24 |
| Finished | Aug 09 06:36:53 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-35ea0ad5-9d42-428a-abe4-49f4e463ce8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501344718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3501344718 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.734929995 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 15044300000 ps |
| CPU time | 54.93 seconds |
| Started | Aug 09 06:35:45 PM PDT 24 |
| Finished | Aug 09 06:37:31 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-9be1aa2b-aba5-484c-9827-262b103b0ff7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=734929995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.734929995 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2028768665 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14896120000 ps |
| CPU time | 57.99 seconds |
| Started | Aug 09 06:35:47 PM PDT 24 |
| Finished | Aug 09 06:37:40 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-2697ea92-4332-41a9-bbd8-095207b9fdcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028768665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2028768665 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.345552804 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12216480000 ps |
| CPU time | 43 seconds |
| Started | Aug 09 06:35:45 PM PDT 24 |
| Finished | Aug 09 06:37:06 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-711a4c29-7f96-4f5b-ad89-48e493ee842e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345552804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.345552804 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2921303721 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14653700000 ps |
| CPU time | 46.19 seconds |
| Started | Aug 09 06:35:47 PM PDT 24 |
| Finished | Aug 09 06:37:14 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-e39ac8f3-43b7-4d5d-bdf8-e65ca540e2cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921303721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2921303721 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3828209922 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 15319580000 ps |
| CPU time | 53.07 seconds |
| Started | Aug 09 06:35:47 PM PDT 24 |
| Finished | Aug 09 06:37:28 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-68bde8c0-80e8-4dc7-9a9c-f2f2b4203ae8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828209922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3828209922 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1854204218 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10835740000 ps |
| CPU time | 38.75 seconds |
| Started | Aug 09 06:35:47 PM PDT 24 |
| Finished | Aug 09 06:37:01 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-23f965bb-bb4b-41e6-a1ca-e760fba7cf3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854204218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1854204218 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.335710957 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9433920000 ps |
| CPU time | 29.17 seconds |
| Started | Aug 09 06:35:56 PM PDT 24 |
| Finished | Aug 09 06:36:50 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-2bd13c50-1c7e-4a12-b6d8-f40d5e9cbe73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335710957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.335710957 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.605109519 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5127400000 ps |
| CPU time | 19.69 seconds |
| Started | Aug 09 06:35:55 PM PDT 24 |
| Finished | Aug 09 06:36:31 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-75b3c8f4-da78-456f-9be8-92f0ebb6453e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=605109519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.605109519 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1053476652 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12909020000 ps |
| CPU time | 49.58 seconds |
| Started | Aug 09 06:35:37 PM PDT 24 |
| Finished | Aug 09 06:37:14 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-142899fc-b0b4-419c-8fdd-7b88c0bf6689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053476652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1053476652 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.387142354 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12176800000 ps |
| CPU time | 38.79 seconds |
| Started | Aug 09 06:35:57 PM PDT 24 |
| Finished | Aug 09 06:37:09 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-232c0c45-4107-4278-bb52-98f5c0fe784a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387142354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.387142354 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1191515774 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13964880000 ps |
| CPU time | 53.92 seconds |
| Started | Aug 09 06:35:54 PM PDT 24 |
| Finished | Aug 09 06:37:37 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-77842c73-ee03-4be3-b054-3db540624f54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191515774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1191515774 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3064436682 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12625060000 ps |
| CPU time | 38.86 seconds |
| Started | Aug 09 06:35:57 PM PDT 24 |
| Finished | Aug 09 06:37:09 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-22f0b19c-a3d9-4821-bb99-bbb085fc4565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064436682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3064436682 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.515307800 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3450920000 ps |
| CPU time | 15.55 seconds |
| Started | Aug 09 06:35:54 PM PDT 24 |
| Finished | Aug 09 06:36:25 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-edde0a9c-fbb6-4a1b-92e9-8dac5479afec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=515307800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.515307800 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2055392715 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8511980000 ps |
| CPU time | 31.55 seconds |
| Started | Aug 09 06:36:00 PM PDT 24 |
| Finished | Aug 09 06:37:01 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-9af63159-f7b8-4eb4-8852-547e90f2e161 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055392715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2055392715 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.155159124 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3689620000 ps |
| CPU time | 11.44 seconds |
| Started | Aug 09 06:35:59 PM PDT 24 |
| Finished | Aug 09 06:36:20 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-2600b0ae-a60b-4c5f-822d-de101c2dc8fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155159124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.155159124 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3999874933 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9412840000 ps |
| CPU time | 44.11 seconds |
| Started | Aug 09 06:35:56 PM PDT 24 |
| Finished | Aug 09 06:37:22 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-cf6ddd7d-3d13-4bd6-ad59-029b62c620d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999874933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3999874933 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3114420773 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12032340000 ps |
| CPU time | 47.2 seconds |
| Started | Aug 09 06:35:55 PM PDT 24 |
| Finished | Aug 09 06:37:27 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-17e05bfc-efe4-43b7-86d8-d0c173bd3f4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114420773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3114420773 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1627774571 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 14649980000 ps |
| CPU time | 52.56 seconds |
| Started | Aug 09 06:35:55 PM PDT 24 |
| Finished | Aug 09 06:37:36 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-53c8a0cf-0179-40f6-801f-67df0b613106 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627774571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1627774571 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2471826117 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14117400000 ps |
| CPU time | 52.64 seconds |
| Started | Aug 09 06:35:57 PM PDT 24 |
| Finished | Aug 09 06:37:37 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-9840be79-d2bb-47d3-bc81-51ab6a49b437 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471826117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2471826117 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1036644299 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12052800000 ps |
| CPU time | 42.57 seconds |
| Started | Aug 09 06:35:34 PM PDT 24 |
| Finished | Aug 09 06:36:54 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-7bd1fe06-4c63-4af9-9f9d-bbbf25d61f44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1036644299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1036644299 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2251794873 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7983120000 ps |
| CPU time | 31.1 seconds |
| Started | Aug 09 06:35:35 PM PDT 24 |
| Finished | Aug 09 06:36:37 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c326d23c-4a37-42ef-93e1-b62af802a259 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2251794873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2251794873 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.765898274 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13981620000 ps |
| CPU time | 52.01 seconds |
| Started | Aug 09 06:35:36 PM PDT 24 |
| Finished | Aug 09 06:37:16 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-07338cd6-34a5-4931-b1bb-e8fbaff26fa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=765898274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.765898274 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3409049740 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4031240000 ps |
| CPU time | 12.21 seconds |
| Started | Aug 09 06:35:37 PM PDT 24 |
| Finished | Aug 09 06:36:00 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-5cdbaac5-c922-4efe-94e8-4d2c819528c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409049740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3409049740 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3909115295 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9768100000 ps |
| CPU time | 43.13 seconds |
| Started | Aug 09 06:35:36 PM PDT 24 |
| Finished | Aug 09 06:36:59 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-127383c1-78aa-4c65-8399-21a314e5385e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909115295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3909115295 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |