| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/18.prim_present_test.2883715705 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2672258407 |
| /workspace/coverage/default/1.prim_present_test.2699632781 |
| /workspace/coverage/default/10.prim_present_test.1853653296 |
| /workspace/coverage/default/11.prim_present_test.411836356 |
| /workspace/coverage/default/12.prim_present_test.1481617736 |
| /workspace/coverage/default/13.prim_present_test.300649839 |
| /workspace/coverage/default/14.prim_present_test.2517387793 |
| /workspace/coverage/default/15.prim_present_test.1910134473 |
| /workspace/coverage/default/16.prim_present_test.2428944380 |
| /workspace/coverage/default/17.prim_present_test.547301629 |
| /workspace/coverage/default/19.prim_present_test.392693281 |
| /workspace/coverage/default/2.prim_present_test.2538464666 |
| /workspace/coverage/default/20.prim_present_test.2446498388 |
| /workspace/coverage/default/21.prim_present_test.2837379963 |
| /workspace/coverage/default/22.prim_present_test.2487489074 |
| /workspace/coverage/default/23.prim_present_test.985544641 |
| /workspace/coverage/default/24.prim_present_test.2397688643 |
| /workspace/coverage/default/25.prim_present_test.2538400 |
| /workspace/coverage/default/26.prim_present_test.1132452075 |
| /workspace/coverage/default/27.prim_present_test.4142938741 |
| /workspace/coverage/default/28.prim_present_test.3405664253 |
| /workspace/coverage/default/29.prim_present_test.3155141442 |
| /workspace/coverage/default/3.prim_present_test.2073699944 |
| /workspace/coverage/default/30.prim_present_test.2608688898 |
| /workspace/coverage/default/31.prim_present_test.2046880114 |
| /workspace/coverage/default/32.prim_present_test.3129440503 |
| /workspace/coverage/default/33.prim_present_test.2980010363 |
| /workspace/coverage/default/34.prim_present_test.2544037733 |
| /workspace/coverage/default/35.prim_present_test.1948436262 |
| /workspace/coverage/default/36.prim_present_test.4286009382 |
| /workspace/coverage/default/37.prim_present_test.2398354468 |
| /workspace/coverage/default/38.prim_present_test.2598614604 |
| /workspace/coverage/default/39.prim_present_test.2829358993 |
| /workspace/coverage/default/4.prim_present_test.4255229767 |
| /workspace/coverage/default/40.prim_present_test.1281072259 |
| /workspace/coverage/default/41.prim_present_test.2474529891 |
| /workspace/coverage/default/42.prim_present_test.3966997411 |
| /workspace/coverage/default/43.prim_present_test.2787042521 |
| /workspace/coverage/default/44.prim_present_test.1567319468 |
| /workspace/coverage/default/45.prim_present_test.3554380501 |
| /workspace/coverage/default/46.prim_present_test.2670579401 |
| /workspace/coverage/default/47.prim_present_test.1425946054 |
| /workspace/coverage/default/48.prim_present_test.2137038184 |
| /workspace/coverage/default/49.prim_present_test.664892827 |
| /workspace/coverage/default/5.prim_present_test.1424355803 |
| /workspace/coverage/default/6.prim_present_test.4255753162 |
| /workspace/coverage/default/7.prim_present_test.2073885441 |
| /workspace/coverage/default/8.prim_present_test.2025145693 |
| /workspace/coverage/default/9.prim_present_test.3066006364 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/36.prim_present_test.4286009382 | Aug 10 04:32:53 PM PDT 24 | Aug 10 04:33:36 PM PDT 24 | 6520540000 ps | ||
| T2 | /workspace/coverage/default/23.prim_present_test.985544641 | Aug 10 04:33:01 PM PDT 24 | Aug 10 04:33:44 PM PDT 24 | 6449860000 ps | ||
| T3 | /workspace/coverage/default/24.prim_present_test.2397688643 | Aug 10 04:33:02 PM PDT 24 | Aug 10 04:33:51 PM PDT 24 | 8217480000 ps | ||
| T4 | /workspace/coverage/default/20.prim_present_test.2446498388 | Aug 10 04:33:03 PM PDT 24 | Aug 10 04:33:51 PM PDT 24 | 7466040000 ps | ||
| T5 | /workspace/coverage/default/3.prim_present_test.2073699944 | Aug 10 04:32:55 PM PDT 24 | Aug 10 04:33:42 PM PDT 24 | 7903760000 ps | ||
| T6 | /workspace/coverage/default/38.prim_present_test.2598614604 | Aug 10 04:32:53 PM PDT 24 | Aug 10 04:33:47 PM PDT 24 | 6947720000 ps | ||
| T7 | /workspace/coverage/default/18.prim_present_test.2883715705 | Aug 10 04:33:08 PM PDT 24 | Aug 10 04:34:03 PM PDT 24 | 8960860000 ps | ||
| T8 | /workspace/coverage/default/7.prim_present_test.2073885441 | Aug 10 04:32:51 PM PDT 24 | Aug 10 04:33:34 PM PDT 24 | 6430640000 ps | ||
| T9 | /workspace/coverage/default/31.prim_present_test.2046880114 | Aug 10 04:32:48 PM PDT 24 | Aug 10 04:33:25 PM PDT 24 | 6190080000 ps | ||
| T10 | /workspace/coverage/default/39.prim_present_test.2829358993 | Aug 10 04:32:59 PM PDT 24 | Aug 10 04:34:08 PM PDT 24 | 11653520000 ps | ||
| T11 | /workspace/coverage/default/27.prim_present_test.4142938741 | Aug 10 04:32:55 PM PDT 24 | Aug 10 04:33:31 PM PDT 24 | 5856520000 ps | ||
| T12 | /workspace/coverage/default/16.prim_present_test.2428944380 | Aug 10 04:32:58 PM PDT 24 | Aug 10 04:34:22 PM PDT 24 | 12437200000 ps | ||
| T13 | /workspace/coverage/default/25.prim_present_test.2538400 | Aug 10 04:33:02 PM PDT 24 | Aug 10 04:34:24 PM PDT 24 | 12575460000 ps | ||
| T14 | /workspace/coverage/default/28.prim_present_test.3405664253 | Aug 10 04:33:03 PM PDT 24 | Aug 10 04:33:37 PM PDT 24 | 5691600000 ps | ||
| T15 | /workspace/coverage/default/0.prim_present_test.2672258407 | Aug 10 04:32:59 PM PDT 24 | Aug 10 04:34:26 PM PDT 24 | 13713780000 ps | ||
| T16 | /workspace/coverage/default/30.prim_present_test.2608688898 | Aug 10 04:33:11 PM PDT 24 | Aug 10 04:33:48 PM PDT 24 | 5991680000 ps | ||
| T17 | /workspace/coverage/default/47.prim_present_test.1425946054 | Aug 10 04:33:07 PM PDT 24 | Aug 10 04:33:45 PM PDT 24 | 6805740000 ps | ||
| T18 | /workspace/coverage/default/22.prim_present_test.2487489074 | Aug 10 04:33:01 PM PDT 24 | Aug 10 04:33:55 PM PDT 24 | 7090940000 ps | ||
| T19 | /workspace/coverage/default/8.prim_present_test.2025145693 | Aug 10 04:32:58 PM PDT 24 | Aug 10 04:33:40 PM PDT 24 | 6616020000 ps | ||
| T20 | /workspace/coverage/default/10.prim_present_test.1853653296 | Aug 10 04:32:43 PM PDT 24 | Aug 10 04:33:53 PM PDT 24 | 11367080000 ps | ||
| T21 | /workspace/coverage/default/46.prim_present_test.2670579401 | Aug 10 04:32:52 PM PDT 24 | Aug 10 04:33:50 PM PDT 24 | 8706040000 ps | ||
| T22 | /workspace/coverage/default/19.prim_present_test.392693281 | Aug 10 04:32:57 PM PDT 24 | Aug 10 04:33:21 PM PDT 24 | 3328780000 ps | ||
| T23 | /workspace/coverage/default/49.prim_present_test.664892827 | Aug 10 04:32:50 PM PDT 24 | Aug 10 04:34:06 PM PDT 24 | 11447060000 ps | ||
| T24 | /workspace/coverage/default/12.prim_present_test.1481617736 | Aug 10 04:32:47 PM PDT 24 | Aug 10 04:33:10 PM PDT 24 | 3532760000 ps | ||
| T25 | /workspace/coverage/default/43.prim_present_test.2787042521 | Aug 10 04:33:09 PM PDT 24 | Aug 10 04:34:14 PM PDT 24 | 10454440000 ps | ||
| T26 | /workspace/coverage/default/34.prim_present_test.2544037733 | Aug 10 04:32:57 PM PDT 24 | Aug 10 04:33:36 PM PDT 24 | 6244640000 ps | ||
| T27 | /workspace/coverage/default/4.prim_present_test.4255229767 | Aug 10 04:32:51 PM PDT 24 | Aug 10 04:33:36 PM PDT 24 | 7022740000 ps | ||
| T28 | /workspace/coverage/default/1.prim_present_test.2699632781 | Aug 10 04:32:58 PM PDT 24 | Aug 10 04:33:36 PM PDT 24 | 5620920000 ps | ||
| T29 | /workspace/coverage/default/37.prim_present_test.2398354468 | Aug 10 04:32:57 PM PDT 24 | Aug 10 04:34:17 PM PDT 24 | 11785580000 ps | ||
| T30 | /workspace/coverage/default/35.prim_present_test.1948436262 | Aug 10 04:32:54 PM PDT 24 | Aug 10 04:34:14 PM PDT 24 | 11401800000 ps | ||
| T31 | /workspace/coverage/default/2.prim_present_test.2538464666 | Aug 10 04:32:46 PM PDT 24 | Aug 10 04:33:45 PM PDT 24 | 10184740000 ps | ||
| T32 | /workspace/coverage/default/11.prim_present_test.411836356 | Aug 10 04:32:36 PM PDT 24 | Aug 10 04:33:11 PM PDT 24 | 5521720000 ps | ||
| T33 | /workspace/coverage/default/14.prim_present_test.2517387793 | Aug 10 04:32:41 PM PDT 24 | Aug 10 04:34:00 PM PDT 24 | 10656560000 ps | ||
| T34 | /workspace/coverage/default/40.prim_present_test.1281072259 | Aug 10 04:32:54 PM PDT 24 | Aug 10 04:34:28 PM PDT 24 | 12207800000 ps | ||
| T35 | /workspace/coverage/default/6.prim_present_test.4255753162 | Aug 10 04:32:51 PM PDT 24 | Aug 10 04:34:05 PM PDT 24 | 11675840000 ps | ||
| T36 | /workspace/coverage/default/15.prim_present_test.1910134473 | Aug 10 04:33:08 PM PDT 24 | Aug 10 04:34:20 PM PDT 24 | 8960860000 ps | ||
| T37 | /workspace/coverage/default/26.prim_present_test.1132452075 | Aug 10 04:33:04 PM PDT 24 | Aug 10 04:34:33 PM PDT 24 | 11008720000 ps | ||
| T38 | /workspace/coverage/default/44.prim_present_test.1567319468 | Aug 10 04:33:00 PM PDT 24 | Aug 10 04:34:13 PM PDT 24 | 11383200000 ps | ||
| T39 | /workspace/coverage/default/45.prim_present_test.3554380501 | Aug 10 04:32:56 PM PDT 24 | Aug 10 04:33:21 PM PDT 24 | 3568100000 ps | ||
| T40 | /workspace/coverage/default/5.prim_present_test.1424355803 | Aug 10 04:32:56 PM PDT 24 | Aug 10 04:33:59 PM PDT 24 | 8312960000 ps | ||
| T41 | /workspace/coverage/default/13.prim_present_test.300649839 | Aug 10 04:32:39 PM PDT 24 | Aug 10 04:34:02 PM PDT 24 | 13967980000 ps | ||
| T42 | /workspace/coverage/default/32.prim_present_test.3129440503 | Aug 10 04:32:46 PM PDT 24 | Aug 10 04:33:14 PM PDT 24 | 3918400000 ps | ||
| T43 | /workspace/coverage/default/42.prim_present_test.3966997411 | Aug 10 04:33:00 PM PDT 24 | Aug 10 04:33:34 PM PDT 24 | 4284200000 ps | ||
| T44 | /workspace/coverage/default/17.prim_present_test.547301629 | Aug 10 04:32:50 PM PDT 24 | Aug 10 04:34:10 PM PDT 24 | 12744100000 ps | ||
| T45 | /workspace/coverage/default/29.prim_present_test.3155141442 | Aug 10 04:33:01 PM PDT 24 | Aug 10 04:34:20 PM PDT 24 | 12574840000 ps | ||
| T46 | /workspace/coverage/default/33.prim_present_test.2980010363 | Aug 10 04:33:02 PM PDT 24 | Aug 10 04:34:28 PM PDT 24 | 14875660000 ps | ||
| T47 | /workspace/coverage/default/9.prim_present_test.3066006364 | Aug 10 04:32:51 PM PDT 24 | Aug 10 04:33:35 PM PDT 24 | 6703440000 ps | ||
| T48 | /workspace/coverage/default/41.prim_present_test.2474529891 | Aug 10 04:32:58 PM PDT 24 | Aug 10 04:34:20 PM PDT 24 | 14238300000 ps | ||
| T49 | /workspace/coverage/default/48.prim_present_test.2137038184 | Aug 10 04:33:04 PM PDT 24 | Aug 10 04:33:36 PM PDT 24 | 4762220000 ps | ||
| T50 | /workspace/coverage/default/21.prim_present_test.2837379963 | Aug 10 04:32:58 PM PDT 24 | Aug 10 04:33:38 PM PDT 24 | 6151640000 ps |
| Test location | /workspace/coverage/default/18.prim_present_test.2883715705 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8960860000 ps |
| CPU time | 29.46 seconds |
| Started | Aug 10 04:33:08 PM PDT 24 |
| Finished | Aug 10 04:34:03 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-cfb4a59a-6014-471b-8295-2636634a53e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883715705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2883715705 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2672258407 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13713780000 ps |
| CPU time | 45.95 seconds |
| Started | Aug 10 04:32:59 PM PDT 24 |
| Finished | Aug 10 04:34:26 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-6fd154b1-37ff-424b-bac3-3db8c42e0e6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2672258407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2672258407 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2699632781 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5620920000 ps |
| CPU time | 20.12 seconds |
| Started | Aug 10 04:32:58 PM PDT 24 |
| Finished | Aug 10 04:33:36 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-b9694445-a2b3-4204-bf97-b05c775c1d6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2699632781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2699632781 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1853653296 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11367080000 ps |
| CPU time | 37.63 seconds |
| Started | Aug 10 04:32:43 PM PDT 24 |
| Finished | Aug 10 04:33:53 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-e0752dfb-6f81-4814-9813-d5bf46d8fc9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853653296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1853653296 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.411836356 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5521720000 ps |
| CPU time | 18.99 seconds |
| Started | Aug 10 04:32:36 PM PDT 24 |
| Finished | Aug 10 04:33:11 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-bdfe2402-731b-46f5-a085-73ab8fdffdef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411836356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.411836356 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1481617736 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3532760000 ps |
| CPU time | 12.1 seconds |
| Started | Aug 10 04:32:47 PM PDT 24 |
| Finished | Aug 10 04:33:10 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-4b484c0d-e01c-4687-ac8d-deb1235ffb4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481617736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1481617736 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.300649839 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13967980000 ps |
| CPU time | 43.99 seconds |
| Started | Aug 10 04:32:39 PM PDT 24 |
| Finished | Aug 10 04:34:02 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-a9a2f1b9-43a0-4302-918b-9eeb81960cef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300649839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.300649839 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2517387793 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10656560000 ps |
| CPU time | 40.9 seconds |
| Started | Aug 10 04:32:41 PM PDT 24 |
| Finished | Aug 10 04:34:00 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-19f49256-e566-44db-ab80-7b1a599ca4d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2517387793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2517387793 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1910134473 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8960860000 ps |
| CPU time | 36.84 seconds |
| Started | Aug 10 04:33:08 PM PDT 24 |
| Finished | Aug 10 04:34:20 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-c0506a8d-acd3-4543-9278-2ed1c3cae5c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910134473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1910134473 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2428944380 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12437200000 ps |
| CPU time | 43.75 seconds |
| Started | Aug 10 04:32:58 PM PDT 24 |
| Finished | Aug 10 04:34:22 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-70705045-9f41-4e6e-821d-786109c6ef0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428944380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2428944380 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.547301629 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12744100000 ps |
| CPU time | 42.74 seconds |
| Started | Aug 10 04:32:50 PM PDT 24 |
| Finished | Aug 10 04:34:10 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-56fceedf-b45a-484a-92c4-2603a0140219 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547301629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.547301629 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.392693281 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3328780000 ps |
| CPU time | 12.24 seconds |
| Started | Aug 10 04:32:57 PM PDT 24 |
| Finished | Aug 10 04:33:21 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-cab142aa-6ffa-417c-89d2-dd20f45ddfc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392693281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.392693281 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2538464666 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10184740000 ps |
| CPU time | 31.67 seconds |
| Started | Aug 10 04:32:46 PM PDT 24 |
| Finished | Aug 10 04:33:45 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-8804888b-737a-4d44-ae8a-8f265ed943ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538464666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2538464666 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2446498388 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7466040000 ps |
| CPU time | 25.81 seconds |
| Started | Aug 10 04:33:03 PM PDT 24 |
| Finished | Aug 10 04:33:51 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-e33c030a-c33b-444f-84b0-d4d296144db3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446498388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2446498388 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2837379963 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6151640000 ps |
| CPU time | 21.09 seconds |
| Started | Aug 10 04:32:58 PM PDT 24 |
| Finished | Aug 10 04:33:38 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-8e60f0a8-c6c6-4457-be49-4f0347432e78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2837379963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2837379963 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2487489074 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7090940000 ps |
| CPU time | 28.25 seconds |
| Started | Aug 10 04:33:01 PM PDT 24 |
| Finished | Aug 10 04:33:55 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-e1c14089-f8fb-4614-a692-60604bb2727f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487489074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2487489074 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.985544641 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6449860000 ps |
| CPU time | 22.69 seconds |
| Started | Aug 10 04:33:01 PM PDT 24 |
| Finished | Aug 10 04:33:44 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-4136d95b-edfd-4357-ba4b-d3add37d1ea0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985544641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.985544641 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2397688643 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8217480000 ps |
| CPU time | 26.28 seconds |
| Started | Aug 10 04:33:02 PM PDT 24 |
| Finished | Aug 10 04:33:51 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-c7927e4c-6e54-4f24-8fac-10b4870236fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2397688643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2397688643 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2538400 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12575460000 ps |
| CPU time | 43.53 seconds |
| Started | Aug 10 04:33:02 PM PDT 24 |
| Finished | Aug 10 04:34:24 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-df735954-b594-424b-841c-7d54c89d8af2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2538400 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1132452075 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11008720000 ps |
| CPU time | 46 seconds |
| Started | Aug 10 04:33:04 PM PDT 24 |
| Finished | Aug 10 04:34:33 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-7a77d773-878d-4ae1-9262-173cead76b4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132452075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1132452075 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.4142938741 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5856520000 ps |
| CPU time | 19.66 seconds |
| Started | Aug 10 04:32:55 PM PDT 24 |
| Finished | Aug 10 04:33:31 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-dda223ab-5a2d-4119-b7b5-e644c17fe58a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142938741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.4142938741 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3405664253 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5691600000 ps |
| CPU time | 18.02 seconds |
| Started | Aug 10 04:33:03 PM PDT 24 |
| Finished | Aug 10 04:33:37 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-2f7c3dee-dc35-4a57-acaf-66783f6723c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405664253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3405664253 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3155141442 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12574840000 ps |
| CPU time | 42.35 seconds |
| Started | Aug 10 04:33:01 PM PDT 24 |
| Finished | Aug 10 04:34:20 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-6ed7b186-1679-4f99-a3e2-db2779d716b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155141442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3155141442 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2073699944 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7903760000 ps |
| CPU time | 25.32 seconds |
| Started | Aug 10 04:32:55 PM PDT 24 |
| Finished | Aug 10 04:33:42 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-a6a559f7-6a41-4e79-9fea-b0af5708363f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073699944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2073699944 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2608688898 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5991680000 ps |
| CPU time | 19.36 seconds |
| Started | Aug 10 04:33:11 PM PDT 24 |
| Finished | Aug 10 04:33:48 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-0e6d9a02-8ca9-4cfa-bb01-a38cc830ae08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608688898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2608688898 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2046880114 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6190080000 ps |
| CPU time | 20.29 seconds |
| Started | Aug 10 04:32:48 PM PDT 24 |
| Finished | Aug 10 04:33:25 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-1d93c4ee-1d7b-4910-8d9c-f14b1e9fc12d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046880114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2046880114 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3129440503 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3918400000 ps |
| CPU time | 14.75 seconds |
| Started | Aug 10 04:32:46 PM PDT 24 |
| Finished | Aug 10 04:33:14 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-df79f0ed-83cf-482f-aa69-3d547fa2e11c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3129440503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3129440503 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2980010363 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14875660000 ps |
| CPU time | 45.58 seconds |
| Started | Aug 10 04:33:02 PM PDT 24 |
| Finished | Aug 10 04:34:28 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-4d9f5db1-b86a-4f40-a4b7-8820f22c59e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980010363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2980010363 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2544037733 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 6244640000 ps |
| CPU time | 20.68 seconds |
| Started | Aug 10 04:32:57 PM PDT 24 |
| Finished | Aug 10 04:33:36 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-a84e7c58-5f69-4b3e-9e83-1a4b90459583 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544037733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2544037733 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1948436262 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11401800000 ps |
| CPU time | 41.87 seconds |
| Started | Aug 10 04:32:54 PM PDT 24 |
| Finished | Aug 10 04:34:14 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-c9ae9035-0b3e-4ff5-adbe-5118ac1a162f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948436262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1948436262 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4286009382 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6520540000 ps |
| CPU time | 22.33 seconds |
| Started | Aug 10 04:32:53 PM PDT 24 |
| Finished | Aug 10 04:33:36 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-9c88a5d7-74ac-4864-b6ab-70bfc5067472 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286009382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4286009382 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2398354468 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11785580000 ps |
| CPU time | 41.97 seconds |
| Started | Aug 10 04:32:57 PM PDT 24 |
| Finished | Aug 10 04:34:17 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-cc862246-8800-4d60-9249-ed65d0caffad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2398354468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2398354468 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2598614604 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6947720000 ps |
| CPU time | 27.58 seconds |
| Started | Aug 10 04:32:53 PM PDT 24 |
| Finished | Aug 10 04:33:47 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-d5e5a7cd-c996-42b0-8c3e-96520f27f024 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598614604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2598614604 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2829358993 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11653520000 ps |
| CPU time | 37.11 seconds |
| Started | Aug 10 04:32:59 PM PDT 24 |
| Finished | Aug 10 04:34:08 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-0b5e79ef-fb0d-4263-a580-f5de6201567c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2829358993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2829358993 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4255229767 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7022740000 ps |
| CPU time | 23.84 seconds |
| Started | Aug 10 04:32:51 PM PDT 24 |
| Finished | Aug 10 04:33:36 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-bff254df-2ebe-42d9-895c-4f1029ef7583 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255229767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4255229767 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1281072259 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12207800000 ps |
| CPU time | 48.3 seconds |
| Started | Aug 10 04:32:54 PM PDT 24 |
| Finished | Aug 10 04:34:28 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-ebd83a59-4bf9-4b4d-a7ec-d670e390befb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281072259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1281072259 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2474529891 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14238300000 ps |
| CPU time | 44.39 seconds |
| Started | Aug 10 04:32:58 PM PDT 24 |
| Finished | Aug 10 04:34:20 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-150ba534-9b9b-4168-8d56-c5e9e15a52fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474529891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2474529891 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3966997411 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4284200000 ps |
| CPU time | 17.62 seconds |
| Started | Aug 10 04:33:00 PM PDT 24 |
| Finished | Aug 10 04:33:34 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-1b587dae-c749-4297-84ea-01cbb33d3ee7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966997411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3966997411 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2787042521 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10454440000 ps |
| CPU time | 35.02 seconds |
| Started | Aug 10 04:33:09 PM PDT 24 |
| Finished | Aug 10 04:34:14 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-5f0311ca-c3ef-46c2-8236-18e0f6b8c801 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2787042521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2787042521 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1567319468 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11383200000 ps |
| CPU time | 39.05 seconds |
| Started | Aug 10 04:33:00 PM PDT 24 |
| Finished | Aug 10 04:34:13 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-8a8f971b-da05-4c02-bfd1-33991f37509d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1567319468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1567319468 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3554380501 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3568100000 ps |
| CPU time | 13.01 seconds |
| Started | Aug 10 04:32:56 PM PDT 24 |
| Finished | Aug 10 04:33:21 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-0bb05edf-358e-425b-bbd3-3ecff33c4910 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554380501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3554380501 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2670579401 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8706040000 ps |
| CPU time | 31.1 seconds |
| Started | Aug 10 04:32:52 PM PDT 24 |
| Finished | Aug 10 04:33:50 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-f2b3b355-a262-4a7a-9443-8b5b1f570000 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670579401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2670579401 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1425946054 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6805740000 ps |
| CPU time | 20.73 seconds |
| Started | Aug 10 04:33:07 PM PDT 24 |
| Finished | Aug 10 04:33:45 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-0203dda0-761a-47c8-bd72-1f822befd9ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425946054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1425946054 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2137038184 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4762220000 ps |
| CPU time | 17.01 seconds |
| Started | Aug 10 04:33:04 PM PDT 24 |
| Finished | Aug 10 04:33:36 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-6a4f002a-1503-4458-b1a1-eaa975193292 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137038184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2137038184 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.664892827 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11447060000 ps |
| CPU time | 40.07 seconds |
| Started | Aug 10 04:32:50 PM PDT 24 |
| Finished | Aug 10 04:34:06 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-df3705c9-49a9-4f60-8cac-689056cc5086 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664892827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.664892827 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1424355803 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8312960000 ps |
| CPU time | 33.51 seconds |
| Started | Aug 10 04:32:56 PM PDT 24 |
| Finished | Aug 10 04:33:59 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-c699efda-9b93-4a7a-b612-0e251262823b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424355803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1424355803 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4255753162 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11675840000 ps |
| CPU time | 39.2 seconds |
| Started | Aug 10 04:32:51 PM PDT 24 |
| Finished | Aug 10 04:34:05 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-d25aedf7-d695-44c5-ada0-d7811169704a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255753162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4255753162 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2073885441 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6430640000 ps |
| CPU time | 22.45 seconds |
| Started | Aug 10 04:32:51 PM PDT 24 |
| Finished | Aug 10 04:33:34 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-55d65e33-cd59-477a-82a7-fd859ff70170 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073885441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2073885441 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2025145693 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6616020000 ps |
| CPU time | 22.4 seconds |
| Started | Aug 10 04:32:58 PM PDT 24 |
| Finished | Aug 10 04:33:40 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-49e65878-bfec-4078-bf24-6498996492c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025145693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2025145693 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3066006364 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6703440000 ps |
| CPU time | 23.34 seconds |
| Started | Aug 10 04:32:51 PM PDT 24 |
| Finished | Aug 10 04:33:35 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-97ef2989-dbf9-47ac-b50b-6cc409faa14e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066006364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3066006364 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |