| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.1033935497 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.225640506 |
| /workspace/coverage/default/10.prim_present_test.4288593044 |
| /workspace/coverage/default/11.prim_present_test.3584248363 |
| /workspace/coverage/default/12.prim_present_test.1973650146 |
| /workspace/coverage/default/13.prim_present_test.1128680085 |
| /workspace/coverage/default/14.prim_present_test.3112761801 |
| /workspace/coverage/default/15.prim_present_test.3183295055 |
| /workspace/coverage/default/16.prim_present_test.1598517302 |
| /workspace/coverage/default/17.prim_present_test.3919374571 |
| /workspace/coverage/default/18.prim_present_test.1692404257 |
| /workspace/coverage/default/19.prim_present_test.1853372035 |
| /workspace/coverage/default/2.prim_present_test.1457367475 |
| /workspace/coverage/default/20.prim_present_test.3926441066 |
| /workspace/coverage/default/21.prim_present_test.1572856437 |
| /workspace/coverage/default/22.prim_present_test.1804908638 |
| /workspace/coverage/default/23.prim_present_test.1434186988 |
| /workspace/coverage/default/24.prim_present_test.292766894 |
| /workspace/coverage/default/25.prim_present_test.2709414273 |
| /workspace/coverage/default/26.prim_present_test.2388808498 |
| /workspace/coverage/default/27.prim_present_test.2276937965 |
| /workspace/coverage/default/28.prim_present_test.3384684788 |
| /workspace/coverage/default/29.prim_present_test.173259836 |
| /workspace/coverage/default/3.prim_present_test.1554971379 |
| /workspace/coverage/default/30.prim_present_test.274289750 |
| /workspace/coverage/default/31.prim_present_test.3373381796 |
| /workspace/coverage/default/32.prim_present_test.29179230 |
| /workspace/coverage/default/33.prim_present_test.1176784948 |
| /workspace/coverage/default/34.prim_present_test.645523066 |
| /workspace/coverage/default/35.prim_present_test.1136595219 |
| /workspace/coverage/default/36.prim_present_test.1424142443 |
| /workspace/coverage/default/37.prim_present_test.1064430385 |
| /workspace/coverage/default/38.prim_present_test.3303187661 |
| /workspace/coverage/default/39.prim_present_test.75672337 |
| /workspace/coverage/default/4.prim_present_test.1991036363 |
| /workspace/coverage/default/40.prim_present_test.2487235778 |
| /workspace/coverage/default/41.prim_present_test.1341617726 |
| /workspace/coverage/default/42.prim_present_test.3720106113 |
| /workspace/coverage/default/43.prim_present_test.2133934123 |
| /workspace/coverage/default/44.prim_present_test.1644440893 |
| /workspace/coverage/default/45.prim_present_test.3972010101 |
| /workspace/coverage/default/46.prim_present_test.3810407084 |
| /workspace/coverage/default/47.prim_present_test.310100941 |
| /workspace/coverage/default/48.prim_present_test.3401422408 |
| /workspace/coverage/default/49.prim_present_test.1728496503 |
| /workspace/coverage/default/5.prim_present_test.3601765098 |
| /workspace/coverage/default/6.prim_present_test.4053626755 |
| /workspace/coverage/default/7.prim_present_test.3829412764 |
| /workspace/coverage/default/8.prim_present_test.1430585385 |
| /workspace/coverage/default/9.prim_present_test.4161763200 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/36.prim_present_test.1424142443 | Aug 11 04:36:32 PM PDT 24 | Aug 11 04:37:38 PM PDT 24 | 11554320000 ps | ||
| T2 | /workspace/coverage/default/30.prim_present_test.274289750 | Aug 11 04:36:07 PM PDT 24 | Aug 11 04:37:39 PM PDT 24 | 12887940000 ps | ||
| T3 | /workspace/coverage/default/22.prim_present_test.1804908638 | Aug 11 04:36:04 PM PDT 24 | Aug 11 04:37:32 PM PDT 24 | 13796860000 ps | ||
| T4 | /workspace/coverage/default/0.prim_present_test.1033935497 | Aug 11 04:36:05 PM PDT 24 | Aug 11 04:36:27 PM PDT 24 | 3698920000 ps | ||
| T5 | /workspace/coverage/default/2.prim_present_test.1457367475 | Aug 11 04:36:01 PM PDT 24 | Aug 11 04:37:04 PM PDT 24 | 10879140000 ps | ||
| T6 | /workspace/coverage/default/43.prim_present_test.2133934123 | Aug 11 04:36:16 PM PDT 24 | Aug 11 04:36:41 PM PDT 24 | 4327600000 ps | ||
| T7 | /workspace/coverage/default/8.prim_present_test.1430585385 | Aug 11 04:36:00 PM PDT 24 | Aug 11 04:36:37 PM PDT 24 | 6120640000 ps | ||
| T8 | /workspace/coverage/default/27.prim_present_test.2276937965 | Aug 11 04:36:02 PM PDT 24 | Aug 11 04:37:29 PM PDT 24 | 13762140000 ps | ||
| T9 | /workspace/coverage/default/21.prim_present_test.1572856437 | Aug 11 04:36:07 PM PDT 24 | Aug 11 04:37:18 PM PDT 24 | 10595180000 ps | ||
| T10 | /workspace/coverage/default/7.prim_present_test.3829412764 | Aug 11 04:36:15 PM PDT 24 | Aug 11 04:37:04 PM PDT 24 | 8630400000 ps | ||
| T11 | /workspace/coverage/default/10.prim_present_test.4288593044 | Aug 11 04:37:40 PM PDT 24 | Aug 11 04:39:11 PM PDT 24 | 14446620000 ps | ||
| T12 | /workspace/coverage/default/20.prim_present_test.3926441066 | Aug 11 04:36:06 PM PDT 24 | Aug 11 04:36:47 PM PDT 24 | 6257040000 ps | ||
| T13 | /workspace/coverage/default/48.prim_present_test.3401422408 | Aug 11 04:37:09 PM PDT 24 | Aug 11 04:38:32 PM PDT 24 | 11608880000 ps | ||
| T14 | /workspace/coverage/default/46.prim_present_test.3810407084 | Aug 11 04:36:09 PM PDT 24 | Aug 11 04:37:18 PM PDT 24 | 10596420000 ps | ||
| T15 | /workspace/coverage/default/12.prim_present_test.1973650146 | Aug 11 04:36:04 PM PDT 24 | Aug 11 04:36:34 PM PDT 24 | 5683540000 ps | ||
| T16 | /workspace/coverage/default/38.prim_present_test.3303187661 | Aug 11 04:36:05 PM PDT 24 | Aug 11 04:36:37 PM PDT 24 | 5118720000 ps | ||
| T17 | /workspace/coverage/default/11.prim_present_test.3584248363 | Aug 11 04:36:11 PM PDT 24 | Aug 11 04:36:48 PM PDT 24 | 5997260000 ps | ||
| T18 | /workspace/coverage/default/19.prim_present_test.1853372035 | Aug 11 04:36:00 PM PDT 24 | Aug 11 04:37:49 PM PDT 24 | 14281700000 ps | ||
| T19 | /workspace/coverage/default/40.prim_present_test.2487235778 | Aug 11 04:36:26 PM PDT 24 | Aug 11 04:37:50 PM PDT 24 | 12540740000 ps | ||
| T20 | /workspace/coverage/default/33.prim_present_test.1176784948 | Aug 11 04:36:12 PM PDT 24 | Aug 11 04:37:02 PM PDT 24 | 7639640000 ps | ||
| T21 | /workspace/coverage/default/24.prim_present_test.292766894 | Aug 11 04:37:09 PM PDT 24 | Aug 11 04:37:41 PM PDT 24 | 4136640000 ps | ||
| T22 | /workspace/coverage/default/17.prim_present_test.3919374571 | Aug 11 04:37:29 PM PDT 24 | Aug 11 04:37:55 PM PDT 24 | 3336840000 ps | ||
| T23 | /workspace/coverage/default/49.prim_present_test.1728496503 | Aug 11 04:36:26 PM PDT 24 | Aug 11 04:37:56 PM PDT 24 | 12745960000 ps | ||
| T24 | /workspace/coverage/default/26.prim_present_test.2388808498 | Aug 11 04:36:10 PM PDT 24 | Aug 11 04:37:35 PM PDT 24 | 12289640000 ps | ||
| T25 | /workspace/coverage/default/47.prim_present_test.310100941 | Aug 11 04:37:09 PM PDT 24 | Aug 11 04:38:46 PM PDT 24 | 14062840000 ps | ||
| T26 | /workspace/coverage/default/32.prim_present_test.29179230 | Aug 11 04:36:17 PM PDT 24 | Aug 11 04:37:16 PM PDT 24 | 10097320000 ps | ||
| T27 | /workspace/coverage/default/34.prim_present_test.645523066 | Aug 11 04:37:26 PM PDT 24 | Aug 11 04:38:18 PM PDT 24 | 6749320000 ps | ||
| T28 | /workspace/coverage/default/25.prim_present_test.2709414273 | Aug 11 04:36:06 PM PDT 24 | Aug 11 04:37:21 PM PDT 24 | 12667840000 ps | ||
| T29 | /workspace/coverage/default/35.prim_present_test.1136595219 | Aug 11 04:36:07 PM PDT 24 | Aug 11 04:37:33 PM PDT 24 | 15315860000 ps | ||
| T30 | /workspace/coverage/default/4.prim_present_test.1991036363 | Aug 11 04:36:03 PM PDT 24 | Aug 11 04:37:21 PM PDT 24 | 13491820000 ps | ||
| T31 | /workspace/coverage/default/15.prim_present_test.3183295055 | Aug 11 04:37:09 PM PDT 24 | Aug 11 04:37:50 PM PDT 24 | 5417560000 ps | ||
| T32 | /workspace/coverage/default/9.prim_present_test.4161763200 | Aug 11 04:36:16 PM PDT 24 | Aug 11 04:37:46 PM PDT 24 | 14418720000 ps | ||
| T33 | /workspace/coverage/default/44.prim_present_test.1644440893 | Aug 11 04:36:06 PM PDT 24 | Aug 11 04:37:42 PM PDT 24 | 13383320000 ps | ||
| T34 | /workspace/coverage/default/5.prim_present_test.3601765098 | Aug 11 04:36:23 PM PDT 24 | Aug 11 04:37:13 PM PDT 24 | 8841200000 ps | ||
| T35 | /workspace/coverage/default/37.prim_present_test.1064430385 | Aug 11 04:36:20 PM PDT 24 | Aug 11 04:36:49 PM PDT 24 | 3403180000 ps | ||
| T36 | /workspace/coverage/default/28.prim_present_test.3384684788 | Aug 11 04:36:45 PM PDT 24 | Aug 11 04:37:18 PM PDT 24 | 6348180000 ps | ||
| T37 | /workspace/coverage/default/3.prim_present_test.1554971379 | Aug 11 04:36:13 PM PDT 24 | Aug 11 04:37:31 PM PDT 24 | 14322620000 ps | ||
| T38 | /workspace/coverage/default/31.prim_present_test.3373381796 | Aug 11 04:36:05 PM PDT 24 | Aug 11 04:37:25 PM PDT 24 | 14563180000 ps | ||
| T39 | /workspace/coverage/default/1.prim_present_test.225640506 | Aug 11 04:36:19 PM PDT 24 | Aug 11 04:37:33 PM PDT 24 | 13599080000 ps | ||
| T40 | /workspace/coverage/default/39.prim_present_test.75672337 | Aug 11 04:36:03 PM PDT 24 | Aug 11 04:37:07 PM PDT 24 | 9475460000 ps | ||
| T41 | /workspace/coverage/default/23.prim_present_test.1434186988 | Aug 11 04:36:06 PM PDT 24 | Aug 11 04:37:07 PM PDT 24 | 9735860000 ps | ||
| T42 | /workspace/coverage/default/42.prim_present_test.3720106113 | Aug 11 04:36:25 PM PDT 24 | Aug 11 04:37:24 PM PDT 24 | 10120880000 ps | ||
| T43 | /workspace/coverage/default/41.prim_present_test.1341617726 | Aug 11 04:36:07 PM PDT 24 | Aug 11 04:36:58 PM PDT 24 | 8740760000 ps | ||
| T44 | /workspace/coverage/default/13.prim_present_test.1128680085 | Aug 11 04:36:12 PM PDT 24 | Aug 11 04:37:33 PM PDT 24 | 12656060000 ps | ||
| T45 | /workspace/coverage/default/14.prim_present_test.3112761801 | Aug 11 04:36:03 PM PDT 24 | Aug 11 04:36:55 PM PDT 24 | 9944800000 ps | ||
| T46 | /workspace/coverage/default/45.prim_present_test.3972010101 | Aug 11 04:36:28 PM PDT 24 | Aug 11 04:38:10 PM PDT 24 | 14302780000 ps | ||
| T47 | /workspace/coverage/default/6.prim_present_test.4053626755 | Aug 11 04:36:00 PM PDT 24 | Aug 11 04:36:54 PM PDT 24 | 8733320000 ps | ||
| T48 | /workspace/coverage/default/16.prim_present_test.1598517302 | Aug 11 04:36:00 PM PDT 24 | Aug 11 04:37:05 PM PDT 24 | 9940460000 ps | ||
| T49 | /workspace/coverage/default/29.prim_present_test.173259836 | Aug 11 04:36:08 PM PDT 24 | Aug 11 04:37:19 PM PDT 24 | 10091740000 ps | ||
| T50 | /workspace/coverage/default/18.prim_present_test.1692404257 | Aug 11 04:36:08 PM PDT 24 | Aug 11 04:36:54 PM PDT 24 | 8401620000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.1033935497 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3698920000 ps |
| CPU time | 12 seconds |
| Started | Aug 11 04:36:05 PM PDT 24 |
| Finished | Aug 11 04:36:27 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-01d1c283-b671-4675-ad48-30ce8db97281 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033935497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1033935497 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.225640506 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13599080000 ps |
| CPU time | 41.09 seconds |
| Started | Aug 11 04:36:19 PM PDT 24 |
| Finished | Aug 11 04:37:33 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-524184a7-414d-41fb-8aa0-89cb35bdc541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225640506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.225640506 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.4288593044 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14446620000 ps |
| CPU time | 47.52 seconds |
| Started | Aug 11 04:37:40 PM PDT 24 |
| Finished | Aug 11 04:39:11 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-25695e8a-19ac-4480-acf1-bc9829b83038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288593044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.4288593044 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3584248363 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5997260000 ps |
| CPU time | 20.08 seconds |
| Started | Aug 11 04:36:11 PM PDT 24 |
| Finished | Aug 11 04:36:48 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-0e70d57b-cfaa-4a1e-bf5e-6925a53fda05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584248363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3584248363 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1973650146 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5683540000 ps |
| CPU time | 16.52 seconds |
| Started | Aug 11 04:36:04 PM PDT 24 |
| Finished | Aug 11 04:36:34 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-6e2c8baa-9fa0-474b-aaf5-e685e5d4323e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1973650146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1973650146 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1128680085 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12656060000 ps |
| CPU time | 42.66 seconds |
| Started | Aug 11 04:36:12 PM PDT 24 |
| Finished | Aug 11 04:37:33 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-d272d0ea-9008-4083-838a-f56fa27cdf86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128680085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1128680085 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3112761801 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9944800000 ps |
| CPU time | 28.34 seconds |
| Started | Aug 11 04:36:03 PM PDT 24 |
| Finished | Aug 11 04:36:55 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-b182b5a0-d47d-489e-bbe2-4c3201d5fafa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3112761801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3112761801 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3183295055 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5417560000 ps |
| CPU time | 21.12 seconds |
| Started | Aug 11 04:37:09 PM PDT 24 |
| Finished | Aug 11 04:37:50 PM PDT 24 |
| Peak memory | 143052 kb |
| Host | smart-303b0a31-5295-4107-8fb8-927a310a8c61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3183295055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3183295055 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1598517302 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9940460000 ps |
| CPU time | 33.72 seconds |
| Started | Aug 11 04:36:00 PM PDT 24 |
| Finished | Aug 11 04:37:05 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-04d3be24-d712-42cb-9cf8-f586d485a3aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598517302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1598517302 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3919374571 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3336840000 ps |
| CPU time | 13.38 seconds |
| Started | Aug 11 04:37:29 PM PDT 24 |
| Finished | Aug 11 04:37:55 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-83431799-6f56-40c0-8423-774e9f1f6b8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3919374571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3919374571 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1692404257 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8401620000 ps |
| CPU time | 25.04 seconds |
| Started | Aug 11 04:36:08 PM PDT 24 |
| Finished | Aug 11 04:36:54 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-0877937a-8833-4b8f-87ce-ebae99cc9ac4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1692404257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1692404257 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1853372035 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14281700000 ps |
| CPU time | 56.33 seconds |
| Started | Aug 11 04:36:00 PM PDT 24 |
| Finished | Aug 11 04:37:49 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-e68bd1f7-9d1f-4701-8237-8a661a1ae88f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853372035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1853372035 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1457367475 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 10879140000 ps |
| CPU time | 33.4 seconds |
| Started | Aug 11 04:36:01 PM PDT 24 |
| Finished | Aug 11 04:37:04 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-eb66b21f-1b54-45ba-a8e7-3b3b08ffb6e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457367475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1457367475 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3926441066 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6257040000 ps |
| CPU time | 22.21 seconds |
| Started | Aug 11 04:36:06 PM PDT 24 |
| Finished | Aug 11 04:36:47 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-b6774adc-f783-4d6f-a57c-800c899f214e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926441066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3926441066 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1572856437 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10595180000 ps |
| CPU time | 37.5 seconds |
| Started | Aug 11 04:36:07 PM PDT 24 |
| Finished | Aug 11 04:37:18 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-3aa8be08-bf99-4278-8320-cfc596891b4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1572856437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1572856437 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1804908638 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13796860000 ps |
| CPU time | 47.01 seconds |
| Started | Aug 11 04:36:04 PM PDT 24 |
| Finished | Aug 11 04:37:32 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-d8123a72-8871-4009-bb17-fe4ab80da925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804908638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1804908638 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1434186988 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9735860000 ps |
| CPU time | 33 seconds |
| Started | Aug 11 04:36:06 PM PDT 24 |
| Finished | Aug 11 04:37:07 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-e137c95e-3f74-47f6-98f8-8447ce2a1cac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1434186988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1434186988 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.292766894 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4136640000 ps |
| CPU time | 16.49 seconds |
| Started | Aug 11 04:37:09 PM PDT 24 |
| Finished | Aug 11 04:37:41 PM PDT 24 |
| Peak memory | 142336 kb |
| Host | smart-a1119eb6-08da-4a32-8936-b35393b5052d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292766894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.292766894 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2709414273 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12667840000 ps |
| CPU time | 40.5 seconds |
| Started | Aug 11 04:36:06 PM PDT 24 |
| Finished | Aug 11 04:37:21 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-eb64953e-dd60-466b-8a6e-588f2b7c7a97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709414273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2709414273 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2388808498 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12289640000 ps |
| CPU time | 44.34 seconds |
| Started | Aug 11 04:36:10 PM PDT 24 |
| Finished | Aug 11 04:37:35 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-69f8a619-a77d-490b-87e0-dd65dd22ef59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388808498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2388808498 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2276937965 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13762140000 ps |
| CPU time | 46.12 seconds |
| Started | Aug 11 04:36:02 PM PDT 24 |
| Finished | Aug 11 04:37:29 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-b60931dd-0935-49b8-a1cb-2d03d26d5d09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276937965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2276937965 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3384684788 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6348180000 ps |
| CPU time | 18.55 seconds |
| Started | Aug 11 04:36:45 PM PDT 24 |
| Finished | Aug 11 04:37:18 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-488b2715-e459-4c72-adee-c734b7e735b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3384684788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3384684788 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.173259836 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10091740000 ps |
| CPU time | 37.74 seconds |
| Started | Aug 11 04:36:08 PM PDT 24 |
| Finished | Aug 11 04:37:19 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-71dbac55-0fc7-423f-b87d-57a94902b251 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173259836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.173259836 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1554971379 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 14322620000 ps |
| CPU time | 43.25 seconds |
| Started | Aug 11 04:36:13 PM PDT 24 |
| Finished | Aug 11 04:37:31 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-77301e64-f481-4dbd-93ce-c915fbd9db0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1554971379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1554971379 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.274289750 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12887940000 ps |
| CPU time | 49.12 seconds |
| Started | Aug 11 04:36:07 PM PDT 24 |
| Finished | Aug 11 04:37:39 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-5f1b1165-0b3f-4fdf-a5eb-a571be208697 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274289750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.274289750 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3373381796 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14563180000 ps |
| CPU time | 43.54 seconds |
| Started | Aug 11 04:36:05 PM PDT 24 |
| Finished | Aug 11 04:37:25 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-c5b3515d-ccbe-4e67-aa27-7c1a8e304846 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373381796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3373381796 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.29179230 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10097320000 ps |
| CPU time | 31.81 seconds |
| Started | Aug 11 04:36:17 PM PDT 24 |
| Finished | Aug 11 04:37:16 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-62a465b4-c070-46f2-b047-88f1b757d0c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29179230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.29179230 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1176784948 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7639640000 ps |
| CPU time | 26.75 seconds |
| Started | Aug 11 04:36:12 PM PDT 24 |
| Finished | Aug 11 04:37:02 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-4f54f055-83a3-492f-9c8e-2f67c7933547 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176784948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1176784948 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.645523066 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6749320000 ps |
| CPU time | 26.94 seconds |
| Started | Aug 11 04:37:26 PM PDT 24 |
| Finished | Aug 11 04:38:18 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-13a75de3-2f16-4e61-b287-c669bdc53aa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645523066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.645523066 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1136595219 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 15315860000 ps |
| CPU time | 45.83 seconds |
| Started | Aug 11 04:36:07 PM PDT 24 |
| Finished | Aug 11 04:37:33 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-0fa115f6-b5c5-43a0-8a5b-60ecfd9a98f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136595219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1136595219 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1424142443 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11554320000 ps |
| CPU time | 35.95 seconds |
| Started | Aug 11 04:36:32 PM PDT 24 |
| Finished | Aug 11 04:37:38 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-00e3a6c7-65f0-4d83-bbdb-4d6dc34f0803 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424142443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1424142443 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1064430385 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3403180000 ps |
| CPU time | 15.05 seconds |
| Started | Aug 11 04:36:20 PM PDT 24 |
| Finished | Aug 11 04:36:49 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-d01ed7d9-5b3e-4774-8bff-3bb2748ac8d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064430385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1064430385 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3303187661 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5118720000 ps |
| CPU time | 17.13 seconds |
| Started | Aug 11 04:36:05 PM PDT 24 |
| Finished | Aug 11 04:36:37 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-a3f78224-0a51-45e2-b9e5-ce4ff0aa3f0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303187661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3303187661 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.75672337 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9475460000 ps |
| CPU time | 33.73 seconds |
| Started | Aug 11 04:36:03 PM PDT 24 |
| Finished | Aug 11 04:37:07 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-d43520d7-29be-41ba-b2e4-bb188ec735c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75672337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.75672337 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1991036363 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13491820000 ps |
| CPU time | 42.61 seconds |
| Started | Aug 11 04:36:03 PM PDT 24 |
| Finished | Aug 11 04:37:21 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-6d2d6cdd-304f-485d-9560-75e4c2fd7fdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991036363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1991036363 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2487235778 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12540740000 ps |
| CPU time | 44.34 seconds |
| Started | Aug 11 04:36:26 PM PDT 24 |
| Finished | Aug 11 04:37:50 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-11ed6bb3-6d41-43cb-be3c-0df3c693cc6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487235778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2487235778 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1341617726 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8740760000 ps |
| CPU time | 27.59 seconds |
| Started | Aug 11 04:36:07 PM PDT 24 |
| Finished | Aug 11 04:36:58 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-659bea70-864f-4526-bad9-5a7e33b4a93d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341617726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1341617726 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3720106113 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10120880000 ps |
| CPU time | 31.73 seconds |
| Started | Aug 11 04:36:25 PM PDT 24 |
| Finished | Aug 11 04:37:24 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-bed50f9e-8868-4d57-b662-b44870569aa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720106113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3720106113 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2133934123 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4327600000 ps |
| CPU time | 13.53 seconds |
| Started | Aug 11 04:36:16 PM PDT 24 |
| Finished | Aug 11 04:36:41 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-f358e507-7531-4610-a6bc-40f8d7e43630 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2133934123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2133934123 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1644440893 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13383320000 ps |
| CPU time | 50.68 seconds |
| Started | Aug 11 04:36:06 PM PDT 24 |
| Finished | Aug 11 04:37:42 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-2eadbd20-0245-4965-838f-30ff2ef78522 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1644440893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1644440893 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3972010101 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14302780000 ps |
| CPU time | 50.87 seconds |
| Started | Aug 11 04:36:28 PM PDT 24 |
| Finished | Aug 11 04:38:10 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-8f2e3a2e-2160-43eb-92fa-ef1297073326 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972010101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3972010101 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3810407084 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10596420000 ps |
| CPU time | 36.9 seconds |
| Started | Aug 11 04:36:09 PM PDT 24 |
| Finished | Aug 11 04:37:18 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-a088d72d-b804-4f89-a42a-5f83a925102a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810407084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3810407084 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.310100941 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 14062840000 ps |
| CPU time | 50.46 seconds |
| Started | Aug 11 04:37:09 PM PDT 24 |
| Finished | Aug 11 04:38:46 PM PDT 24 |
| Peak memory | 143880 kb |
| Host | smart-bd3e4a72-9414-431f-bb74-b7239f90b274 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310100941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.310100941 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3401422408 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11608880000 ps |
| CPU time | 43.26 seconds |
| Started | Aug 11 04:37:09 PM PDT 24 |
| Finished | Aug 11 04:38:32 PM PDT 24 |
| Peak memory | 142224 kb |
| Host | smart-d6e775b2-8653-40b3-b91d-9c37d76edd4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3401422408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3401422408 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1728496503 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12745960000 ps |
| CPU time | 46.9 seconds |
| Started | Aug 11 04:36:26 PM PDT 24 |
| Finished | Aug 11 04:37:56 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-d3d65900-6681-4181-8d93-133e9952381a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728496503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1728496503 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3601765098 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8841200000 ps |
| CPU time | 27.65 seconds |
| Started | Aug 11 04:36:23 PM PDT 24 |
| Finished | Aug 11 04:37:13 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-cf8a2792-4761-454c-b94e-4209025cb8b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601765098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3601765098 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4053626755 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8733320000 ps |
| CPU time | 29 seconds |
| Started | Aug 11 04:36:00 PM PDT 24 |
| Finished | Aug 11 04:36:54 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-35f0f95e-8464-42bd-be3d-1dd05f1981c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4053626755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4053626755 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3829412764 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8630400000 ps |
| CPU time | 26.99 seconds |
| Started | Aug 11 04:36:15 PM PDT 24 |
| Finished | Aug 11 04:37:04 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-4be9bd71-72a0-4f02-b4dc-0c8e38dc052a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829412764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3829412764 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1430585385 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6120640000 ps |
| CPU time | 20.01 seconds |
| Started | Aug 11 04:36:00 PM PDT 24 |
| Finished | Aug 11 04:36:37 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-623ab38f-21b2-40ff-b7ab-42e2dd21a885 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430585385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1430585385 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.4161763200 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14418720000 ps |
| CPU time | 48.26 seconds |
| Started | Aug 11 04:36:16 PM PDT 24 |
| Finished | Aug 11 04:37:46 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-4c7c9c28-1cc9-4bd2-83d2-e664263d7328 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161763200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.4161763200 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |