| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/14.prim_present_test.2935623389 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.974380015 |
| /workspace/coverage/default/1.prim_present_test.3025983249 |
| /workspace/coverage/default/10.prim_present_test.3803023888 |
| /workspace/coverage/default/11.prim_present_test.1451550154 |
| /workspace/coverage/default/12.prim_present_test.4091020491 |
| /workspace/coverage/default/13.prim_present_test.2958319935 |
| /workspace/coverage/default/15.prim_present_test.4033204448 |
| /workspace/coverage/default/16.prim_present_test.3156958970 |
| /workspace/coverage/default/17.prim_present_test.2695315013 |
| /workspace/coverage/default/18.prim_present_test.4264073312 |
| /workspace/coverage/default/19.prim_present_test.4279849852 |
| /workspace/coverage/default/2.prim_present_test.1183456276 |
| /workspace/coverage/default/20.prim_present_test.1249851138 |
| /workspace/coverage/default/21.prim_present_test.3018472787 |
| /workspace/coverage/default/22.prim_present_test.1508476422 |
| /workspace/coverage/default/23.prim_present_test.1316771741 |
| /workspace/coverage/default/24.prim_present_test.3579017654 |
| /workspace/coverage/default/25.prim_present_test.707766677 |
| /workspace/coverage/default/26.prim_present_test.3956991234 |
| /workspace/coverage/default/27.prim_present_test.2224710098 |
| /workspace/coverage/default/28.prim_present_test.507985090 |
| /workspace/coverage/default/29.prim_present_test.3238097292 |
| /workspace/coverage/default/3.prim_present_test.243004609 |
| /workspace/coverage/default/30.prim_present_test.665838878 |
| /workspace/coverage/default/31.prim_present_test.497067579 |
| /workspace/coverage/default/32.prim_present_test.307247972 |
| /workspace/coverage/default/33.prim_present_test.3580790255 |
| /workspace/coverage/default/34.prim_present_test.3803894859 |
| /workspace/coverage/default/35.prim_present_test.3223447836 |
| /workspace/coverage/default/36.prim_present_test.114440223 |
| /workspace/coverage/default/37.prim_present_test.3530529667 |
| /workspace/coverage/default/38.prim_present_test.3415859906 |
| /workspace/coverage/default/39.prim_present_test.1555751774 |
| /workspace/coverage/default/4.prim_present_test.1216472970 |
| /workspace/coverage/default/40.prim_present_test.616609009 |
| /workspace/coverage/default/41.prim_present_test.3647479673 |
| /workspace/coverage/default/42.prim_present_test.761650705 |
| /workspace/coverage/default/43.prim_present_test.3988573780 |
| /workspace/coverage/default/44.prim_present_test.1783823551 |
| /workspace/coverage/default/45.prim_present_test.4020201206 |
| /workspace/coverage/default/46.prim_present_test.4234880267 |
| /workspace/coverage/default/47.prim_present_test.3160311018 |
| /workspace/coverage/default/48.prim_present_test.3153662444 |
| /workspace/coverage/default/49.prim_present_test.3704429309 |
| /workspace/coverage/default/5.prim_present_test.4171906389 |
| /workspace/coverage/default/6.prim_present_test.3402076976 |
| /workspace/coverage/default/7.prim_present_test.2038454526 |
| /workspace/coverage/default/8.prim_present_test.3856318526 |
| /workspace/coverage/default/9.prim_present_test.3317018532 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/22.prim_present_test.1508476422 | Aug 12 04:26:40 PM PDT 24 | Aug 12 04:27:31 PM PDT 24 | 7339560000 ps | ||
| T2 | /workspace/coverage/default/26.prim_present_test.3956991234 | Aug 12 04:21:17 PM PDT 24 | Aug 12 04:22:52 PM PDT 24 | 13784460000 ps | ||
| T3 | /workspace/coverage/default/30.prim_present_test.665838878 | Aug 12 04:22:31 PM PDT 24 | Aug 12 04:23:16 PM PDT 24 | 5984860000 ps | ||
| T4 | /workspace/coverage/default/25.prim_present_test.707766677 | Aug 12 04:21:17 PM PDT 24 | Aug 12 04:22:05 PM PDT 24 | 7312900000 ps | ||
| T5 | /workspace/coverage/default/20.prim_present_test.1249851138 | Aug 12 04:24:41 PM PDT 24 | Aug 12 04:25:35 PM PDT 24 | 8077360000 ps | ||
| T6 | /workspace/coverage/default/14.prim_present_test.2935623389 | Aug 12 04:22:08 PM PDT 24 | Aug 12 04:22:59 PM PDT 24 | 6441180000 ps | ||
| T7 | /workspace/coverage/default/40.prim_present_test.616609009 | Aug 12 04:22:17 PM PDT 24 | Aug 12 04:23:27 PM PDT 24 | 9631700000 ps | ||
| T8 | /workspace/coverage/default/9.prim_present_test.3317018532 | Aug 12 04:23:25 PM PDT 24 | Aug 12 04:24:43 PM PDT 24 | 13985340000 ps | ||
| T9 | /workspace/coverage/default/48.prim_present_test.3153662444 | Aug 12 04:22:17 PM PDT 24 | Aug 12 04:23:07 PM PDT 24 | 6882620000 ps | ||
| T10 | /workspace/coverage/default/39.prim_present_test.1555751774 | Aug 12 04:21:26 PM PDT 24 | Aug 12 04:22:57 PM PDT 24 | 12341100000 ps | ||
| T11 | /workspace/coverage/default/32.prim_present_test.307247972 | Aug 12 04:21:16 PM PDT 24 | Aug 12 04:22:00 PM PDT 24 | 6499460000 ps | ||
| T12 | /workspace/coverage/default/4.prim_present_test.1216472970 | Aug 12 04:26:41 PM PDT 24 | Aug 12 04:28:19 PM PDT 24 | 14858920000 ps | ||
| T13 | /workspace/coverage/default/3.prim_present_test.243004609 | Aug 12 04:26:11 PM PDT 24 | Aug 12 04:26:44 PM PDT 24 | 4922800000 ps | ||
| T14 | /workspace/coverage/default/47.prim_present_test.3160311018 | Aug 12 04:21:15 PM PDT 24 | Aug 12 04:21:52 PM PDT 24 | 5460960000 ps | ||
| T15 | /workspace/coverage/default/21.prim_present_test.3018472787 | Aug 12 04:26:53 PM PDT 24 | Aug 12 04:27:59 PM PDT 24 | 12391940000 ps | ||
| T16 | /workspace/coverage/default/17.prim_present_test.2695315013 | Aug 12 04:21:56 PM PDT 24 | Aug 12 04:22:58 PM PDT 24 | 8245380000 ps | ||
| T17 | /workspace/coverage/default/43.prim_present_test.3988573780 | Aug 12 04:22:17 PM PDT 24 | Aug 12 04:23:04 PM PDT 24 | 6252080000 ps | ||
| T18 | /workspace/coverage/default/35.prim_present_test.3223447836 | Aug 12 04:22:18 PM PDT 24 | Aug 12 04:23:40 PM PDT 24 | 13038600000 ps | ||
| T19 | /workspace/coverage/default/27.prim_present_test.2224710098 | Aug 12 04:22:16 PM PDT 24 | Aug 12 04:23:39 PM PDT 24 | 11848200000 ps | ||
| T20 | /workspace/coverage/default/37.prim_present_test.3530529667 | Aug 12 04:22:18 PM PDT 24 | Aug 12 04:23:24 PM PDT 24 | 8996200000 ps | ||
| T21 | /workspace/coverage/default/33.prim_present_test.3580790255 | Aug 12 04:22:17 PM PDT 24 | Aug 12 04:22:59 PM PDT 24 | 5509320000 ps | ||
| T22 | /workspace/coverage/default/46.prim_present_test.4234880267 | Aug 12 04:21:16 PM PDT 24 | Aug 12 04:22:46 PM PDT 24 | 14217840000 ps | ||
| T23 | /workspace/coverage/default/10.prim_present_test.3803023888 | Aug 12 04:23:48 PM PDT 24 | Aug 12 04:25:29 PM PDT 24 | 14441040000 ps | ||
| T24 | /workspace/coverage/default/29.prim_present_test.3238097292 | Aug 12 04:21:16 PM PDT 24 | Aug 12 04:21:41 PM PDT 24 | 3672880000 ps | ||
| T25 | /workspace/coverage/default/11.prim_present_test.1451550154 | Aug 12 04:24:07 PM PDT 24 | Aug 12 04:25:33 PM PDT 24 | 11275940000 ps | ||
| T26 | /workspace/coverage/default/12.prim_present_test.4091020491 | Aug 12 04:23:27 PM PDT 24 | Aug 12 04:23:54 PM PDT 24 | 4098200000 ps | ||
| T27 | /workspace/coverage/default/6.prim_present_test.3402076976 | Aug 12 04:24:46 PM PDT 24 | Aug 12 04:26:25 PM PDT 24 | 12073880000 ps | ||
| T28 | /workspace/coverage/default/0.prim_present_test.974380015 | Aug 12 04:23:03 PM PDT 24 | Aug 12 04:24:15 PM PDT 24 | 8291260000 ps | ||
| T29 | /workspace/coverage/default/42.prim_present_test.761650705 | Aug 12 04:23:01 PM PDT 24 | Aug 12 04:25:01 PM PDT 24 | 14517920000 ps | ||
| T30 | /workspace/coverage/default/15.prim_present_test.4033204448 | Aug 12 04:24:15 PM PDT 24 | Aug 12 04:25:44 PM PDT 24 | 11666540000 ps | ||
| T31 | /workspace/coverage/default/19.prim_present_test.4279849852 | Aug 12 04:21:48 PM PDT 24 | Aug 12 04:23:37 PM PDT 24 | 14346180000 ps | ||
| T32 | /workspace/coverage/default/18.prim_present_test.4264073312 | Aug 12 04:26:26 PM PDT 24 | Aug 12 04:27:23 PM PDT 24 | 6741260000 ps | ||
| T33 | /workspace/coverage/default/31.prim_present_test.497067579 | Aug 12 04:22:16 PM PDT 24 | Aug 12 04:23:45 PM PDT 24 | 12467580000 ps | ||
| T34 | /workspace/coverage/default/45.prim_present_test.4020201206 | Aug 12 04:21:16 PM PDT 24 | Aug 12 04:22:49 PM PDT 24 | 14904800000 ps | ||
| T35 | /workspace/coverage/default/41.prim_present_test.3647479673 | Aug 12 04:23:47 PM PDT 24 | Aug 12 04:24:53 PM PDT 24 | 9693700000 ps | ||
| T36 | /workspace/coverage/default/13.prim_present_test.2958319935 | Aug 12 04:26:57 PM PDT 24 | Aug 12 04:27:30 PM PDT 24 | 5361140000 ps | ||
| T37 | /workspace/coverage/default/24.prim_present_test.3579017654 | Aug 12 04:23:38 PM PDT 24 | Aug 12 04:24:55 PM PDT 24 | 10482340000 ps | ||
| T38 | /workspace/coverage/default/28.prim_present_test.507985090 | Aug 12 04:22:17 PM PDT 24 | Aug 12 04:23:33 PM PDT 24 | 10899600000 ps | ||
| T39 | /workspace/coverage/default/36.prim_present_test.114440223 | Aug 12 04:22:16 PM PDT 24 | Aug 12 04:23:57 PM PDT 24 | 14353620000 ps | ||
| T40 | /workspace/coverage/default/16.prim_present_test.3156958970 | Aug 12 04:26:24 PM PDT 24 | Aug 12 04:27:53 PM PDT 24 | 14729960000 ps | ||
| T41 | /workspace/coverage/default/1.prim_present_test.3025983249 | Aug 12 04:24:34 PM PDT 24 | Aug 12 04:25:48 PM PDT 24 | 9909460000 ps | ||
| T42 | /workspace/coverage/default/49.prim_present_test.3704429309 | Aug 12 04:25:19 PM PDT 24 | Aug 12 04:26:51 PM PDT 24 | 13134080000 ps | ||
| T43 | /workspace/coverage/default/44.prim_present_test.1783823551 | Aug 12 04:21:17 PM PDT 24 | Aug 12 04:22:02 PM PDT 24 | 6305400000 ps | ||
| T44 | /workspace/coverage/default/38.prim_present_test.3415859906 | Aug 12 04:26:32 PM PDT 24 | Aug 12 04:27:53 PM PDT 24 | 13346120000 ps | ||
| T45 | /workspace/coverage/default/7.prim_present_test.2038454526 | Aug 12 04:26:38 PM PDT 24 | Aug 12 04:27:35 PM PDT 24 | 8538640000 ps | ||
| T46 | /workspace/coverage/default/23.prim_present_test.1316771741 | Aug 12 04:23:28 PM PDT 24 | Aug 12 04:23:59 PM PDT 24 | 4196780000 ps | ||
| T47 | /workspace/coverage/default/34.prim_present_test.3803894859 | Aug 12 04:22:30 PM PDT 24 | Aug 12 04:23:46 PM PDT 24 | 9859240000 ps | ||
| T48 | /workspace/coverage/default/5.prim_present_test.4171906389 | Aug 12 04:27:11 PM PDT 24 | Aug 12 04:28:27 PM PDT 24 | 12721160000 ps | ||
| T49 | /workspace/coverage/default/2.prim_present_test.1183456276 | Aug 12 04:26:11 PM PDT 24 | Aug 12 04:27:39 PM PDT 24 | 14391440000 ps | ||
| T50 | /workspace/coverage/default/8.prim_present_test.3856318526 | Aug 12 04:23:47 PM PDT 24 | Aug 12 04:25:19 PM PDT 24 | 11186660000 ps |
| Test location | /workspace/coverage/default/14.prim_present_test.2935623389 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6441180000 ps |
| CPU time | 26.5 seconds |
| Started | Aug 12 04:22:08 PM PDT 24 |
| Finished | Aug 12 04:22:59 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-fc613550-1f0f-4139-8141-2d9a43482f28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935623389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2935623389 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.974380015 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8291260000 ps |
| CPU time | 37.19 seconds |
| Started | Aug 12 04:23:03 PM PDT 24 |
| Finished | Aug 12 04:24:15 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-41f04d8c-ea21-43ae-a212-0cf963b7c5bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974380015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.974380015 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3025983249 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9909460000 ps |
| CPU time | 39.17 seconds |
| Started | Aug 12 04:24:34 PM PDT 24 |
| Finished | Aug 12 04:25:48 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-f09c7891-8e75-412f-a3e4-03cd5af7b17c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025983249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3025983249 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3803023888 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14441040000 ps |
| CPU time | 54.08 seconds |
| Started | Aug 12 04:23:48 PM PDT 24 |
| Finished | Aug 12 04:25:29 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-f01706c9-eec6-4e78-8225-4a2ffa5e19f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803023888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3803023888 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1451550154 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11275940000 ps |
| CPU time | 45.33 seconds |
| Started | Aug 12 04:24:07 PM PDT 24 |
| Finished | Aug 12 04:25:33 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-ec177b34-b7a0-4710-aa5d-5611e1923cd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451550154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1451550154 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4091020491 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4098200000 ps |
| CPU time | 14.23 seconds |
| Started | Aug 12 04:23:27 PM PDT 24 |
| Finished | Aug 12 04:23:54 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-afae8a1a-6e98-4af3-9a72-95a28796689c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091020491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4091020491 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2958319935 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5361140000 ps |
| CPU time | 18.05 seconds |
| Started | Aug 12 04:26:57 PM PDT 24 |
| Finished | Aug 12 04:27:30 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-528b2612-b454-4bff-9a2d-a47a4202f565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958319935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2958319935 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.4033204448 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11666540000 ps |
| CPU time | 46.77 seconds |
| Started | Aug 12 04:24:15 PM PDT 24 |
| Finished | Aug 12 04:25:44 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-e40a2047-3fcd-4b8c-9ee8-62008958f66d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033204448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.4033204448 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3156958970 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14729960000 ps |
| CPU time | 47.15 seconds |
| Started | Aug 12 04:26:24 PM PDT 24 |
| Finished | Aug 12 04:27:53 PM PDT 24 |
| Peak memory | 144080 kb |
| Host | smart-6561f279-9874-43b1-a04d-c2da6edb7c0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156958970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3156958970 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2695315013 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8245380000 ps |
| CPU time | 32.14 seconds |
| Started | Aug 12 04:21:56 PM PDT 24 |
| Finished | Aug 12 04:22:58 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-ff4e78f2-ce4b-419a-a00e-5c49f8eaafe8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695315013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2695315013 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.4264073312 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6741260000 ps |
| CPU time | 29.4 seconds |
| Started | Aug 12 04:26:26 PM PDT 24 |
| Finished | Aug 12 04:27:23 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-f5317538-cbf1-4a27-84c8-892668c27a63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264073312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.4264073312 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.4279849852 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14346180000 ps |
| CPU time | 56.83 seconds |
| Started | Aug 12 04:21:48 PM PDT 24 |
| Finished | Aug 12 04:23:37 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-3641fa5d-2379-4245-b96c-74df9e10ea25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4279849852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.4279849852 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1183456276 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14391440000 ps |
| CPU time | 48.25 seconds |
| Started | Aug 12 04:26:11 PM PDT 24 |
| Finished | Aug 12 04:27:39 PM PDT 24 |
| Peak memory | 143328 kb |
| Host | smart-a6f7d0b6-48d7-4db8-afbf-3798bee96913 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183456276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1183456276 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1249851138 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8077360000 ps |
| CPU time | 28.7 seconds |
| Started | Aug 12 04:24:41 PM PDT 24 |
| Finished | Aug 12 04:25:35 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-374f98ee-a855-4535-803c-145462e6e8cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249851138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1249851138 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3018472787 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12391940000 ps |
| CPU time | 36.95 seconds |
| Started | Aug 12 04:26:53 PM PDT 24 |
| Finished | Aug 12 04:27:59 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-22d48ada-fec0-4bdf-93aa-b8251ddee9bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018472787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3018472787 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1508476422 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7339560000 ps |
| CPU time | 26.92 seconds |
| Started | Aug 12 04:26:40 PM PDT 24 |
| Finished | Aug 12 04:27:31 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-02d2004a-c8e1-4799-ac8e-da63132000ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1508476422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1508476422 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1316771741 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4196780000 ps |
| CPU time | 16.25 seconds |
| Started | Aug 12 04:23:28 PM PDT 24 |
| Finished | Aug 12 04:23:59 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-5ab11f66-1d24-4246-84d7-1b72893becea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316771741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1316771741 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3579017654 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10482340000 ps |
| CPU time | 41.3 seconds |
| Started | Aug 12 04:23:38 PM PDT 24 |
| Finished | Aug 12 04:24:55 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-86257298-453a-43ad-ba79-d283ae147659 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579017654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3579017654 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.707766677 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7312900000 ps |
| CPU time | 25.82 seconds |
| Started | Aug 12 04:21:17 PM PDT 24 |
| Finished | Aug 12 04:22:05 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-4679c701-5113-4423-800a-dde1a0576a40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707766677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.707766677 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3956991234 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13784460000 ps |
| CPU time | 50.65 seconds |
| Started | Aug 12 04:21:17 PM PDT 24 |
| Finished | Aug 12 04:22:52 PM PDT 24 |
| Peak memory | 144508 kb |
| Host | smart-b121941c-3e4c-44cf-b8a3-f64a88bc915a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956991234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3956991234 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2224710098 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11848200000 ps |
| CPU time | 43.95 seconds |
| Started | Aug 12 04:22:16 PM PDT 24 |
| Finished | Aug 12 04:23:39 PM PDT 24 |
| Peak memory | 143120 kb |
| Host | smart-6067bd17-9104-4b7d-9246-965acedd25ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224710098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2224710098 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.507985090 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10899600000 ps |
| CPU time | 40.55 seconds |
| Started | Aug 12 04:22:17 PM PDT 24 |
| Finished | Aug 12 04:23:33 PM PDT 24 |
| Peak memory | 144524 kb |
| Host | smart-8cd23627-c082-4a0b-9954-d1153aba9a34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507985090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.507985090 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3238097292 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3672880000 ps |
| CPU time | 13.54 seconds |
| Started | Aug 12 04:21:16 PM PDT 24 |
| Finished | Aug 12 04:21:41 PM PDT 24 |
| Peak memory | 144536 kb |
| Host | smart-489f7376-6367-4fff-ab3f-0a2a70396c62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238097292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3238097292 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.243004609 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4922800000 ps |
| CPU time | 17.86 seconds |
| Started | Aug 12 04:26:11 PM PDT 24 |
| Finished | Aug 12 04:26:44 PM PDT 24 |
| Peak memory | 143200 kb |
| Host | smart-42b29bfe-3794-4570-bf5a-16d8c8be2275 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243004609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.243004609 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.665838878 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5984860000 ps |
| CPU time | 23.71 seconds |
| Started | Aug 12 04:22:31 PM PDT 24 |
| Finished | Aug 12 04:23:16 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-98eaae57-8f4f-4d34-a50a-1764ac5f40a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665838878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.665838878 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.497067579 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12467580000 ps |
| CPU time | 46.72 seconds |
| Started | Aug 12 04:22:16 PM PDT 24 |
| Finished | Aug 12 04:23:45 PM PDT 24 |
| Peak memory | 143904 kb |
| Host | smart-2afb69f1-78e9-4458-b7d2-4088256ebfc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497067579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.497067579 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.307247972 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6499460000 ps |
| CPU time | 23.54 seconds |
| Started | Aug 12 04:21:16 PM PDT 24 |
| Finished | Aug 12 04:22:00 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-06a787d6-3870-4926-9dce-bd10bb52e68c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307247972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.307247972 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3580790255 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5509320000 ps |
| CPU time | 21.56 seconds |
| Started | Aug 12 04:22:17 PM PDT 24 |
| Finished | Aug 12 04:22:59 PM PDT 24 |
| Peak memory | 142532 kb |
| Host | smart-2b70d213-ec13-4c8a-a6db-06078a361fff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580790255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3580790255 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3803894859 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9859240000 ps |
| CPU time | 39.49 seconds |
| Started | Aug 12 04:22:30 PM PDT 24 |
| Finished | Aug 12 04:23:46 PM PDT 24 |
| Peak memory | 144860 kb |
| Host | smart-4399162e-3e55-48fa-ac4a-29f7d5fbe313 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803894859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3803894859 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3223447836 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13038600000 ps |
| CPU time | 44.69 seconds |
| Started | Aug 12 04:22:18 PM PDT 24 |
| Finished | Aug 12 04:23:40 PM PDT 24 |
| Peak memory | 143688 kb |
| Host | smart-f6b78ea9-4690-4b84-8c5a-5268df01a20f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223447836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3223447836 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.114440223 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 14353620000 ps |
| CPU time | 53.32 seconds |
| Started | Aug 12 04:22:16 PM PDT 24 |
| Finished | Aug 12 04:23:57 PM PDT 24 |
| Peak memory | 142556 kb |
| Host | smart-e955be51-744b-4663-a096-d360bdd44289 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114440223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.114440223 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3530529667 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8996200000 ps |
| CPU time | 34.49 seconds |
| Started | Aug 12 04:22:18 PM PDT 24 |
| Finished | Aug 12 04:23:24 PM PDT 24 |
| Peak memory | 144388 kb |
| Host | smart-66a33921-22e3-4261-929d-11f31be7e537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3530529667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3530529667 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3415859906 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13346120000 ps |
| CPU time | 44.02 seconds |
| Started | Aug 12 04:26:32 PM PDT 24 |
| Finished | Aug 12 04:27:53 PM PDT 24 |
| Peak memory | 144740 kb |
| Host | smart-43dcf871-3700-4b55-b407-b30de88bb934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415859906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3415859906 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1555751774 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12341100000 ps |
| CPU time | 47.45 seconds |
| Started | Aug 12 04:21:26 PM PDT 24 |
| Finished | Aug 12 04:22:57 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-e16bb762-80e5-46f2-8d8f-e22f0a4721da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1555751774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1555751774 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1216472970 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 14858920000 ps |
| CPU time | 52.35 seconds |
| Started | Aug 12 04:26:41 PM PDT 24 |
| Finished | Aug 12 04:28:19 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-09b34880-a8cf-4a6a-9554-5b007bea9d21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216472970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1216472970 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.616609009 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9631700000 ps |
| CPU time | 36.7 seconds |
| Started | Aug 12 04:22:17 PM PDT 24 |
| Finished | Aug 12 04:23:27 PM PDT 24 |
| Peak memory | 142848 kb |
| Host | smart-9c899329-15ed-4a6d-9534-55fee9cfe96e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616609009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.616609009 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3647479673 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9693700000 ps |
| CPU time | 35.63 seconds |
| Started | Aug 12 04:23:47 PM PDT 24 |
| Finished | Aug 12 04:24:53 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-96e002a2-92b0-4b2d-9269-ee68f2a7cf8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647479673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3647479673 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.761650705 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14517920000 ps |
| CPU time | 62.45 seconds |
| Started | Aug 12 04:23:01 PM PDT 24 |
| Finished | Aug 12 04:25:01 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-80d803d6-8635-4e0e-8e8d-3404a8e6ec5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761650705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.761650705 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3988573780 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6252080000 ps |
| CPU time | 24.15 seconds |
| Started | Aug 12 04:22:17 PM PDT 24 |
| Finished | Aug 12 04:23:04 PM PDT 24 |
| Peak memory | 142576 kb |
| Host | smart-132c72e1-ab03-4b5f-885e-913534640b85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3988573780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3988573780 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1783823551 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6305400000 ps |
| CPU time | 23.6 seconds |
| Started | Aug 12 04:21:17 PM PDT 24 |
| Finished | Aug 12 04:22:02 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-0a617ea6-b8a7-4db2-bb6c-aa525103c897 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783823551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1783823551 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4020201206 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 14904800000 ps |
| CPU time | 50.32 seconds |
| Started | Aug 12 04:21:16 PM PDT 24 |
| Finished | Aug 12 04:22:49 PM PDT 24 |
| Peak memory | 144680 kb |
| Host | smart-8552b0b4-72aa-4ed0-a1b6-5f86a77a2a6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020201206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4020201206 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4234880267 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 14217840000 ps |
| CPU time | 48.84 seconds |
| Started | Aug 12 04:21:16 PM PDT 24 |
| Finished | Aug 12 04:22:46 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-b6b4e59e-dd0f-4025-ba1a-ecaa83dfbc52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4234880267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4234880267 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3160311018 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5460960000 ps |
| CPU time | 19.56 seconds |
| Started | Aug 12 04:21:15 PM PDT 24 |
| Finished | Aug 12 04:21:52 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-c68a2ddf-75ce-458d-b316-be29478a20cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160311018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3160311018 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3153662444 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6882620000 ps |
| CPU time | 25.76 seconds |
| Started | Aug 12 04:22:17 PM PDT 24 |
| Finished | Aug 12 04:23:07 PM PDT 24 |
| Peak memory | 142976 kb |
| Host | smart-185be26d-8973-4f03-bd10-f8f6955956ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153662444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3153662444 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3704429309 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13134080000 ps |
| CPU time | 49.01 seconds |
| Started | Aug 12 04:25:19 PM PDT 24 |
| Finished | Aug 12 04:26:51 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-4402337e-bdda-4594-aa33-aa2f49158ccb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3704429309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3704429309 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.4171906389 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12721160000 ps |
| CPU time | 41.3 seconds |
| Started | Aug 12 04:27:11 PM PDT 24 |
| Finished | Aug 12 04:28:27 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-f4b75d17-d950-4a02-a186-3c4b3a2e72f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171906389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.4171906389 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3402076976 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12073880000 ps |
| CPU time | 51.32 seconds |
| Started | Aug 12 04:24:46 PM PDT 24 |
| Finished | Aug 12 04:26:25 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-db1e6e6c-e4ae-48a3-8caa-dd92bad272ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3402076976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3402076976 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2038454526 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8538640000 ps |
| CPU time | 30.39 seconds |
| Started | Aug 12 04:26:38 PM PDT 24 |
| Finished | Aug 12 04:27:35 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-66755463-3c31-45ef-bae0-feaa0bb46204 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038454526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2038454526 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3856318526 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11186660000 ps |
| CPU time | 47.86 seconds |
| Started | Aug 12 04:23:47 PM PDT 24 |
| Finished | Aug 12 04:25:19 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-8ed2a9c8-263b-4cb8-9c6a-2d7ebdcef2fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856318526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3856318526 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3317018532 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13985340000 ps |
| CPU time | 41.31 seconds |
| Started | Aug 12 04:23:25 PM PDT 24 |
| Finished | Aug 12 04:24:43 PM PDT 24 |
| Peak memory | 144212 kb |
| Host | smart-f1ef1434-3d62-482d-a287-e1b9b81e2240 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317018532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3317018532 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |