| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.3286078036 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2516864378 |
| /workspace/coverage/default/1.prim_present_test.3666483047 |
| /workspace/coverage/default/11.prim_present_test.758755571 |
| /workspace/coverage/default/12.prim_present_test.1795076019 |
| /workspace/coverage/default/13.prim_present_test.1463771814 |
| /workspace/coverage/default/14.prim_present_test.1968441943 |
| /workspace/coverage/default/15.prim_present_test.2240768097 |
| /workspace/coverage/default/16.prim_present_test.1445500630 |
| /workspace/coverage/default/17.prim_present_test.1711177902 |
| /workspace/coverage/default/18.prim_present_test.1895754552 |
| /workspace/coverage/default/19.prim_present_test.1078242039 |
| /workspace/coverage/default/2.prim_present_test.402756855 |
| /workspace/coverage/default/20.prim_present_test.2342059249 |
| /workspace/coverage/default/21.prim_present_test.310361043 |
| /workspace/coverage/default/22.prim_present_test.493606856 |
| /workspace/coverage/default/23.prim_present_test.2814470145 |
| /workspace/coverage/default/24.prim_present_test.424502531 |
| /workspace/coverage/default/25.prim_present_test.1217552065 |
| /workspace/coverage/default/26.prim_present_test.1748879451 |
| /workspace/coverage/default/27.prim_present_test.1524655710 |
| /workspace/coverage/default/28.prim_present_test.3237093471 |
| /workspace/coverage/default/29.prim_present_test.2310209139 |
| /workspace/coverage/default/3.prim_present_test.3695791482 |
| /workspace/coverage/default/30.prim_present_test.3307335989 |
| /workspace/coverage/default/31.prim_present_test.2486384706 |
| /workspace/coverage/default/32.prim_present_test.4055985841 |
| /workspace/coverage/default/33.prim_present_test.944321288 |
| /workspace/coverage/default/34.prim_present_test.1547710916 |
| /workspace/coverage/default/35.prim_present_test.2604472875 |
| /workspace/coverage/default/36.prim_present_test.2035290455 |
| /workspace/coverage/default/37.prim_present_test.1994848067 |
| /workspace/coverage/default/38.prim_present_test.499158761 |
| /workspace/coverage/default/39.prim_present_test.1205020979 |
| /workspace/coverage/default/4.prim_present_test.2974789009 |
| /workspace/coverage/default/40.prim_present_test.853351709 |
| /workspace/coverage/default/41.prim_present_test.2829103153 |
| /workspace/coverage/default/42.prim_present_test.879262447 |
| /workspace/coverage/default/43.prim_present_test.3924060365 |
| /workspace/coverage/default/44.prim_present_test.939962979 |
| /workspace/coverage/default/45.prim_present_test.3948072034 |
| /workspace/coverage/default/46.prim_present_test.2561779454 |
| /workspace/coverage/default/47.prim_present_test.2866055023 |
| /workspace/coverage/default/48.prim_present_test.2469358743 |
| /workspace/coverage/default/49.prim_present_test.1756376905 |
| /workspace/coverage/default/5.prim_present_test.2819345900 |
| /workspace/coverage/default/6.prim_present_test.474953720 |
| /workspace/coverage/default/7.prim_present_test.1501665453 |
| /workspace/coverage/default/8.prim_present_test.1539620096 |
| /workspace/coverage/default/9.prim_present_test.481337945 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_present_test.3286078036 | Aug 13 04:45:39 PM PDT 24 | Aug 13 04:46:50 PM PDT 24 | 11339800000 ps | ||
| T2 | /workspace/coverage/default/3.prim_present_test.3695791482 | Aug 13 04:45:40 PM PDT 24 | Aug 13 04:46:27 PM PDT 24 | 6568280000 ps | ||
| T3 | /workspace/coverage/default/42.prim_present_test.879262447 | Aug 13 04:46:03 PM PDT 24 | Aug 13 04:47:04 PM PDT 24 | 7168440000 ps | ||
| T4 | /workspace/coverage/default/22.prim_present_test.493606856 | Aug 13 04:45:49 PM PDT 24 | Aug 13 04:47:30 PM PDT 24 | 12849500000 ps | ||
| T5 | /workspace/coverage/default/11.prim_present_test.758755571 | Aug 13 04:45:40 PM PDT 24 | Aug 13 04:46:18 PM PDT 24 | 5021380000 ps | ||
| T6 | /workspace/coverage/default/2.prim_present_test.402756855 | Aug 13 04:45:40 PM PDT 24 | Aug 13 04:47:30 PM PDT 24 | 14230240000 ps | ||
| T7 | /workspace/coverage/default/32.prim_present_test.4055985841 | Aug 13 04:45:54 PM PDT 24 | Aug 13 04:46:52 PM PDT 24 | 8980700000 ps | ||
| T8 | /workspace/coverage/default/37.prim_present_test.1994848067 | Aug 13 04:46:06 PM PDT 24 | Aug 13 04:47:01 PM PDT 24 | 6996080000 ps | ||
| T9 | /workspace/coverage/default/31.prim_present_test.2486384706 | Aug 13 04:45:55 PM PDT 24 | Aug 13 04:47:38 PM PDT 24 | 13757800000 ps | ||
| T10 | /workspace/coverage/default/36.prim_present_test.2035290455 | Aug 13 04:46:05 PM PDT 24 | Aug 13 04:47:41 PM PDT 24 | 13540800000 ps | ||
| T11 | /workspace/coverage/default/4.prim_present_test.2974789009 | Aug 13 04:45:41 PM PDT 24 | Aug 13 04:47:02 PM PDT 24 | 13275440000 ps | ||
| T12 | /workspace/coverage/default/14.prim_present_test.1968441943 | Aug 13 04:45:48 PM PDT 24 | Aug 13 04:46:37 PM PDT 24 | 7622280000 ps | ||
| T13 | /workspace/coverage/default/44.prim_present_test.939962979 | Aug 13 04:46:01 PM PDT 24 | Aug 13 04:46:49 PM PDT 24 | 8135020000 ps | ||
| T14 | /workspace/coverage/default/33.prim_present_test.944321288 | Aug 13 04:45:54 PM PDT 24 | Aug 13 04:46:43 PM PDT 24 | 5893100000 ps | ||
| T15 | /workspace/coverage/default/49.prim_present_test.1756376905 | Aug 13 04:46:04 PM PDT 24 | Aug 13 04:46:47 PM PDT 24 | 6256420000 ps | ||
| T16 | /workspace/coverage/default/21.prim_present_test.310361043 | Aug 13 04:45:51 PM PDT 24 | Aug 13 04:47:05 PM PDT 24 | 9569080000 ps | ||
| T17 | /workspace/coverage/default/13.prim_present_test.1463771814 | Aug 13 04:45:42 PM PDT 24 | Aug 13 04:46:14 PM PDT 24 | 4123620000 ps | ||
| T18 | /workspace/coverage/default/5.prim_present_test.2819345900 | Aug 13 04:45:42 PM PDT 24 | Aug 13 04:46:44 PM PDT 24 | 8325980000 ps | ||
| T19 | /workspace/coverage/default/38.prim_present_test.499158761 | Aug 13 04:46:03 PM PDT 24 | Aug 13 04:47:09 PM PDT 24 | 10303160000 ps | ||
| T20 | /workspace/coverage/default/41.prim_present_test.2829103153 | Aug 13 04:46:00 PM PDT 24 | Aug 13 04:47:30 PM PDT 24 | 13988440000 ps | ||
| T21 | /workspace/coverage/default/8.prim_present_test.1539620096 | Aug 13 04:45:41 PM PDT 24 | Aug 13 04:46:17 PM PDT 24 | 5236520000 ps | ||
| T22 | /workspace/coverage/default/39.prim_present_test.1205020979 | Aug 13 04:46:02 PM PDT 24 | Aug 13 04:47:46 PM PDT 24 | 14311460000 ps | ||
| T23 | /workspace/coverage/default/35.prim_present_test.2604472875 | Aug 13 04:46:02 PM PDT 24 | Aug 13 04:46:53 PM PDT 24 | 8482220000 ps | ||
| T24 | /workspace/coverage/default/20.prim_present_test.2342059249 | Aug 13 04:45:47 PM PDT 24 | Aug 13 04:47:12 PM PDT 24 | 12988380000 ps | ||
| T25 | /workspace/coverage/default/34.prim_present_test.1547710916 | Aug 13 04:45:54 PM PDT 24 | Aug 13 04:47:12 PM PDT 24 | 12654200000 ps | ||
| T26 | /workspace/coverage/default/24.prim_present_test.424502531 | Aug 13 04:45:47 PM PDT 24 | Aug 13 04:47:18 PM PDT 24 | 14250080000 ps | ||
| T27 | /workspace/coverage/default/15.prim_present_test.2240768097 | Aug 13 04:45:47 PM PDT 24 | Aug 13 04:47:53 PM PDT 24 | 14855200000 ps | ||
| T28 | /workspace/coverage/default/12.prim_present_test.1795076019 | Aug 13 04:45:41 PM PDT 24 | Aug 13 04:46:26 PM PDT 24 | 5349980000 ps | ||
| T29 | /workspace/coverage/default/27.prim_present_test.1524655710 | Aug 13 04:45:56 PM PDT 24 | Aug 13 04:46:34 PM PDT 24 | 5658120000 ps | ||
| T30 | /workspace/coverage/default/47.prim_present_test.2866055023 | Aug 13 04:46:02 PM PDT 24 | Aug 13 04:47:36 PM PDT 24 | 12373340000 ps | ||
| T31 | /workspace/coverage/default/6.prim_present_test.474953720 | Aug 13 04:45:40 PM PDT 24 | Aug 13 04:46:31 PM PDT 24 | 7002280000 ps | ||
| T32 | /workspace/coverage/default/1.prim_present_test.3666483047 | Aug 13 04:45:33 PM PDT 24 | Aug 13 04:46:54 PM PDT 24 | 12613280000 ps | ||
| T33 | /workspace/coverage/default/18.prim_present_test.1895754552 | Aug 13 04:45:50 PM PDT 24 | Aug 13 04:47:17 PM PDT 24 | 11151320000 ps | ||
| T34 | /workspace/coverage/default/25.prim_present_test.1217552065 | Aug 13 04:45:54 PM PDT 24 | Aug 13 04:46:31 PM PDT 24 | 5835440000 ps | ||
| T35 | /workspace/coverage/default/26.prim_present_test.1748879451 | Aug 13 04:45:54 PM PDT 24 | Aug 13 04:46:51 PM PDT 24 | 9016660000 ps | ||
| T36 | /workspace/coverage/default/43.prim_present_test.3924060365 | Aug 13 04:46:06 PM PDT 24 | Aug 13 04:46:31 PM PDT 24 | 3124180000 ps | ||
| T37 | /workspace/coverage/default/29.prim_present_test.2310209139 | Aug 13 04:45:54 PM PDT 24 | Aug 13 04:46:59 PM PDT 24 | 9127640000 ps | ||
| T38 | /workspace/coverage/default/23.prim_present_test.2814470145 | Aug 13 04:45:47 PM PDT 24 | Aug 13 04:47:11 PM PDT 24 | 11350960000 ps | ||
| T39 | /workspace/coverage/default/7.prim_present_test.1501665453 | Aug 13 04:45:42 PM PDT 24 | Aug 13 04:46:18 PM PDT 24 | 4607220000 ps | ||
| T40 | /workspace/coverage/default/46.prim_present_test.2561779454 | Aug 13 04:46:06 PM PDT 24 | Aug 13 04:47:22 PM PDT 24 | 10000600000 ps | ||
| T41 | /workspace/coverage/default/0.prim_present_test.2516864378 | Aug 13 04:45:42 PM PDT 24 | Aug 13 04:46:27 PM PDT 24 | 7951500000 ps | ||
| T42 | /workspace/coverage/default/9.prim_present_test.481337945 | Aug 13 04:45:41 PM PDT 24 | Aug 13 04:46:13 PM PDT 24 | 4417500000 ps | ||
| T43 | /workspace/coverage/default/16.prim_present_test.1445500630 | Aug 13 04:45:51 PM PDT 24 | Aug 13 04:47:37 PM PDT 24 | 13946900000 ps | ||
| T44 | /workspace/coverage/default/40.prim_present_test.853351709 | Aug 13 04:46:03 PM PDT 24 | Aug 13 04:47:00 PM PDT 24 | 8086040000 ps | ||
| T45 | /workspace/coverage/default/19.prim_present_test.1078242039 | Aug 13 04:45:47 PM PDT 24 | Aug 13 04:46:27 PM PDT 24 | 4382160000 ps | ||
| T46 | /workspace/coverage/default/45.prim_present_test.3948072034 | Aug 13 04:46:04 PM PDT 24 | Aug 13 04:46:40 PM PDT 24 | 6067940000 ps | ||
| T47 | /workspace/coverage/default/28.prim_present_test.3237093471 | Aug 13 04:45:54 PM PDT 24 | Aug 13 04:46:23 PM PDT 24 | 3917780000 ps | ||
| T48 | /workspace/coverage/default/17.prim_present_test.1711177902 | Aug 13 04:45:48 PM PDT 24 | Aug 13 04:46:27 PM PDT 24 | 5060440000 ps | ||
| T49 | /workspace/coverage/default/48.prim_present_test.2469358743 | Aug 13 04:46:01 PM PDT 24 | Aug 13 04:46:58 PM PDT 24 | 9293800000 ps | ||
| T50 | /workspace/coverage/default/30.prim_present_test.3307335989 | Aug 13 04:45:55 PM PDT 24 | Aug 13 04:46:50 PM PDT 24 | 8458040000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.3286078036 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11339800000 ps |
| CPU time | 38 seconds |
| Started | Aug 13 04:45:39 PM PDT 24 |
| Finished | Aug 13 04:46:50 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-de11f257-ab33-4860-bc4d-a85ad86ecbf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3286078036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3286078036 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2516864378 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 7951500000 ps |
| CPU time | 23.89 seconds |
| Started | Aug 13 04:45:42 PM PDT 24 |
| Finished | Aug 13 04:46:27 PM PDT 24 |
| Peak memory | 144184 kb |
| Host | smart-685ad9cf-e32c-4296-9f32-4f13e2a00cb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516864378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2516864378 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3666483047 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12613280000 ps |
| CPU time | 42.91 seconds |
| Started | Aug 13 04:45:33 PM PDT 24 |
| Finished | Aug 13 04:46:54 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-eb4009cc-eaa8-46b1-9357-9d323ebaa8b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666483047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3666483047 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.758755571 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5021380000 ps |
| CPU time | 19.89 seconds |
| Started | Aug 13 04:45:40 PM PDT 24 |
| Finished | Aug 13 04:46:18 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-e5513913-c2f9-4b43-a03a-ea7a697aec61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758755571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.758755571 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1795076019 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5349980000 ps |
| CPU time | 22.8 seconds |
| Started | Aug 13 04:45:41 PM PDT 24 |
| Finished | Aug 13 04:46:26 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-45e3b9d0-d615-49fb-8769-f3963804ca34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795076019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1795076019 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1463771814 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4123620000 ps |
| CPU time | 17.05 seconds |
| Started | Aug 13 04:45:42 PM PDT 24 |
| Finished | Aug 13 04:46:14 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-cb42320a-ea72-4a61-b416-b62d48c5aaa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463771814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1463771814 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1968441943 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7622280000 ps |
| CPU time | 25.54 seconds |
| Started | Aug 13 04:45:48 PM PDT 24 |
| Finished | Aug 13 04:46:37 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-f0293eb4-e5aa-4529-b41a-5d4a0effa991 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968441943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1968441943 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2240768097 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14855200000 ps |
| CPU time | 64.17 seconds |
| Started | Aug 13 04:45:47 PM PDT 24 |
| Finished | Aug 13 04:47:53 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-28ffac72-cf03-441a-a8d2-da90decf57ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240768097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2240768097 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1445500630 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13946900000 ps |
| CPU time | 53.9 seconds |
| Started | Aug 13 04:45:51 PM PDT 24 |
| Finished | Aug 13 04:47:37 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-c496e08c-ed02-4398-8991-8e0f0bb2a1d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1445500630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1445500630 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1711177902 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5060440000 ps |
| CPU time | 19.95 seconds |
| Started | Aug 13 04:45:48 PM PDT 24 |
| Finished | Aug 13 04:46:27 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-abe06370-7cc7-4f2b-b11b-495f2aa56a71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711177902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1711177902 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1895754552 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11151320000 ps |
| CPU time | 43.76 seconds |
| Started | Aug 13 04:45:50 PM PDT 24 |
| Finished | Aug 13 04:47:17 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-f7da9888-d15b-4033-b115-5ffc164d5c96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1895754552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1895754552 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1078242039 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4382160000 ps |
| CPU time | 20.07 seconds |
| Started | Aug 13 04:45:47 PM PDT 24 |
| Finished | Aug 13 04:46:27 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-77625872-1431-4774-8161-56fb97f7176c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078242039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1078242039 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.402756855 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14230240000 ps |
| CPU time | 55.87 seconds |
| Started | Aug 13 04:45:40 PM PDT 24 |
| Finished | Aug 13 04:47:30 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-63d7fbce-6501-4ca3-a3af-4abb21eff60a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402756855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.402756855 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2342059249 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12988380000 ps |
| CPU time | 45 seconds |
| Started | Aug 13 04:45:47 PM PDT 24 |
| Finished | Aug 13 04:47:12 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-89b3f489-f9b4-4dc4-82d0-92e42f7e07be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2342059249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2342059249 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.310361043 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9569080000 ps |
| CPU time | 37.74 seconds |
| Started | Aug 13 04:45:51 PM PDT 24 |
| Finished | Aug 13 04:47:05 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-bdfa0cd5-4c67-4b9a-ae0f-f0d75b990ef4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310361043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.310361043 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.493606856 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12849500000 ps |
| CPU time | 51.05 seconds |
| Started | Aug 13 04:45:49 PM PDT 24 |
| Finished | Aug 13 04:47:30 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-e38fefef-c5e7-4dfa-ab3b-7294beb51ac2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493606856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.493606856 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2814470145 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11350960000 ps |
| CPU time | 43.53 seconds |
| Started | Aug 13 04:45:47 PM PDT 24 |
| Finished | Aug 13 04:47:11 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-7dd27d70-03d2-4010-ac94-253e464d1af1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814470145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2814470145 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.424502531 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14250080000 ps |
| CPU time | 48.64 seconds |
| Started | Aug 13 04:45:47 PM PDT 24 |
| Finished | Aug 13 04:47:18 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-2baf9a28-01c5-45bf-aa20-fae0a1f4fcf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=424502531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.424502531 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1217552065 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5835440000 ps |
| CPU time | 20.14 seconds |
| Started | Aug 13 04:45:54 PM PDT 24 |
| Finished | Aug 13 04:46:31 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-7b983601-c60a-4528-b210-ac1201c88708 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217552065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1217552065 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1748879451 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9016660000 ps |
| CPU time | 30.54 seconds |
| Started | Aug 13 04:45:54 PM PDT 24 |
| Finished | Aug 13 04:46:51 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-aa3f8037-cfcc-4ca8-87e9-fef8489bf21f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1748879451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1748879451 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1524655710 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5658120000 ps |
| CPU time | 20.42 seconds |
| Started | Aug 13 04:45:56 PM PDT 24 |
| Finished | Aug 13 04:46:34 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-dd400a56-0ba4-4af7-9ef1-29f7d07bf871 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524655710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1524655710 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3237093471 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3917780000 ps |
| CPU time | 15.34 seconds |
| Started | Aug 13 04:45:54 PM PDT 24 |
| Finished | Aug 13 04:46:23 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-35cee627-2f4e-4f02-97e7-bde1528bd288 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237093471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3237093471 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2310209139 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9127640000 ps |
| CPU time | 34.18 seconds |
| Started | Aug 13 04:45:54 PM PDT 24 |
| Finished | Aug 13 04:46:59 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-6d6050b7-5e5f-4c18-9633-cf94ca0c2572 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310209139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2310209139 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3695791482 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6568280000 ps |
| CPU time | 24.93 seconds |
| Started | Aug 13 04:45:40 PM PDT 24 |
| Finished | Aug 13 04:46:27 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-9498276b-94a5-482b-9412-19c22c68809a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3695791482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3695791482 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3307335989 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8458040000 ps |
| CPU time | 28.47 seconds |
| Started | Aug 13 04:45:55 PM PDT 24 |
| Finished | Aug 13 04:46:50 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-e2c1b75f-2bd4-4284-89e6-3c7d6c52872b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307335989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3307335989 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2486384706 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13757800000 ps |
| CPU time | 53.94 seconds |
| Started | Aug 13 04:45:55 PM PDT 24 |
| Finished | Aug 13 04:47:38 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-e44d0725-23d5-4ec1-afb0-1f5b0ec1912a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2486384706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2486384706 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4055985841 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8980700000 ps |
| CPU time | 31.11 seconds |
| Started | Aug 13 04:45:54 PM PDT 24 |
| Finished | Aug 13 04:46:52 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-a7bfa978-fc49-4308-8c5b-fd0c1e339755 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055985841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4055985841 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.944321288 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5893100000 ps |
| CPU time | 25.12 seconds |
| Started | Aug 13 04:45:54 PM PDT 24 |
| Finished | Aug 13 04:46:43 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-cd963188-909f-4daa-b095-021704f5427f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944321288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.944321288 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1547710916 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12654200000 ps |
| CPU time | 41.61 seconds |
| Started | Aug 13 04:45:54 PM PDT 24 |
| Finished | Aug 13 04:47:12 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-4b1d6d50-8212-4998-b662-880ae4b991bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1547710916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1547710916 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2604472875 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8482220000 ps |
| CPU time | 27.3 seconds |
| Started | Aug 13 04:46:02 PM PDT 24 |
| Finished | Aug 13 04:46:53 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-228a7c3d-aff9-4cee-a55d-05413cad6eaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604472875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2604472875 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2035290455 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13540800000 ps |
| CPU time | 51.09 seconds |
| Started | Aug 13 04:46:05 PM PDT 24 |
| Finished | Aug 13 04:47:41 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-75ae83e4-6d43-4be6-8a49-06fe8b188629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2035290455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2035290455 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1994848067 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6996080000 ps |
| CPU time | 28.71 seconds |
| Started | Aug 13 04:46:06 PM PDT 24 |
| Finished | Aug 13 04:47:01 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-aaec28af-527e-4535-bd5b-43f78bb32d1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994848067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1994848067 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.499158761 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10303160000 ps |
| CPU time | 35.35 seconds |
| Started | Aug 13 04:46:03 PM PDT 24 |
| Finished | Aug 13 04:47:09 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-f42e4457-fe1c-446f-b431-953df4dbbd52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=499158761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.499158761 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1205020979 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 14311460000 ps |
| CPU time | 53.72 seconds |
| Started | Aug 13 04:46:02 PM PDT 24 |
| Finished | Aug 13 04:47:46 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-17330f9f-9b4c-4784-8f11-337b1a5587ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205020979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1205020979 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2974789009 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13275440000 ps |
| CPU time | 43.4 seconds |
| Started | Aug 13 04:45:41 PM PDT 24 |
| Finished | Aug 13 04:47:02 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-cf8a1677-3f1d-4abe-bf6b-334fcf398f95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2974789009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2974789009 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.853351709 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8086040000 ps |
| CPU time | 30 seconds |
| Started | Aug 13 04:46:03 PM PDT 24 |
| Finished | Aug 13 04:47:00 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-f325be19-a83c-4396-a808-ec8164d6b577 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853351709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.853351709 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2829103153 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 13988440000 ps |
| CPU time | 48.12 seconds |
| Started | Aug 13 04:46:00 PM PDT 24 |
| Finished | Aug 13 04:47:30 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-efca1ea1-c80e-455f-bda2-5a05b21ef8fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2829103153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2829103153 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.879262447 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7168440000 ps |
| CPU time | 30.56 seconds |
| Started | Aug 13 04:46:03 PM PDT 24 |
| Finished | Aug 13 04:47:04 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-d543361d-53d1-4d4f-990b-ed382b717d35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879262447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.879262447 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3924060365 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3124180000 ps |
| CPU time | 13.26 seconds |
| Started | Aug 13 04:46:06 PM PDT 24 |
| Finished | Aug 13 04:46:31 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-32e0a901-5d80-46a9-aae3-ca61ff9aed87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924060365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3924060365 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.939962979 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 8135020000 ps |
| CPU time | 26.09 seconds |
| Started | Aug 13 04:46:01 PM PDT 24 |
| Finished | Aug 13 04:46:49 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-86302524-879a-4343-afb9-c922f13dd006 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939962979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.939962979 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3948072034 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6067940000 ps |
| CPU time | 19.54 seconds |
| Started | Aug 13 04:46:04 PM PDT 24 |
| Finished | Aug 13 04:46:40 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-6870a415-373e-47c4-a978-a85d2f2ba9a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948072034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3948072034 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2561779454 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10000600000 ps |
| CPU time | 39.46 seconds |
| Started | Aug 13 04:46:06 PM PDT 24 |
| Finished | Aug 13 04:47:22 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-8f48f73b-4aad-4180-961c-0adf6156914b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2561779454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2561779454 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2866055023 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 12373340000 ps |
| CPU time | 48.3 seconds |
| Started | Aug 13 04:46:02 PM PDT 24 |
| Finished | Aug 13 04:47:36 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-1c76fe3e-e2b7-45a1-9d08-f2db0906ed94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2866055023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2866055023 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2469358743 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9293800000 ps |
| CPU time | 30.74 seconds |
| Started | Aug 13 04:46:01 PM PDT 24 |
| Finished | Aug 13 04:46:58 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-4bb1ca37-f0a9-4a6d-88a2-8a39cdea9125 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469358743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2469358743 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1756376905 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6256420000 ps |
| CPU time | 22.59 seconds |
| Started | Aug 13 04:46:04 PM PDT 24 |
| Finished | Aug 13 04:46:47 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-d34a9502-4d9a-4917-855c-9345e508166f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756376905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1756376905 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2819345900 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8325980000 ps |
| CPU time | 32.11 seconds |
| Started | Aug 13 04:45:42 PM PDT 24 |
| Finished | Aug 13 04:46:44 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-8cc48473-5c97-43bd-8633-086e1150f729 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819345900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2819345900 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.474953720 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7002280000 ps |
| CPU time | 26.04 seconds |
| Started | Aug 13 04:45:40 PM PDT 24 |
| Finished | Aug 13 04:46:31 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-b1a7c045-87eb-4669-8039-3aeb37284277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474953720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.474953720 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1501665453 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4607220000 ps |
| CPU time | 18.25 seconds |
| Started | Aug 13 04:45:42 PM PDT 24 |
| Finished | Aug 13 04:46:18 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-301f62c6-593d-4c92-9672-2e0687eb0622 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1501665453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1501665453 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1539620096 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5236520000 ps |
| CPU time | 19.37 seconds |
| Started | Aug 13 04:45:41 PM PDT 24 |
| Finished | Aug 13 04:46:17 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-6d658a1c-24a4-40be-8682-6505d9629f8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539620096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1539620096 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.481337945 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4417500000 ps |
| CPU time | 16.8 seconds |
| Started | Aug 13 04:45:41 PM PDT 24 |
| Finished | Aug 13 04:46:13 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-7f41cd42-07ea-4cd6-88ad-16ee42fa1d1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481337945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.481337945 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |