| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.586786669 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.4172798630 |
| /workspace/coverage/default/10.prim_present_test.3766260009 |
| /workspace/coverage/default/11.prim_present_test.1239170438 |
| /workspace/coverage/default/12.prim_present_test.1465503377 |
| /workspace/coverage/default/13.prim_present_test.4521913 |
| /workspace/coverage/default/14.prim_present_test.26403767 |
| /workspace/coverage/default/15.prim_present_test.2122010430 |
| /workspace/coverage/default/16.prim_present_test.2134307201 |
| /workspace/coverage/default/17.prim_present_test.3618142001 |
| /workspace/coverage/default/18.prim_present_test.2271371318 |
| /workspace/coverage/default/19.prim_present_test.3085656001 |
| /workspace/coverage/default/2.prim_present_test.3309419451 |
| /workspace/coverage/default/20.prim_present_test.2445266629 |
| /workspace/coverage/default/21.prim_present_test.560314529 |
| /workspace/coverage/default/22.prim_present_test.3806256340 |
| /workspace/coverage/default/23.prim_present_test.2779852787 |
| /workspace/coverage/default/24.prim_present_test.3458560949 |
| /workspace/coverage/default/25.prim_present_test.46556330 |
| /workspace/coverage/default/26.prim_present_test.3409027599 |
| /workspace/coverage/default/27.prim_present_test.3745544105 |
| /workspace/coverage/default/28.prim_present_test.2369583 |
| /workspace/coverage/default/29.prim_present_test.3177900614 |
| /workspace/coverage/default/3.prim_present_test.846201452 |
| /workspace/coverage/default/30.prim_present_test.2976888921 |
| /workspace/coverage/default/31.prim_present_test.2945526861 |
| /workspace/coverage/default/32.prim_present_test.3695509769 |
| /workspace/coverage/default/33.prim_present_test.2373421371 |
| /workspace/coverage/default/34.prim_present_test.389498899 |
| /workspace/coverage/default/35.prim_present_test.504822872 |
| /workspace/coverage/default/36.prim_present_test.2665832230 |
| /workspace/coverage/default/37.prim_present_test.800407081 |
| /workspace/coverage/default/38.prim_present_test.1001347618 |
| /workspace/coverage/default/39.prim_present_test.1292315356 |
| /workspace/coverage/default/4.prim_present_test.3963744269 |
| /workspace/coverage/default/40.prim_present_test.644074722 |
| /workspace/coverage/default/41.prim_present_test.387211283 |
| /workspace/coverage/default/42.prim_present_test.3771921373 |
| /workspace/coverage/default/43.prim_present_test.1843566671 |
| /workspace/coverage/default/44.prim_present_test.1931147717 |
| /workspace/coverage/default/45.prim_present_test.1518952590 |
| /workspace/coverage/default/46.prim_present_test.676531035 |
| /workspace/coverage/default/47.prim_present_test.933881979 |
| /workspace/coverage/default/48.prim_present_test.2278255504 |
| /workspace/coverage/default/49.prim_present_test.1387041019 |
| /workspace/coverage/default/5.prim_present_test.3588195272 |
| /workspace/coverage/default/6.prim_present_test.1994775925 |
| /workspace/coverage/default/7.prim_present_test.670394615 |
| /workspace/coverage/default/8.prim_present_test.3347081920 |
| /workspace/coverage/default/9.prim_present_test.2967145713 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/44.prim_present_test.1931147717 | Aug 14 04:33:50 PM PDT 24 | Aug 14 04:35:01 PM PDT 24 | 11903380000 ps | ||
| T2 | /workspace/coverage/default/11.prim_present_test.1239170438 | Aug 14 04:33:56 PM PDT 24 | Aug 14 04:34:40 PM PDT 24 | 7093420000 ps | ||
| T3 | /workspace/coverage/default/35.prim_present_test.504822872 | Aug 14 04:33:46 PM PDT 24 | Aug 14 04:34:20 PM PDT 24 | 5531640000 ps | ||
| T4 | /workspace/coverage/default/12.prim_present_test.1465503377 | Aug 14 04:33:43 PM PDT 24 | Aug 14 04:34:10 PM PDT 24 | 3662340000 ps | ||
| T5 | /workspace/coverage/default/46.prim_present_test.676531035 | Aug 14 04:34:11 PM PDT 24 | Aug 14 04:35:01 PM PDT 24 | 8110220000 ps | ||
| T6 | /workspace/coverage/default/21.prim_present_test.560314529 | Aug 14 04:33:42 PM PDT 24 | Aug 14 04:34:58 PM PDT 24 | 12360940000 ps | ||
| T7 | /workspace/coverage/default/47.prim_present_test.933881979 | Aug 14 04:33:34 PM PDT 24 | Aug 14 04:35:09 PM PDT 24 | 13682160000 ps | ||
| T8 | /workspace/coverage/default/0.prim_present_test.586786669 | Aug 14 04:33:40 PM PDT 24 | Aug 14 04:35:03 PM PDT 24 | 10618120000 ps | ||
| T9 | /workspace/coverage/default/16.prim_present_test.2134307201 | Aug 14 04:33:45 PM PDT 24 | Aug 14 04:35:16 PM PDT 24 | 11758920000 ps | ||
| T10 | /workspace/coverage/default/1.prim_present_test.4172798630 | Aug 14 04:33:43 PM PDT 24 | Aug 14 04:35:02 PM PDT 24 | 13217160000 ps | ||
| T11 | /workspace/coverage/default/19.prim_present_test.3085656001 | Aug 14 04:33:36 PM PDT 24 | Aug 14 04:35:00 PM PDT 24 | 13217780000 ps | ||
| T12 | /workspace/coverage/default/4.prim_present_test.3963744269 | Aug 14 04:33:45 PM PDT 24 | Aug 14 04:34:49 PM PDT 24 | 10607580000 ps | ||
| T13 | /workspace/coverage/default/48.prim_present_test.2278255504 | Aug 14 04:33:38 PM PDT 24 | Aug 14 04:34:56 PM PDT 24 | 12454560000 ps | ||
| T14 | /workspace/coverage/default/31.prim_present_test.2945526861 | Aug 14 04:33:48 PM PDT 24 | Aug 14 04:35:28 PM PDT 24 | 11602680000 ps | ||
| T15 | /workspace/coverage/default/9.prim_present_test.2967145713 | Aug 14 04:33:50 PM PDT 24 | Aug 14 04:34:38 PM PDT 24 | 8804000000 ps | ||
| T16 | /workspace/coverage/default/10.prim_present_test.3766260009 | Aug 14 04:33:44 PM PDT 24 | Aug 14 04:35:18 PM PDT 24 | 14486300000 ps | ||
| T17 | /workspace/coverage/default/24.prim_present_test.3458560949 | Aug 14 04:33:44 PM PDT 24 | Aug 14 04:34:47 PM PDT 24 | 9323560000 ps | ||
| T18 | /workspace/coverage/default/5.prim_present_test.3588195272 | Aug 14 04:33:52 PM PDT 24 | Aug 14 04:35:10 PM PDT 24 | 13463920000 ps | ||
| T19 | /workspace/coverage/default/41.prim_present_test.387211283 | Aug 14 04:33:57 PM PDT 24 | Aug 14 04:35:07 PM PDT 24 | 9428960000 ps | ||
| T20 | /workspace/coverage/default/39.prim_present_test.1292315356 | Aug 14 04:33:49 PM PDT 24 | Aug 14 04:34:26 PM PDT 24 | 4856460000 ps | ||
| T21 | /workspace/coverage/default/22.prim_present_test.3806256340 | Aug 14 04:33:43 PM PDT 24 | Aug 14 04:34:29 PM PDT 24 | 7830600000 ps | ||
| T22 | /workspace/coverage/default/6.prim_present_test.1994775925 | Aug 14 04:33:44 PM PDT 24 | Aug 14 04:34:16 PM PDT 24 | 5398340000 ps | ||
| T23 | /workspace/coverage/default/2.prim_present_test.3309419451 | Aug 14 04:33:53 PM PDT 24 | Aug 14 04:34:57 PM PDT 24 | 12650480000 ps | ||
| T24 | /workspace/coverage/default/8.prim_present_test.3347081920 | Aug 14 04:33:45 PM PDT 24 | Aug 14 04:34:13 PM PDT 24 | 4085800000 ps | ||
| T25 | /workspace/coverage/default/14.prim_present_test.26403767 | Aug 14 04:33:48 PM PDT 24 | Aug 14 04:34:38 PM PDT 24 | 8379300000 ps | ||
| T26 | /workspace/coverage/default/29.prim_present_test.3177900614 | Aug 14 04:33:33 PM PDT 24 | Aug 14 04:34:31 PM PDT 24 | 8720920000 ps | ||
| T27 | /workspace/coverage/default/7.prim_present_test.670394615 | Aug 14 04:34:00 PM PDT 24 | Aug 14 04:34:36 PM PDT 24 | 6687940000 ps | ||
| T28 | /workspace/coverage/default/37.prim_present_test.800407081 | Aug 14 04:33:59 PM PDT 24 | Aug 14 04:34:32 PM PDT 24 | 6152260000 ps | ||
| T29 | /workspace/coverage/default/40.prim_present_test.644074722 | Aug 14 04:34:02 PM PDT 24 | Aug 14 04:34:50 PM PDT 24 | 7372420000 ps | ||
| T30 | /workspace/coverage/default/28.prim_present_test.2369583 | Aug 14 04:33:44 PM PDT 24 | Aug 14 04:34:30 PM PDT 24 | 6459780000 ps | ||
| T31 | /workspace/coverage/default/25.prim_present_test.46556330 | Aug 14 04:33:39 PM PDT 24 | Aug 14 04:35:20 PM PDT 24 | 13638140000 ps | ||
| T32 | /workspace/coverage/default/3.prim_present_test.846201452 | Aug 14 04:33:44 PM PDT 24 | Aug 14 04:35:33 PM PDT 24 | 14243260000 ps | ||
| T33 | /workspace/coverage/default/34.prim_present_test.389498899 | Aug 14 04:34:09 PM PDT 24 | Aug 14 04:35:23 PM PDT 24 | 12106740000 ps | ||
| T34 | /workspace/coverage/default/38.prim_present_test.1001347618 | Aug 14 04:34:05 PM PDT 24 | Aug 14 04:35:10 PM PDT 24 | 10327960000 ps | ||
| T35 | /workspace/coverage/default/33.prim_present_test.2373421371 | Aug 14 04:33:50 PM PDT 24 | Aug 14 04:35:09 PM PDT 24 | 10321760000 ps | ||
| T36 | /workspace/coverage/default/49.prim_present_test.1387041019 | Aug 14 04:33:50 PM PDT 24 | Aug 14 04:35:08 PM PDT 24 | 11927560000 ps | ||
| T37 | /workspace/coverage/default/30.prim_present_test.2976888921 | Aug 14 04:33:28 PM PDT 24 | Aug 14 04:34:19 PM PDT 24 | 8192060000 ps | ||
| T38 | /workspace/coverage/default/43.prim_present_test.1843566671 | Aug 14 04:33:34 PM PDT 24 | Aug 14 04:34:42 PM PDT 24 | 11248040000 ps | ||
| T39 | /workspace/coverage/default/15.prim_present_test.2122010430 | Aug 14 04:33:52 PM PDT 24 | Aug 14 04:34:32 PM PDT 24 | 6327720000 ps | ||
| T40 | /workspace/coverage/default/13.prim_present_test.4521913 | Aug 14 04:33:32 PM PDT 24 | Aug 14 04:34:01 PM PDT 24 | 4461520000 ps | ||
| T41 | /workspace/coverage/default/42.prim_present_test.3771921373 | Aug 14 04:33:44 PM PDT 24 | Aug 14 04:34:51 PM PDT 24 | 10117160000 ps | ||
| T42 | /workspace/coverage/default/27.prim_present_test.3745544105 | Aug 14 04:33:55 PM PDT 24 | Aug 14 04:35:10 PM PDT 24 | 12610800000 ps | ||
| T43 | /workspace/coverage/default/26.prim_present_test.3409027599 | Aug 14 04:33:28 PM PDT 24 | Aug 14 04:33:48 PM PDT 24 | 3321960000 ps | ||
| T44 | /workspace/coverage/default/32.prim_present_test.3695509769 | Aug 14 04:33:44 PM PDT 24 | Aug 14 04:35:13 PM PDT 24 | 13342400000 ps | ||
| T45 | /workspace/coverage/default/18.prim_present_test.2271371318 | Aug 14 04:33:47 PM PDT 24 | Aug 14 04:35:12 PM PDT 24 | 13894200000 ps | ||
| T46 | /workspace/coverage/default/20.prim_present_test.2445266629 | Aug 14 04:34:00 PM PDT 24 | Aug 14 04:34:24 PM PDT 24 | 4289160000 ps | ||
| T47 | /workspace/coverage/default/23.prim_present_test.2779852787 | Aug 14 04:33:33 PM PDT 24 | Aug 14 04:34:01 PM PDT 24 | 3454640000 ps | ||
| T48 | /workspace/coverage/default/17.prim_present_test.3618142001 | Aug 14 04:33:54 PM PDT 24 | Aug 14 04:34:23 PM PDT 24 | 5810640000 ps | ||
| T49 | /workspace/coverage/default/36.prim_present_test.2665832230 | Aug 14 04:33:35 PM PDT 24 | Aug 14 04:34:51 PM PDT 24 | 13474460000 ps | ||
| T50 | /workspace/coverage/default/45.prim_present_test.1518952590 | Aug 14 04:33:53 PM PDT 24 | Aug 14 04:34:31 PM PDT 24 | 5659360000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.586786669 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10618120000 ps |
| CPU time | 42.75 seconds |
| Started | Aug 14 04:33:40 PM PDT 24 |
| Finished | Aug 14 04:35:03 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-bbccaf74-5d21-477c-b092-f2f6acd90dea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586786669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.586786669 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4172798630 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13217160000 ps |
| CPU time | 42.31 seconds |
| Started | Aug 14 04:33:43 PM PDT 24 |
| Finished | Aug 14 04:35:02 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-ea9cea2d-271e-4e00-98d4-6937257d5342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172798630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4172798630 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3766260009 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 14486300000 ps |
| CPU time | 49.21 seconds |
| Started | Aug 14 04:33:44 PM PDT 24 |
| Finished | Aug 14 04:35:18 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-dd6287c5-0d8d-46ca-9cc7-66d89fdbd2f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766260009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3766260009 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1239170438 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7093420000 ps |
| CPU time | 23.49 seconds |
| Started | Aug 14 04:33:56 PM PDT 24 |
| Finished | Aug 14 04:34:40 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-4b1572b2-b1cd-49a4-acfa-70691b9de780 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239170438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1239170438 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1465503377 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3662340000 ps |
| CPU time | 14.57 seconds |
| Started | Aug 14 04:33:43 PM PDT 24 |
| Finished | Aug 14 04:34:10 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-22728816-1b21-4cea-a187-9b32535ef761 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465503377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1465503377 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.4521913 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4461520000 ps |
| CPU time | 15.49 seconds |
| Started | Aug 14 04:33:32 PM PDT 24 |
| Finished | Aug 14 04:34:01 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-94546097-1852-4835-811c-b7f52e738a43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4521913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.4521913 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.26403767 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8379300000 ps |
| CPU time | 26.45 seconds |
| Started | Aug 14 04:33:48 PM PDT 24 |
| Finished | Aug 14 04:34:38 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-a9a1ceff-6e24-4405-9be3-ce72cf41f76d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26403767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.26403767 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2122010430 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6327720000 ps |
| CPU time | 21.14 seconds |
| Started | Aug 14 04:33:52 PM PDT 24 |
| Finished | Aug 14 04:34:32 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-46976792-280d-4dd8-b026-85b914f90ab1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122010430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2122010430 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2134307201 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11758920000 ps |
| CPU time | 46.97 seconds |
| Started | Aug 14 04:33:45 PM PDT 24 |
| Finished | Aug 14 04:35:16 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-6d7e97ef-5747-42af-a0fc-8ef7583f775f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134307201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2134307201 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3618142001 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5810640000 ps |
| CPU time | 15.71 seconds |
| Started | Aug 14 04:33:54 PM PDT 24 |
| Finished | Aug 14 04:34:23 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-0a58d4bb-8d7f-4737-aed0-9a43b33d1007 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618142001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3618142001 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2271371318 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13894200000 ps |
| CPU time | 45.79 seconds |
| Started | Aug 14 04:33:47 PM PDT 24 |
| Finished | Aug 14 04:35:12 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-0ef72829-ab2b-4e7f-86a5-716c557d9c90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2271371318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2271371318 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3085656001 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13217780000 ps |
| CPU time | 44.28 seconds |
| Started | Aug 14 04:33:36 PM PDT 24 |
| Finished | Aug 14 04:35:00 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-e37f3249-57e4-4e29-8b08-93c5d6804496 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085656001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3085656001 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3309419451 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12650480000 ps |
| CPU time | 35.25 seconds |
| Started | Aug 14 04:33:53 PM PDT 24 |
| Finished | Aug 14 04:34:57 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-dbe910f2-21bb-4ef2-afde-d07f0fe699b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309419451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3309419451 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2445266629 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4289160000 ps |
| CPU time | 13.11 seconds |
| Started | Aug 14 04:34:00 PM PDT 24 |
| Finished | Aug 14 04:34:24 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-5b8d3c85-5ebd-4afd-8924-420c6d8bface |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445266629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2445266629 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.560314529 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12360940000 ps |
| CPU time | 40.75 seconds |
| Started | Aug 14 04:33:42 PM PDT 24 |
| Finished | Aug 14 04:34:58 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-aa6c8ba1-c5dd-4564-a0a9-5383bb2c73c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560314529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.560314529 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3806256340 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7830600000 ps |
| CPU time | 24.63 seconds |
| Started | Aug 14 04:33:43 PM PDT 24 |
| Finished | Aug 14 04:34:29 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-885f4b69-2e47-4bb5-a397-1b7896b382bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806256340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3806256340 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2779852787 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3454640000 ps |
| CPU time | 14.52 seconds |
| Started | Aug 14 04:33:33 PM PDT 24 |
| Finished | Aug 14 04:34:01 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-f78986aa-425e-49a3-9d35-3f9d2da90685 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779852787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2779852787 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3458560949 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9323560000 ps |
| CPU time | 32.86 seconds |
| Started | Aug 14 04:33:44 PM PDT 24 |
| Finished | Aug 14 04:34:47 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-cfbae08e-3779-4f7c-aff6-20158e9de8a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458560949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3458560949 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.46556330 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13638140000 ps |
| CPU time | 52.23 seconds |
| Started | Aug 14 04:33:39 PM PDT 24 |
| Finished | Aug 14 04:35:20 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-2707ac1b-e30c-4135-a364-1b156f900a44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46556330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.46556330 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3409027599 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3321960000 ps |
| CPU time | 11.02 seconds |
| Started | Aug 14 04:33:28 PM PDT 24 |
| Finished | Aug 14 04:33:48 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-75b1ecfa-097d-4cc6-bbc4-9123c0c56df4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409027599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3409027599 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3745544105 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12610800000 ps |
| CPU time | 40.47 seconds |
| Started | Aug 14 04:33:55 PM PDT 24 |
| Finished | Aug 14 04:35:10 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-b548cd71-b633-4f3e-8cd8-f58de5019dff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745544105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3745544105 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2369583 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6459780000 ps |
| CPU time | 24.17 seconds |
| Started | Aug 14 04:33:44 PM PDT 24 |
| Finished | Aug 14 04:34:30 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-079f3b51-c919-460a-ad3a-46934a1471ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2369583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2369583 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3177900614 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8720920000 ps |
| CPU time | 30.2 seconds |
| Started | Aug 14 04:33:33 PM PDT 24 |
| Finished | Aug 14 04:34:31 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-fd575ec2-aa9e-41ef-a2cf-208d3bb0d375 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177900614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3177900614 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.846201452 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14243260000 ps |
| CPU time | 57.23 seconds |
| Started | Aug 14 04:33:44 PM PDT 24 |
| Finished | Aug 14 04:35:33 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-e6405d7d-7d37-4a84-9f15-2f4448b6df36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=846201452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.846201452 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2976888921 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8192060000 ps |
| CPU time | 27.25 seconds |
| Started | Aug 14 04:33:28 PM PDT 24 |
| Finished | Aug 14 04:34:19 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-7a77b4eb-fbb7-43d6-909c-9967dfa96f29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976888921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2976888921 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2945526861 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11602680000 ps |
| CPU time | 51.31 seconds |
| Started | Aug 14 04:33:48 PM PDT 24 |
| Finished | Aug 14 04:35:28 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-27923896-5ca9-4be5-a672-798d7a9bb7f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945526861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2945526861 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3695509769 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13342400000 ps |
| CPU time | 47.85 seconds |
| Started | Aug 14 04:33:44 PM PDT 24 |
| Finished | Aug 14 04:35:13 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-687c7a89-3287-44f3-9ca2-e47c8686c238 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3695509769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3695509769 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2373421371 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10321760000 ps |
| CPU time | 41.41 seconds |
| Started | Aug 14 04:33:50 PM PDT 24 |
| Finished | Aug 14 04:35:09 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-cb4f477e-d7a0-4688-9d07-0d3cf71ff6c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373421371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2373421371 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.389498899 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12106740000 ps |
| CPU time | 39.52 seconds |
| Started | Aug 14 04:34:09 PM PDT 24 |
| Finished | Aug 14 04:35:23 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-c463d221-6322-4cd9-b6df-2d881bf3bcca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389498899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.389498899 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.504822872 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5531640000 ps |
| CPU time | 18.48 seconds |
| Started | Aug 14 04:33:46 PM PDT 24 |
| Finished | Aug 14 04:34:20 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-36839e27-1952-42af-a59d-e00e23c6f4d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504822872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.504822872 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2665832230 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13474460000 ps |
| CPU time | 41.54 seconds |
| Started | Aug 14 04:33:35 PM PDT 24 |
| Finished | Aug 14 04:34:51 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-d6057c74-3f88-49d4-b342-29e985751663 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665832230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2665832230 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.800407081 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6152260000 ps |
| CPU time | 17.63 seconds |
| Started | Aug 14 04:33:59 PM PDT 24 |
| Finished | Aug 14 04:34:32 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-922165e2-4b64-4cba-a0f1-3ad3245864ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800407081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.800407081 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1001347618 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10327960000 ps |
| CPU time | 34.72 seconds |
| Started | Aug 14 04:34:05 PM PDT 24 |
| Finished | Aug 14 04:35:10 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-7f89588c-f8dd-4389-8b31-3c3def1b736c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001347618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1001347618 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1292315356 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4856460000 ps |
| CPU time | 19.18 seconds |
| Started | Aug 14 04:33:49 PM PDT 24 |
| Finished | Aug 14 04:34:26 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-6cd34db9-13e0-4ff3-8019-dfd7dedb6807 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292315356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1292315356 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3963744269 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10607580000 ps |
| CPU time | 34.1 seconds |
| Started | Aug 14 04:33:45 PM PDT 24 |
| Finished | Aug 14 04:34:49 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-1aa7cf1d-a90a-4477-bae0-e35bda896f91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963744269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3963744269 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.644074722 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7372420000 ps |
| CPU time | 25.06 seconds |
| Started | Aug 14 04:34:02 PM PDT 24 |
| Finished | Aug 14 04:34:50 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-2798d0b3-30e3-4975-8565-3994a513af0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=644074722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.644074722 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.387211283 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9428960000 ps |
| CPU time | 36.42 seconds |
| Started | Aug 14 04:33:57 PM PDT 24 |
| Finished | Aug 14 04:35:07 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-82e96ff3-952e-40f1-b2ec-f21ef1811329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387211283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.387211283 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3771921373 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10117160000 ps |
| CPU time | 35.16 seconds |
| Started | Aug 14 04:33:44 PM PDT 24 |
| Finished | Aug 14 04:34:51 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-30a40aba-4319-4b39-b573-652a84057add |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771921373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3771921373 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1843566671 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11248040000 ps |
| CPU time | 36.49 seconds |
| Started | Aug 14 04:33:34 PM PDT 24 |
| Finished | Aug 14 04:34:42 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-6b4ae67c-6201-4193-b94a-798a18e908f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1843566671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1843566671 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1931147717 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11903380000 ps |
| CPU time | 38.16 seconds |
| Started | Aug 14 04:33:50 PM PDT 24 |
| Finished | Aug 14 04:35:01 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-29bec3e8-d145-46c9-8020-fc00270ad6c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931147717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1931147717 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1518952590 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5659360000 ps |
| CPU time | 19.83 seconds |
| Started | Aug 14 04:33:53 PM PDT 24 |
| Finished | Aug 14 04:34:31 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-e41b1758-ac31-4fc3-b953-c771bc99b048 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518952590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1518952590 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.676531035 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8110220000 ps |
| CPU time | 26.47 seconds |
| Started | Aug 14 04:34:11 PM PDT 24 |
| Finished | Aug 14 04:35:01 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-fea9ec7c-f989-4d42-98b3-d295e499b28a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676531035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.676531035 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.933881979 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13682160000 ps |
| CPU time | 48.24 seconds |
| Started | Aug 14 04:33:34 PM PDT 24 |
| Finished | Aug 14 04:35:09 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-18f8cd02-c272-46f0-9349-f8e362ca0a0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933881979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.933881979 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2278255504 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12454560000 ps |
| CPU time | 41.36 seconds |
| Started | Aug 14 04:33:38 PM PDT 24 |
| Finished | Aug 14 04:34:56 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-c11f6623-354f-4115-b203-9f287eceff4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2278255504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2278255504 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1387041019 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11927560000 ps |
| CPU time | 41.78 seconds |
| Started | Aug 14 04:33:50 PM PDT 24 |
| Finished | Aug 14 04:35:08 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-5af062f9-fd8f-445f-aaf9-f1650e5155d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387041019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1387041019 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3588195272 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13463920000 ps |
| CPU time | 42.03 seconds |
| Started | Aug 14 04:33:52 PM PDT 24 |
| Finished | Aug 14 04:35:10 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-00c45997-b7bc-480f-94f4-d84dc4733f90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588195272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3588195272 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1994775925 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5398340000 ps |
| CPU time | 17.26 seconds |
| Started | Aug 14 04:33:44 PM PDT 24 |
| Finished | Aug 14 04:34:16 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-3cdcfefd-1236-45d9-9cfc-89bc4e64b28a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994775925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1994775925 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.670394615 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6687940000 ps |
| CPU time | 19.85 seconds |
| Started | Aug 14 04:34:00 PM PDT 24 |
| Finished | Aug 14 04:34:36 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-dae41272-9a48-4157-93a6-d902984d61fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670394615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.670394615 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3347081920 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4085800000 ps |
| CPU time | 14.91 seconds |
| Started | Aug 14 04:33:45 PM PDT 24 |
| Finished | Aug 14 04:34:13 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-6c6a5653-772b-4c89-9d34-767fe27ab76d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347081920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3347081920 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2967145713 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8804000000 ps |
| CPU time | 25.89 seconds |
| Started | Aug 14 04:33:50 PM PDT 24 |
| Finished | Aug 14 04:34:38 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-030bd74a-3b2f-45b8-a537-631b788b8836 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967145713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2967145713 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |