| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.4014778474 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3401538160 |
| /workspace/coverage/default/1.prim_present_test.945156498 |
| /workspace/coverage/default/11.prim_present_test.109343831 |
| /workspace/coverage/default/12.prim_present_test.1090699563 |
| /workspace/coverage/default/13.prim_present_test.2624836405 |
| /workspace/coverage/default/14.prim_present_test.3411157924 |
| /workspace/coverage/default/15.prim_present_test.756020266 |
| /workspace/coverage/default/16.prim_present_test.789696221 |
| /workspace/coverage/default/17.prim_present_test.1853821431 |
| /workspace/coverage/default/18.prim_present_test.2079054240 |
| /workspace/coverage/default/19.prim_present_test.3471317023 |
| /workspace/coverage/default/2.prim_present_test.4055729349 |
| /workspace/coverage/default/20.prim_present_test.422998076 |
| /workspace/coverage/default/21.prim_present_test.4181235892 |
| /workspace/coverage/default/22.prim_present_test.2950702411 |
| /workspace/coverage/default/23.prim_present_test.1350871824 |
| /workspace/coverage/default/24.prim_present_test.3076963580 |
| /workspace/coverage/default/25.prim_present_test.1644474814 |
| /workspace/coverage/default/26.prim_present_test.2731725489 |
| /workspace/coverage/default/27.prim_present_test.1339541030 |
| /workspace/coverage/default/28.prim_present_test.996522420 |
| /workspace/coverage/default/29.prim_present_test.3075910377 |
| /workspace/coverage/default/3.prim_present_test.1982024156 |
| /workspace/coverage/default/30.prim_present_test.1733174798 |
| /workspace/coverage/default/31.prim_present_test.3017300927 |
| /workspace/coverage/default/32.prim_present_test.2960114643 |
| /workspace/coverage/default/33.prim_present_test.2679218041 |
| /workspace/coverage/default/34.prim_present_test.1107932752 |
| /workspace/coverage/default/35.prim_present_test.2419283932 |
| /workspace/coverage/default/36.prim_present_test.844521576 |
| /workspace/coverage/default/37.prim_present_test.1431769639 |
| /workspace/coverage/default/38.prim_present_test.1287028149 |
| /workspace/coverage/default/39.prim_present_test.1075690967 |
| /workspace/coverage/default/4.prim_present_test.1973277324 |
| /workspace/coverage/default/40.prim_present_test.2269780691 |
| /workspace/coverage/default/41.prim_present_test.617457218 |
| /workspace/coverage/default/42.prim_present_test.2827111426 |
| /workspace/coverage/default/43.prim_present_test.6530716 |
| /workspace/coverage/default/44.prim_present_test.1270372199 |
| /workspace/coverage/default/45.prim_present_test.3150257694 |
| /workspace/coverage/default/46.prim_present_test.2548219982 |
| /workspace/coverage/default/47.prim_present_test.3088812549 |
| /workspace/coverage/default/48.prim_present_test.574355829 |
| /workspace/coverage/default/49.prim_present_test.3059134248 |
| /workspace/coverage/default/5.prim_present_test.409512980 |
| /workspace/coverage/default/6.prim_present_test.3252931520 |
| /workspace/coverage/default/7.prim_present_test.2691113169 |
| /workspace/coverage/default/8.prim_present_test.165323768 |
| /workspace/coverage/default/9.prim_present_test.1766049856 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_present_test.409512980 | Aug 15 05:17:38 PM PDT 24 | Aug 15 05:19:21 PM PDT 24 | 14738640000 ps | ||
| T2 | /workspace/coverage/default/48.prim_present_test.574355829 | Aug 15 05:17:52 PM PDT 24 | Aug 15 05:18:50 PM PDT 24 | 7549120000 ps | ||
| T3 | /workspace/coverage/default/19.prim_present_test.3471317023 | Aug 15 05:17:40 PM PDT 24 | Aug 15 05:18:53 PM PDT 24 | 9742060000 ps | ||
| T4 | /workspace/coverage/default/10.prim_present_test.4014778474 | Aug 15 05:17:39 PM PDT 24 | Aug 15 05:18:45 PM PDT 24 | 10135140000 ps | ||
| T5 | /workspace/coverage/default/27.prim_present_test.1339541030 | Aug 15 05:17:41 PM PDT 24 | Aug 15 05:19:21 PM PDT 24 | 14292860000 ps | ||
| T6 | /workspace/coverage/default/11.prim_present_test.109343831 | Aug 15 05:17:41 PM PDT 24 | Aug 15 05:19:12 PM PDT 24 | 13088820000 ps | ||
| T7 | /workspace/coverage/default/25.prim_present_test.1644474814 | Aug 15 05:17:41 PM PDT 24 | Aug 15 05:18:10 PM PDT 24 | 4175700000 ps | ||
| T8 | /workspace/coverage/default/42.prim_present_test.2827111426 | Aug 15 05:17:49 PM PDT 24 | Aug 15 05:18:56 PM PDT 24 | 9720980000 ps | ||
| T9 | /workspace/coverage/default/46.prim_present_test.2548219982 | Aug 15 05:17:50 PM PDT 24 | Aug 15 05:18:28 PM PDT 24 | 5729420000 ps | ||
| T10 | /workspace/coverage/default/20.prim_present_test.422998076 | Aug 15 05:17:42 PM PDT 24 | Aug 15 05:19:07 PM PDT 24 | 10418480000 ps | ||
| T11 | /workspace/coverage/default/15.prim_present_test.756020266 | Aug 15 05:17:41 PM PDT 24 | Aug 15 05:18:31 PM PDT 24 | 7697920000 ps | ||
| T12 | /workspace/coverage/default/1.prim_present_test.945156498 | Aug 15 05:17:42 PM PDT 24 | Aug 15 05:18:34 PM PDT 24 | 6982440000 ps | ||
| T13 | /workspace/coverage/default/12.prim_present_test.1090699563 | Aug 15 05:17:39 PM PDT 24 | Aug 15 05:19:05 PM PDT 24 | 13457720000 ps | ||
| T14 | /workspace/coverage/default/45.prim_present_test.3150257694 | Aug 15 05:17:48 PM PDT 24 | Aug 15 05:18:46 PM PDT 24 | 8518180000 ps | ||
| T15 | /workspace/coverage/default/6.prim_present_test.3252931520 | Aug 15 05:17:39 PM PDT 24 | Aug 15 05:18:55 PM PDT 24 | 11958560000 ps | ||
| T16 | /workspace/coverage/default/41.prim_present_test.617457218 | Aug 15 05:17:50 PM PDT 24 | Aug 15 05:19:09 PM PDT 24 | 10092360000 ps | ||
| T17 | /workspace/coverage/default/24.prim_present_test.3076963580 | Aug 15 05:17:40 PM PDT 24 | Aug 15 05:18:54 PM PDT 24 | 10631140000 ps | ||
| T18 | /workspace/coverage/default/23.prim_present_test.1350871824 | Aug 15 05:17:41 PM PDT 24 | Aug 15 05:18:48 PM PDT 24 | 9197080000 ps | ||
| T19 | /workspace/coverage/default/14.prim_present_test.3411157924 | Aug 15 05:17:44 PM PDT 24 | Aug 15 05:18:59 PM PDT 24 | 13055960000 ps | ||
| T20 | /workspace/coverage/default/39.prim_present_test.1075690967 | Aug 15 05:17:48 PM PDT 24 | Aug 15 05:18:38 PM PDT 24 | 6655700000 ps | ||
| T21 | /workspace/coverage/default/31.prim_present_test.3017300927 | Aug 15 05:17:39 PM PDT 24 | Aug 15 05:18:47 PM PDT 24 | 10119640000 ps | ||
| T22 | /workspace/coverage/default/38.prim_present_test.1287028149 | Aug 15 05:17:51 PM PDT 24 | Aug 15 05:18:49 PM PDT 24 | 8960240000 ps | ||
| T23 | /workspace/coverage/default/22.prim_present_test.2950702411 | Aug 15 05:17:43 PM PDT 24 | Aug 15 05:18:59 PM PDT 24 | 13335580000 ps | ||
| T24 | /workspace/coverage/default/37.prim_present_test.1431769639 | Aug 15 05:17:49 PM PDT 24 | Aug 15 05:19:22 PM PDT 24 | 14676640000 ps | ||
| T25 | /workspace/coverage/default/18.prim_present_test.2079054240 | Aug 15 05:17:43 PM PDT 24 | Aug 15 05:18:52 PM PDT 24 | 11504720000 ps | ||
| T26 | /workspace/coverage/default/32.prim_present_test.2960114643 | Aug 15 05:17:41 PM PDT 24 | Aug 15 05:19:13 PM PDT 24 | 12755260000 ps | ||
| T27 | /workspace/coverage/default/2.prim_present_test.4055729349 | Aug 15 05:17:38 PM PDT 24 | Aug 15 05:18:05 PM PDT 24 | 3646220000 ps | ||
| T28 | /workspace/coverage/default/0.prim_present_test.3401538160 | Aug 15 05:17:38 PM PDT 24 | Aug 15 05:18:37 PM PDT 24 | 9239860000 ps | ||
| T29 | /workspace/coverage/default/47.prim_present_test.3088812549 | Aug 15 05:17:49 PM PDT 24 | Aug 15 05:19:33 PM PDT 24 | 15180700000 ps | ||
| T30 | /workspace/coverage/default/40.prim_present_test.2269780691 | Aug 15 05:17:50 PM PDT 24 | Aug 15 05:18:24 PM PDT 24 | 4999060000 ps | ||
| T31 | /workspace/coverage/default/49.prim_present_test.3059134248 | Aug 15 05:17:50 PM PDT 24 | Aug 15 05:18:57 PM PDT 24 | 9399200000 ps | ||
| T32 | /workspace/coverage/default/35.prim_present_test.2419283932 | Aug 15 05:17:48 PM PDT 24 | Aug 15 05:19:00 PM PDT 24 | 9903880000 ps | ||
| T33 | /workspace/coverage/default/26.prim_present_test.2731725489 | Aug 15 05:17:40 PM PDT 24 | Aug 15 05:18:57 PM PDT 24 | 12169980000 ps | ||
| T34 | /workspace/coverage/default/33.prim_present_test.2679218041 | Aug 15 05:17:39 PM PDT 24 | Aug 15 05:18:25 PM PDT 24 | 6339500000 ps | ||
| T35 | /workspace/coverage/default/28.prim_present_test.996522420 | Aug 15 05:17:41 PM PDT 24 | Aug 15 05:18:29 PM PDT 24 | 6497600000 ps | ||
| T36 | /workspace/coverage/default/8.prim_present_test.165323768 | Aug 15 05:17:38 PM PDT 24 | Aug 15 05:18:30 PM PDT 24 | 8014740000 ps | ||
| T37 | /workspace/coverage/default/36.prim_present_test.844521576 | Aug 15 05:17:49 PM PDT 24 | Aug 15 05:18:19 PM PDT 24 | 4346200000 ps | ||
| T38 | /workspace/coverage/default/13.prim_present_test.2624836405 | Aug 15 05:17:40 PM PDT 24 | Aug 15 05:18:30 PM PDT 24 | 6532320000 ps | ||
| T39 | /workspace/coverage/default/4.prim_present_test.1973277324 | Aug 15 05:17:40 PM PDT 24 | Aug 15 05:18:12 PM PDT 24 | 5166460000 ps | ||
| T40 | /workspace/coverage/default/9.prim_present_test.1766049856 | Aug 15 05:17:37 PM PDT 24 | Aug 15 05:19:06 PM PDT 24 | 12856940000 ps | ||
| T41 | /workspace/coverage/default/43.prim_present_test.6530716 | Aug 15 05:17:52 PM PDT 24 | Aug 15 05:18:46 PM PDT 24 | 7055600000 ps | ||
| T42 | /workspace/coverage/default/3.prim_present_test.1982024156 | Aug 15 05:17:42 PM PDT 24 | Aug 15 05:18:05 PM PDT 24 | 3658620000 ps | ||
| T43 | /workspace/coverage/default/17.prim_present_test.1853821431 | Aug 15 05:17:38 PM PDT 24 | Aug 15 05:19:10 PM PDT 24 | 12883600000 ps | ||
| T44 | /workspace/coverage/default/21.prim_present_test.4181235892 | Aug 15 05:17:43 PM PDT 24 | Aug 15 05:19:19 PM PDT 24 | 12329940000 ps | ||
| T45 | /workspace/coverage/default/30.prim_present_test.1733174798 | Aug 15 05:17:38 PM PDT 24 | Aug 15 05:19:29 PM PDT 24 | 13638140000 ps | ||
| T46 | /workspace/coverage/default/29.prim_present_test.3075910377 | Aug 15 05:17:43 PM PDT 24 | Aug 15 05:19:06 PM PDT 24 | 14849620000 ps | ||
| T47 | /workspace/coverage/default/16.prim_present_test.789696221 | Aug 15 05:17:44 PM PDT 24 | Aug 15 05:19:29 PM PDT 24 | 13343640000 ps | ||
| T48 | /workspace/coverage/default/7.prim_present_test.2691113169 | Aug 15 05:17:40 PM PDT 24 | Aug 15 05:18:47 PM PDT 24 | 10334780000 ps | ||
| T49 | /workspace/coverage/default/44.prim_present_test.1270372199 | Aug 15 05:17:50 PM PDT 24 | Aug 15 05:18:58 PM PDT 24 | 10083060000 ps | ||
| T50 | /workspace/coverage/default/34.prim_present_test.1107932752 | Aug 15 05:17:48 PM PDT 24 | Aug 15 05:18:59 PM PDT 24 | 11096140000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.4014778474 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10135140000 ps |
| CPU time | 34.63 seconds |
| Started | Aug 15 05:17:39 PM PDT 24 |
| Finished | Aug 15 05:18:45 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-831bdf4a-667d-44f8-b010-c5209a049762 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014778474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.4014778474 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3401538160 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9239860000 ps |
| CPU time | 31.26 seconds |
| Started | Aug 15 05:17:38 PM PDT 24 |
| Finished | Aug 15 05:18:37 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-ca50e3d5-7eec-4728-8f49-f8d40be2c4d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3401538160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3401538160 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.945156498 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6982440000 ps |
| CPU time | 27.9 seconds |
| Started | Aug 15 05:17:42 PM PDT 24 |
| Finished | Aug 15 05:18:34 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-f39cefe0-ba51-40ff-aee1-a8e580c3b9fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945156498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.945156498 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.109343831 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13088820000 ps |
| CPU time | 48.73 seconds |
| Started | Aug 15 05:17:41 PM PDT 24 |
| Finished | Aug 15 05:19:12 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-174f883d-6252-4fcc-9b54-47184df36009 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109343831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.109343831 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1090699563 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13457720000 ps |
| CPU time | 44.58 seconds |
| Started | Aug 15 05:17:39 PM PDT 24 |
| Finished | Aug 15 05:19:05 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-07573392-3c40-478a-8c24-fb0f582a87e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090699563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1090699563 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2624836405 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6532320000 ps |
| CPU time | 25.78 seconds |
| Started | Aug 15 05:17:40 PM PDT 24 |
| Finished | Aug 15 05:18:30 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-05466258-1ebd-4d92-bda8-e72eb278cb14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624836405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2624836405 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3411157924 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13055960000 ps |
| CPU time | 40.11 seconds |
| Started | Aug 15 05:17:44 PM PDT 24 |
| Finished | Aug 15 05:18:59 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-b98f48b8-d8ef-4cf9-b18f-77bfd6a3497f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411157924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3411157924 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.756020266 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7697920000 ps |
| CPU time | 26.92 seconds |
| Started | Aug 15 05:17:41 PM PDT 24 |
| Finished | Aug 15 05:18:31 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-13474c69-f054-4f29-8b37-8cbcd9e8a782 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756020266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.756020266 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.789696221 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13343640000 ps |
| CPU time | 53.91 seconds |
| Started | Aug 15 05:17:44 PM PDT 24 |
| Finished | Aug 15 05:19:29 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-7eef1f01-c098-4676-88cb-76037bc226c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789696221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.789696221 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1853821431 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12883600000 ps |
| CPU time | 48.15 seconds |
| Started | Aug 15 05:17:38 PM PDT 24 |
| Finished | Aug 15 05:19:10 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-51ed12b7-e27e-4004-b298-f2ad4d39ff40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853821431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1853821431 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2079054240 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11504720000 ps |
| CPU time | 36.8 seconds |
| Started | Aug 15 05:17:43 PM PDT 24 |
| Finished | Aug 15 05:18:52 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-f30866fa-0dae-4771-a5c0-2e39db4663f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079054240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2079054240 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3471317023 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9742060000 ps |
| CPU time | 38 seconds |
| Started | Aug 15 05:17:40 PM PDT 24 |
| Finished | Aug 15 05:18:53 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-8fbe169c-8dfb-4b8b-b938-3d89de7de553 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3471317023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3471317023 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4055729349 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3646220000 ps |
| CPU time | 14.4 seconds |
| Started | Aug 15 05:17:38 PM PDT 24 |
| Finished | Aug 15 05:18:05 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-ea7abcbf-d721-47fe-b90a-733f033641d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055729349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4055729349 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.422998076 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10418480000 ps |
| CPU time | 43.18 seconds |
| Started | Aug 15 05:17:42 PM PDT 24 |
| Finished | Aug 15 05:19:07 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-15578305-a19e-42c3-b25b-e3155b6ae5ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422998076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.422998076 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4181235892 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12329940000 ps |
| CPU time | 48.9 seconds |
| Started | Aug 15 05:17:43 PM PDT 24 |
| Finished | Aug 15 05:19:19 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-9a0171c3-fbbe-4826-a7d6-6281c2e2ac57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181235892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4181235892 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2950702411 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13335580000 ps |
| CPU time | 40.91 seconds |
| Started | Aug 15 05:17:43 PM PDT 24 |
| Finished | Aug 15 05:18:59 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-86b9917e-fbbf-47b5-884f-8052ab1c082d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950702411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2950702411 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1350871824 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9197080000 ps |
| CPU time | 35.13 seconds |
| Started | Aug 15 05:17:41 PM PDT 24 |
| Finished | Aug 15 05:18:48 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-e3d1f8c0-a7e7-419f-9f8d-45df86786f61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350871824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1350871824 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3076963580 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10631140000 ps |
| CPU time | 39.07 seconds |
| Started | Aug 15 05:17:40 PM PDT 24 |
| Finished | Aug 15 05:18:54 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-1c223efc-8352-4d9f-be49-955e9a918e22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3076963580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3076963580 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1644474814 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4175700000 ps |
| CPU time | 15.71 seconds |
| Started | Aug 15 05:17:41 PM PDT 24 |
| Finished | Aug 15 05:18:10 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-fa2ae62e-9cfd-4142-ab11-fee77b6551a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1644474814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1644474814 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2731725489 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12169980000 ps |
| CPU time | 41.59 seconds |
| Started | Aug 15 05:17:40 PM PDT 24 |
| Finished | Aug 15 05:18:57 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-a38a8465-68c3-49ec-8b37-b8dd293974af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731725489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2731725489 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1339541030 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14292860000 ps |
| CPU time | 53.08 seconds |
| Started | Aug 15 05:17:41 PM PDT 24 |
| Finished | Aug 15 05:19:21 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-98c7fc63-2cc5-46af-8478-ed0909b50264 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1339541030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1339541030 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.996522420 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6497600000 ps |
| CPU time | 26.29 seconds |
| Started | Aug 15 05:17:41 PM PDT 24 |
| Finished | Aug 15 05:18:29 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-41286409-bb68-4aea-bfe9-65c4e2a3aa60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996522420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.996522420 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3075910377 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14849620000 ps |
| CPU time | 45.5 seconds |
| Started | Aug 15 05:17:43 PM PDT 24 |
| Finished | Aug 15 05:19:06 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-b1a0f7f1-7e4d-46f0-8325-bcf004b4a4de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3075910377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3075910377 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1982024156 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3658620000 ps |
| CPU time | 12.25 seconds |
| Started | Aug 15 05:17:42 PM PDT 24 |
| Finished | Aug 15 05:18:05 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-a1959d87-846b-4822-9ed8-296a6515efd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982024156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1982024156 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1733174798 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13638140000 ps |
| CPU time | 57.38 seconds |
| Started | Aug 15 05:17:38 PM PDT 24 |
| Finished | Aug 15 05:19:29 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-19f57177-94bf-4cf1-ba67-a8788fc644c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733174798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1733174798 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3017300927 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10119640000 ps |
| CPU time | 36.11 seconds |
| Started | Aug 15 05:17:39 PM PDT 24 |
| Finished | Aug 15 05:18:47 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-dbed5ae4-a6e1-42f0-8537-21f92bb3bee6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017300927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3017300927 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2960114643 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12755260000 ps |
| CPU time | 48.46 seconds |
| Started | Aug 15 05:17:41 PM PDT 24 |
| Finished | Aug 15 05:19:13 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-a57de09f-f782-45bf-871f-ba74d147c007 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960114643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2960114643 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2679218041 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6339500000 ps |
| CPU time | 24.05 seconds |
| Started | Aug 15 05:17:39 PM PDT 24 |
| Finished | Aug 15 05:18:25 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-f7a60844-d3fe-47d2-a069-163f49c11dfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679218041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2679218041 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1107932752 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11096140000 ps |
| CPU time | 37.17 seconds |
| Started | Aug 15 05:17:48 PM PDT 24 |
| Finished | Aug 15 05:18:59 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-e692c191-5c3e-4d45-b028-5f7c8d449258 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107932752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1107932752 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2419283932 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9903880000 ps |
| CPU time | 37.9 seconds |
| Started | Aug 15 05:17:48 PM PDT 24 |
| Finished | Aug 15 05:19:00 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-28ef3eef-7f57-4634-bb79-55b213593d4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419283932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2419283932 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.844521576 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4346200000 ps |
| CPU time | 15.83 seconds |
| Started | Aug 15 05:17:49 PM PDT 24 |
| Finished | Aug 15 05:18:19 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-97121a75-0669-410e-9473-46895fe19304 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844521576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.844521576 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1431769639 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 14676640000 ps |
| CPU time | 49.81 seconds |
| Started | Aug 15 05:17:49 PM PDT 24 |
| Finished | Aug 15 05:19:22 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-ddcd0d8b-7360-47e2-a94a-92aa7727d565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431769639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1431769639 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1287028149 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8960240000 ps |
| CPU time | 30.94 seconds |
| Started | Aug 15 05:17:51 PM PDT 24 |
| Finished | Aug 15 05:18:49 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-c9215116-7a21-4a5c-8a7c-88489efba481 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287028149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1287028149 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1075690967 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6655700000 ps |
| CPU time | 26.24 seconds |
| Started | Aug 15 05:17:48 PM PDT 24 |
| Finished | Aug 15 05:18:38 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-3c8805b4-4987-43a8-9b69-66f63c1efeaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075690967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1075690967 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1973277324 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5166460000 ps |
| CPU time | 17.32 seconds |
| Started | Aug 15 05:17:40 PM PDT 24 |
| Finished | Aug 15 05:18:12 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-e4fa3d95-7896-44b1-bb4d-39348d8a4e6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1973277324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1973277324 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2269780691 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4999060000 ps |
| CPU time | 18.36 seconds |
| Started | Aug 15 05:17:50 PM PDT 24 |
| Finished | Aug 15 05:18:24 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-7ba97f5c-710c-4411-a6e2-40aca9285d13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2269780691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2269780691 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.617457218 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10092360000 ps |
| CPU time | 41.3 seconds |
| Started | Aug 15 05:17:50 PM PDT 24 |
| Finished | Aug 15 05:19:09 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-70cafb32-e3a5-4fdf-b0cf-c928419ebb68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617457218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.617457218 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2827111426 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9720980000 ps |
| CPU time | 35.24 seconds |
| Started | Aug 15 05:17:49 PM PDT 24 |
| Finished | Aug 15 05:18:56 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-b9a664a5-614b-4d92-9412-611e2a7f3f95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827111426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2827111426 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.6530716 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 7055600000 ps |
| CPU time | 27.54 seconds |
| Started | Aug 15 05:17:52 PM PDT 24 |
| Finished | Aug 15 05:18:46 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-594e99d3-a424-4a28-8586-00c10b63bc00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6530716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.6530716 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1270372199 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10083060000 ps |
| CPU time | 36.15 seconds |
| Started | Aug 15 05:17:50 PM PDT 24 |
| Finished | Aug 15 05:18:58 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-c51eca23-8963-4836-b36f-6a425d1a305b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1270372199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1270372199 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3150257694 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8518180000 ps |
| CPU time | 30.84 seconds |
| Started | Aug 15 05:17:48 PM PDT 24 |
| Finished | Aug 15 05:18:46 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-235e1b4a-1097-4b17-9637-51dd2502541c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150257694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3150257694 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2548219982 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5729420000 ps |
| CPU time | 20.11 seconds |
| Started | Aug 15 05:17:50 PM PDT 24 |
| Finished | Aug 15 05:18:28 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-7421b842-f054-4387-9886-94101a47664d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2548219982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2548219982 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3088812549 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 15180700000 ps |
| CPU time | 55.18 seconds |
| Started | Aug 15 05:17:49 PM PDT 24 |
| Finished | Aug 15 05:19:33 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-92848dd7-fce8-4b51-83a7-cdc81f3459ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088812549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3088812549 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.574355829 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7549120000 ps |
| CPU time | 29.73 seconds |
| Started | Aug 15 05:17:52 PM PDT 24 |
| Finished | Aug 15 05:18:50 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-ab66b2ef-95bb-49ab-a01f-5a37a80bad80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574355829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.574355829 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3059134248 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9399200000 ps |
| CPU time | 35.8 seconds |
| Started | Aug 15 05:17:50 PM PDT 24 |
| Finished | Aug 15 05:18:57 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-fa0556a2-62c3-4df7-8b14-98b369eab712 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059134248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3059134248 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.409512980 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14738640000 ps |
| CPU time | 54.48 seconds |
| Started | Aug 15 05:17:38 PM PDT 24 |
| Finished | Aug 15 05:19:21 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-51b89d11-538c-4ba1-ae96-1da582371fff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409512980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.409512980 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3252931520 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11958560000 ps |
| CPU time | 40.19 seconds |
| Started | Aug 15 05:17:39 PM PDT 24 |
| Finished | Aug 15 05:18:55 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-727fe8ae-1467-4c0e-865a-f71f90df43bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252931520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3252931520 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2691113169 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10334780000 ps |
| CPU time | 35.52 seconds |
| Started | Aug 15 05:17:40 PM PDT 24 |
| Finished | Aug 15 05:18:47 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-a7912280-7bb4-44f4-8b41-23eb3eccb75e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2691113169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2691113169 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.165323768 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8014740000 ps |
| CPU time | 27.87 seconds |
| Started | Aug 15 05:17:38 PM PDT 24 |
| Finished | Aug 15 05:18:30 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-d2abe511-539d-421a-964d-6ec591531442 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165323768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.165323768 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1766049856 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12856940000 ps |
| CPU time | 47.16 seconds |
| Started | Aug 15 05:17:37 PM PDT 24 |
| Finished | Aug 15 05:19:06 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-6478abf2-cb3f-4963-a827-c84509b2b74b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1766049856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1766049856 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |