| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2239967381 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.2859546307 |
| /workspace/coverage/default/10.prim_present_test.3468588915 |
| /workspace/coverage/default/11.prim_present_test.3051284922 |
| /workspace/coverage/default/12.prim_present_test.2985096184 |
| /workspace/coverage/default/13.prim_present_test.3645662617 |
| /workspace/coverage/default/14.prim_present_test.1412258201 |
| /workspace/coverage/default/15.prim_present_test.384962423 |
| /workspace/coverage/default/16.prim_present_test.2914495571 |
| /workspace/coverage/default/17.prim_present_test.2299915387 |
| /workspace/coverage/default/18.prim_present_test.2568493383 |
| /workspace/coverage/default/19.prim_present_test.3123902638 |
| /workspace/coverage/default/2.prim_present_test.427499160 |
| /workspace/coverage/default/20.prim_present_test.2852953864 |
| /workspace/coverage/default/21.prim_present_test.2395720334 |
| /workspace/coverage/default/22.prim_present_test.4117667661 |
| /workspace/coverage/default/23.prim_present_test.1653846403 |
| /workspace/coverage/default/24.prim_present_test.3998646410 |
| /workspace/coverage/default/25.prim_present_test.1474436749 |
| /workspace/coverage/default/26.prim_present_test.3561757115 |
| /workspace/coverage/default/27.prim_present_test.2328040984 |
| /workspace/coverage/default/28.prim_present_test.3072305251 |
| /workspace/coverage/default/29.prim_present_test.2428715758 |
| /workspace/coverage/default/3.prim_present_test.703364105 |
| /workspace/coverage/default/30.prim_present_test.1637689622 |
| /workspace/coverage/default/31.prim_present_test.1544201675 |
| /workspace/coverage/default/32.prim_present_test.2457001578 |
| /workspace/coverage/default/33.prim_present_test.3612266612 |
| /workspace/coverage/default/34.prim_present_test.396317750 |
| /workspace/coverage/default/35.prim_present_test.3421187124 |
| /workspace/coverage/default/36.prim_present_test.854419696 |
| /workspace/coverage/default/37.prim_present_test.3343585691 |
| /workspace/coverage/default/38.prim_present_test.2415397635 |
| /workspace/coverage/default/39.prim_present_test.2054564664 |
| /workspace/coverage/default/4.prim_present_test.3798496288 |
| /workspace/coverage/default/40.prim_present_test.681304290 |
| /workspace/coverage/default/41.prim_present_test.197968500 |
| /workspace/coverage/default/42.prim_present_test.1320204235 |
| /workspace/coverage/default/43.prim_present_test.464046357 |
| /workspace/coverage/default/44.prim_present_test.3178693464 |
| /workspace/coverage/default/45.prim_present_test.3887055562 |
| /workspace/coverage/default/46.prim_present_test.2323875597 |
| /workspace/coverage/default/47.prim_present_test.1064207655 |
| /workspace/coverage/default/48.prim_present_test.2569910910 |
| /workspace/coverage/default/49.prim_present_test.228375948 |
| /workspace/coverage/default/5.prim_present_test.2162175616 |
| /workspace/coverage/default/6.prim_present_test.608483680 |
| /workspace/coverage/default/7.prim_present_test.804681416 |
| /workspace/coverage/default/8.prim_present_test.4067404788 |
| /workspace/coverage/default/9.prim_present_test.185081921 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_present_test.2985096184 | Aug 16 04:19:28 PM PDT 24 | Aug 16 04:21:24 PM PDT 24 | 15218520000 ps | ||
| T2 | /workspace/coverage/default/41.prim_present_test.197968500 | Aug 16 04:24:49 PM PDT 24 | Aug 16 04:25:36 PM PDT 24 | 6960120000 ps | ||
| T3 | /workspace/coverage/default/5.prim_present_test.2162175616 | Aug 16 04:23:39 PM PDT 24 | Aug 16 04:24:29 PM PDT 24 | 7598100000 ps | ||
| T4 | /workspace/coverage/default/0.prim_present_test.2239967381 | Aug 16 04:24:24 PM PDT 24 | Aug 16 04:25:52 PM PDT 24 | 12978460000 ps | ||
| T5 | /workspace/coverage/default/13.prim_present_test.3645662617 | Aug 16 04:20:06 PM PDT 24 | Aug 16 04:21:03 PM PDT 24 | 8790980000 ps | ||
| T6 | /workspace/coverage/default/17.prim_present_test.2299915387 | Aug 16 04:19:29 PM PDT 24 | Aug 16 04:20:40 PM PDT 24 | 9849320000 ps | ||
| T7 | /workspace/coverage/default/40.prim_present_test.681304290 | Aug 16 04:24:49 PM PDT 24 | Aug 16 04:26:02 PM PDT 24 | 11437760000 ps | ||
| T8 | /workspace/coverage/default/44.prim_present_test.3178693464 | Aug 16 04:24:50 PM PDT 24 | Aug 16 04:26:28 PM PDT 24 | 14743600000 ps | ||
| T9 | /workspace/coverage/default/47.prim_present_test.1064207655 | Aug 16 04:24:48 PM PDT 24 | Aug 16 04:25:53 PM PDT 24 | 9432060000 ps | ||
| T10 | /workspace/coverage/default/38.prim_present_test.2415397635 | Aug 16 04:24:49 PM PDT 24 | Aug 16 04:25:30 PM PDT 24 | 6274400000 ps | ||
| T11 | /workspace/coverage/default/31.prim_present_test.1544201675 | Aug 16 04:24:47 PM PDT 24 | Aug 16 04:25:26 PM PDT 24 | 6107620000 ps | ||
| T12 | /workspace/coverage/default/18.prim_present_test.2568493383 | Aug 16 04:19:28 PM PDT 24 | Aug 16 04:20:45 PM PDT 24 | 9951620000 ps | ||
| T13 | /workspace/coverage/default/1.prim_present_test.2859546307 | Aug 16 04:22:08 PM PDT 24 | Aug 16 04:22:38 PM PDT 24 | 4317060000 ps | ||
| T14 | /workspace/coverage/default/37.prim_present_test.3343585691 | Aug 16 04:24:48 PM PDT 24 | Aug 16 04:25:47 PM PDT 24 | 9177240000 ps | ||
| T15 | /workspace/coverage/default/22.prim_present_test.4117667661 | Aug 16 04:24:48 PM PDT 24 | Aug 16 04:26:24 PM PDT 24 | 13344260000 ps | ||
| T16 | /workspace/coverage/default/46.prim_present_test.2323875597 | Aug 16 04:24:51 PM PDT 24 | Aug 16 04:25:16 PM PDT 24 | 3679080000 ps | ||
| T17 | /workspace/coverage/default/30.prim_present_test.1637689622 | Aug 16 04:24:52 PM PDT 24 | Aug 16 04:26:33 PM PDT 24 | 14416860000 ps | ||
| T18 | /workspace/coverage/default/35.prim_present_test.3421187124 | Aug 16 04:25:00 PM PDT 24 | Aug 16 04:25:56 PM PDT 24 | 7960180000 ps | ||
| T19 | /workspace/coverage/default/42.prim_present_test.1320204235 | Aug 16 04:24:59 PM PDT 24 | Aug 16 04:26:24 PM PDT 24 | 11881680000 ps | ||
| T20 | /workspace/coverage/default/14.prim_present_test.1412258201 | Aug 16 04:19:29 PM PDT 24 | Aug 16 04:20:38 PM PDT 24 | 9510180000 ps | ||
| T21 | /workspace/coverage/default/3.prim_present_test.703364105 | Aug 16 04:23:22 PM PDT 24 | Aug 16 04:24:37 PM PDT 24 | 10766920000 ps | ||
| T22 | /workspace/coverage/default/24.prim_present_test.3998646410 | Aug 16 04:24:53 PM PDT 24 | Aug 16 04:26:01 PM PDT 24 | 10757000000 ps | ||
| T23 | /workspace/coverage/default/25.prim_present_test.1474436749 | Aug 16 04:24:49 PM PDT 24 | Aug 16 04:26:13 PM PDT 24 | 10875420000 ps | ||
| T24 | /workspace/coverage/default/29.prim_present_test.2428715758 | Aug 16 04:24:51 PM PDT 24 | Aug 16 04:26:21 PM PDT 24 | 12959860000 ps | ||
| T25 | /workspace/coverage/default/8.prim_present_test.4067404788 | Aug 16 04:20:28 PM PDT 24 | Aug 16 04:21:54 PM PDT 24 | 11869280000 ps | ||
| T26 | /workspace/coverage/default/33.prim_present_test.3612266612 | Aug 16 04:25:00 PM PDT 24 | Aug 16 04:26:10 PM PDT 24 | 9871640000 ps | ||
| T27 | /workspace/coverage/default/28.prim_present_test.3072305251 | Aug 16 04:24:53 PM PDT 24 | Aug 16 04:25:31 PM PDT 24 | 4706420000 ps | ||
| T28 | /workspace/coverage/default/49.prim_present_test.228375948 | Aug 16 04:24:50 PM PDT 24 | Aug 16 04:25:21 PM PDT 24 | 4677280000 ps | ||
| T29 | /workspace/coverage/default/10.prim_present_test.3468588915 | Aug 16 04:24:00 PM PDT 24 | Aug 16 04:24:55 PM PDT 24 | 8983180000 ps | ||
| T30 | /workspace/coverage/default/7.prim_present_test.804681416 | Aug 16 04:23:02 PM PDT 24 | Aug 16 04:24:05 PM PDT 24 | 8645900000 ps | ||
| T31 | /workspace/coverage/default/2.prim_present_test.427499160 | Aug 16 04:23:21 PM PDT 24 | Aug 16 04:24:23 PM PDT 24 | 8872820000 ps | ||
| T32 | /workspace/coverage/default/27.prim_present_test.2328040984 | Aug 16 04:24:54 PM PDT 24 | Aug 16 04:25:30 PM PDT 24 | 5426240000 ps | ||
| T33 | /workspace/coverage/default/6.prim_present_test.608483680 | Aug 16 04:19:13 PM PDT 24 | Aug 16 04:19:52 PM PDT 24 | 6340740000 ps | ||
| T34 | /workspace/coverage/default/36.prim_present_test.854419696 | Aug 16 04:24:53 PM PDT 24 | Aug 16 04:26:35 PM PDT 24 | 14857680000 ps | ||
| T35 | /workspace/coverage/default/4.prim_present_test.3798496288 | Aug 16 04:23:21 PM PDT 24 | Aug 16 04:24:39 PM PDT 24 | 11191620000 ps | ||
| T36 | /workspace/coverage/default/19.prim_present_test.3123902638 | Aug 16 04:19:29 PM PDT 24 | Aug 16 04:20:07 PM PDT 24 | 5260080000 ps | ||
| T37 | /workspace/coverage/default/16.prim_present_test.2914495571 | Aug 16 04:19:28 PM PDT 24 | Aug 16 04:19:58 PM PDT 24 | 3910960000 ps | ||
| T38 | /workspace/coverage/default/32.prim_present_test.2457001578 | Aug 16 04:24:55 PM PDT 24 | Aug 16 04:26:06 PM PDT 24 | 13526540000 ps | ||
| T39 | /workspace/coverage/default/45.prim_present_test.3887055562 | Aug 16 04:25:00 PM PDT 24 | Aug 16 04:25:54 PM PDT 24 | 7656380000 ps | ||
| T40 | /workspace/coverage/default/34.prim_present_test.396317750 | Aug 16 04:24:47 PM PDT 24 | Aug 16 04:26:25 PM PDT 24 | 13990300000 ps | ||
| T41 | /workspace/coverage/default/26.prim_present_test.3561757115 | Aug 16 04:24:57 PM PDT 24 | Aug 16 04:25:46 PM PDT 24 | 8766180000 ps | ||
| T42 | /workspace/coverage/default/43.prim_present_test.464046357 | Aug 16 04:24:52 PM PDT 24 | Aug 16 04:25:38 PM PDT 24 | 8307380000 ps | ||
| T43 | /workspace/coverage/default/9.prim_present_test.185081921 | Aug 16 04:23:17 PM PDT 24 | Aug 16 04:24:32 PM PDT 24 | 12344820000 ps | ||
| T44 | /workspace/coverage/default/11.prim_present_test.3051284922 | Aug 16 04:19:28 PM PDT 24 | Aug 16 04:20:54 PM PDT 24 | 11877340000 ps | ||
| T45 | /workspace/coverage/default/48.prim_present_test.2569910910 | Aug 16 04:24:51 PM PDT 24 | Aug 16 04:26:06 PM PDT 24 | 10386240000 ps | ||
| T46 | /workspace/coverage/default/23.prim_present_test.1653846403 | Aug 16 04:24:59 PM PDT 24 | Aug 16 04:26:36 PM PDT 24 | 13976040000 ps | ||
| T47 | /workspace/coverage/default/20.prim_present_test.2852953864 | Aug 16 04:24:49 PM PDT 24 | Aug 16 04:25:26 PM PDT 24 | 5511800000 ps | ||
| T48 | /workspace/coverage/default/21.prim_present_test.2395720334 | Aug 16 04:24:49 PM PDT 24 | Aug 16 04:26:05 PM PDT 24 | 12656060000 ps | ||
| T49 | /workspace/coverage/default/15.prim_present_test.384962423 | Aug 16 04:19:29 PM PDT 24 | Aug 16 04:19:52 PM PDT 24 | 3120460000 ps | ||
| T50 | /workspace/coverage/default/39.prim_present_test.2054564664 | Aug 16 04:24:50 PM PDT 24 | Aug 16 04:26:19 PM PDT 24 | 14118640000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2239967381 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12978460000 ps |
| CPU time | 46.26 seconds |
| Started | Aug 16 04:24:24 PM PDT 24 |
| Finished | Aug 16 04:25:52 PM PDT 24 |
| Peak memory | 144532 kb |
| Host | smart-46c3a0ba-f9a4-49e2-9561-2bfd21b8c05b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239967381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2239967381 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2859546307 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4317060000 ps |
| CPU time | 16.14 seconds |
| Started | Aug 16 04:22:08 PM PDT 24 |
| Finished | Aug 16 04:22:38 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-2da5a0ba-43de-4a02-894d-958d291dc003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859546307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2859546307 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3468588915 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8983180000 ps |
| CPU time | 29.2 seconds |
| Started | Aug 16 04:24:00 PM PDT 24 |
| Finished | Aug 16 04:24:55 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-577f078a-aa72-4a29-b9df-9d8d5a977ddc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468588915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3468588915 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3051284922 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11877340000 ps |
| CPU time | 44.92 seconds |
| Started | Aug 16 04:19:28 PM PDT 24 |
| Finished | Aug 16 04:20:54 PM PDT 24 |
| Peak memory | 143264 kb |
| Host | smart-9f706ac5-cd40-43d9-9fff-cb3d7698cfb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051284922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3051284922 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2985096184 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 15218520000 ps |
| CPU time | 60.76 seconds |
| Started | Aug 16 04:19:28 PM PDT 24 |
| Finished | Aug 16 04:21:24 PM PDT 24 |
| Peak memory | 142892 kb |
| Host | smart-5781b306-5a6c-418b-b476-75fb9855438d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985096184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2985096184 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3645662617 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8790980000 ps |
| CPU time | 30.9 seconds |
| Started | Aug 16 04:20:06 PM PDT 24 |
| Finished | Aug 16 04:21:03 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-0d7998a8-b379-4b08-8af8-f5c5200f0f6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3645662617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3645662617 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1412258201 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9510180000 ps |
| CPU time | 36.15 seconds |
| Started | Aug 16 04:19:29 PM PDT 24 |
| Finished | Aug 16 04:20:38 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-428210a8-bdf4-4214-adef-5e001ef52651 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412258201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1412258201 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.384962423 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3120460000 ps |
| CPU time | 12.18 seconds |
| Started | Aug 16 04:19:29 PM PDT 24 |
| Finished | Aug 16 04:19:52 PM PDT 24 |
| Peak memory | 143120 kb |
| Host | smart-eb727970-5722-41c8-ac81-c4018966f361 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384962423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.384962423 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2914495571 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3910960000 ps |
| CPU time | 15.49 seconds |
| Started | Aug 16 04:19:28 PM PDT 24 |
| Finished | Aug 16 04:19:58 PM PDT 24 |
| Peak memory | 143324 kb |
| Host | smart-2dac7db4-0a34-4f47-b92a-a579a3f71960 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914495571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2914495571 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2299915387 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9849320000 ps |
| CPU time | 37.11 seconds |
| Started | Aug 16 04:19:29 PM PDT 24 |
| Finished | Aug 16 04:20:40 PM PDT 24 |
| Peak memory | 144724 kb |
| Host | smart-145d074f-a1e6-4701-a9b7-d7892baf73b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299915387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2299915387 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2568493383 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9951620000 ps |
| CPU time | 40.16 seconds |
| Started | Aug 16 04:19:28 PM PDT 24 |
| Finished | Aug 16 04:20:45 PM PDT 24 |
| Peak memory | 142864 kb |
| Host | smart-acedba4e-6d9d-4fb4-b568-290d88a85e7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568493383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2568493383 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3123902638 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5260080000 ps |
| CPU time | 20.04 seconds |
| Started | Aug 16 04:19:29 PM PDT 24 |
| Finished | Aug 16 04:20:07 PM PDT 24 |
| Peak memory | 144720 kb |
| Host | smart-a01842c5-88d2-46c8-90d8-95cb764a5ac9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123902638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3123902638 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.427499160 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8872820000 ps |
| CPU time | 32.7 seconds |
| Started | Aug 16 04:23:21 PM PDT 24 |
| Finished | Aug 16 04:24:23 PM PDT 24 |
| Peak memory | 144532 kb |
| Host | smart-33eb5523-7c3d-45d1-ab47-64e698f4307e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=427499160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.427499160 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2852953864 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5511800000 ps |
| CPU time | 19.82 seconds |
| Started | Aug 16 04:24:49 PM PDT 24 |
| Finished | Aug 16 04:25:26 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-9595b07d-980d-48f8-9808-555a5cafa868 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852953864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2852953864 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2395720334 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12656060000 ps |
| CPU time | 40.97 seconds |
| Started | Aug 16 04:24:49 PM PDT 24 |
| Finished | Aug 16 04:26:05 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-cb9df6cc-f3b0-4172-b91c-0279126588df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2395720334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2395720334 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.4117667661 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13344260000 ps |
| CPU time | 50.33 seconds |
| Started | Aug 16 04:24:48 PM PDT 24 |
| Finished | Aug 16 04:26:24 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-a8d4ed06-355b-4189-891e-8029c1d1d9d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4117667661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.4117667661 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1653846403 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13976040000 ps |
| CPU time | 51.19 seconds |
| Started | Aug 16 04:24:59 PM PDT 24 |
| Finished | Aug 16 04:26:36 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-6789cbe0-7f47-4d1a-8a9d-9fe3032df1c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653846403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1653846403 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3998646410 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10757000000 ps |
| CPU time | 36.32 seconds |
| Started | Aug 16 04:24:53 PM PDT 24 |
| Finished | Aug 16 04:26:01 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-af5104e5-59ab-4b4d-8181-c58e49f127a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998646410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3998646410 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1474436749 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10875420000 ps |
| CPU time | 42.19 seconds |
| Started | Aug 16 04:24:49 PM PDT 24 |
| Finished | Aug 16 04:26:13 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-005ac4f6-9871-4979-81b2-e3ad54c960d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1474436749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1474436749 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3561757115 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8766180000 ps |
| CPU time | 26.34 seconds |
| Started | Aug 16 04:24:57 PM PDT 24 |
| Finished | Aug 16 04:25:46 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-e7b8bdde-c634-49b7-9f6e-73a0e4121b73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561757115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3561757115 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2328040984 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5426240000 ps |
| CPU time | 19.63 seconds |
| Started | Aug 16 04:24:54 PM PDT 24 |
| Finished | Aug 16 04:25:30 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-bc50ac83-74fd-4589-8417-5ea2b17cf42b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328040984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2328040984 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3072305251 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4706420000 ps |
| CPU time | 20.07 seconds |
| Started | Aug 16 04:24:53 PM PDT 24 |
| Finished | Aug 16 04:25:31 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-c8ec9b0f-b94c-482a-9eef-e25c9fd02163 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072305251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3072305251 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2428715758 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12959860000 ps |
| CPU time | 46.86 seconds |
| Started | Aug 16 04:24:51 PM PDT 24 |
| Finished | Aug 16 04:26:21 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-07bdb331-b026-4baf-b343-76c162b81021 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428715758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2428715758 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.703364105 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10766920000 ps |
| CPU time | 39.98 seconds |
| Started | Aug 16 04:23:22 PM PDT 24 |
| Finished | Aug 16 04:24:37 PM PDT 24 |
| Peak memory | 144648 kb |
| Host | smart-a0a68922-8249-4fb4-ad51-ef640a5a6550 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703364105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.703364105 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1637689622 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 14416860000 ps |
| CPU time | 53.48 seconds |
| Started | Aug 16 04:24:52 PM PDT 24 |
| Finished | Aug 16 04:26:33 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-2cef5632-4e31-4705-9444-0fac6038dd98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637689622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1637689622 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1544201675 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6107620000 ps |
| CPU time | 20.71 seconds |
| Started | Aug 16 04:24:47 PM PDT 24 |
| Finished | Aug 16 04:25:26 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-cc9fad49-d5a9-4a67-add0-c7f43f2dceb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544201675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1544201675 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2457001578 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13526540000 ps |
| CPU time | 39.57 seconds |
| Started | Aug 16 04:24:55 PM PDT 24 |
| Finished | Aug 16 04:26:06 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-f6c9c01a-e442-4f15-8f6c-111e7e213957 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2457001578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2457001578 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3612266612 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9871640000 ps |
| CPU time | 36.92 seconds |
| Started | Aug 16 04:25:00 PM PDT 24 |
| Finished | Aug 16 04:26:10 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-0e20022a-7376-4ad6-813e-71be8cb739f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3612266612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3612266612 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.396317750 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13990300000 ps |
| CPU time | 51.72 seconds |
| Started | Aug 16 04:24:47 PM PDT 24 |
| Finished | Aug 16 04:26:25 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-db9c57a8-21b4-4a2d-a1ed-c3556cec432f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396317750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.396317750 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3421187124 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7960180000 ps |
| CPU time | 29.88 seconds |
| Started | Aug 16 04:25:00 PM PDT 24 |
| Finished | Aug 16 04:25:56 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-590e79c8-8dec-46d8-a97e-1bec383c8857 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421187124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3421187124 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.854419696 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 14857680000 ps |
| CPU time | 54.32 seconds |
| Started | Aug 16 04:24:53 PM PDT 24 |
| Finished | Aug 16 04:26:35 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-9ad90b35-6e10-4957-962b-28265e7549f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854419696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.854419696 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3343585691 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9177240000 ps |
| CPU time | 31.59 seconds |
| Started | Aug 16 04:24:48 PM PDT 24 |
| Finished | Aug 16 04:25:47 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-43c704e1-83d9-428b-a5fc-9b5ee2c12b3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3343585691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3343585691 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2415397635 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6274400000 ps |
| CPU time | 22.1 seconds |
| Started | Aug 16 04:24:49 PM PDT 24 |
| Finished | Aug 16 04:25:30 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-d28bd270-9deb-4995-b522-7d58079629e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415397635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2415397635 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2054564664 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14118640000 ps |
| CPU time | 47.58 seconds |
| Started | Aug 16 04:24:50 PM PDT 24 |
| Finished | Aug 16 04:26:19 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-f34f0bb0-0cc0-48b4-bbef-f1925772b049 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054564664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2054564664 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3798496288 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11191620000 ps |
| CPU time | 40.86 seconds |
| Started | Aug 16 04:23:21 PM PDT 24 |
| Finished | Aug 16 04:24:39 PM PDT 24 |
| Peak memory | 144720 kb |
| Host | smart-6a8920a4-7453-46c3-aaa6-37ba2cb07088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3798496288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3798496288 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.681304290 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11437760000 ps |
| CPU time | 39.1 seconds |
| Started | Aug 16 04:24:49 PM PDT 24 |
| Finished | Aug 16 04:26:02 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-84ab7acd-3fc2-4bce-a894-cf0bebb54ec0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681304290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.681304290 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.197968500 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6960120000 ps |
| CPU time | 24.47 seconds |
| Started | Aug 16 04:24:49 PM PDT 24 |
| Finished | Aug 16 04:25:36 PM PDT 24 |
| Peak memory | 144236 kb |
| Host | smart-9c0e076b-97c6-4856-a01f-66d1129b7f9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=197968500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.197968500 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1320204235 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11881680000 ps |
| CPU time | 44.59 seconds |
| Started | Aug 16 04:24:59 PM PDT 24 |
| Finished | Aug 16 04:26:24 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-867f38a5-a81f-416f-a6c8-286a7c452a9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320204235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1320204235 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.464046357 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8307380000 ps |
| CPU time | 25.56 seconds |
| Started | Aug 16 04:24:52 PM PDT 24 |
| Finished | Aug 16 04:25:38 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-66ffa20b-8361-47ff-a75c-e79fdbfc4097 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464046357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.464046357 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3178693464 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 14743600000 ps |
| CPU time | 51.67 seconds |
| Started | Aug 16 04:24:50 PM PDT 24 |
| Finished | Aug 16 04:26:28 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-8afe8965-2c10-4689-a122-bd83ea3af77e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178693464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3178693464 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3887055562 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7656380000 ps |
| CPU time | 28.54 seconds |
| Started | Aug 16 04:25:00 PM PDT 24 |
| Finished | Aug 16 04:25:54 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-8e835f61-bd24-443b-8edc-d4d3b0c16065 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3887055562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3887055562 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2323875597 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3679080000 ps |
| CPU time | 13.41 seconds |
| Started | Aug 16 04:24:51 PM PDT 24 |
| Finished | Aug 16 04:25:16 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-4e024015-f047-4354-b310-f14624ea9994 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323875597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2323875597 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1064207655 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9432060000 ps |
| CPU time | 33.95 seconds |
| Started | Aug 16 04:24:48 PM PDT 24 |
| Finished | Aug 16 04:25:53 PM PDT 24 |
| Peak memory | 144248 kb |
| Host | smart-83863475-6073-4054-826e-9da53bd01ca8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064207655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1064207655 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2569910910 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10386240000 ps |
| CPU time | 39.85 seconds |
| Started | Aug 16 04:24:51 PM PDT 24 |
| Finished | Aug 16 04:26:06 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-64510f4c-3ebf-4f35-b307-57cc86a8d1a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569910910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2569910910 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.228375948 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4677280000 ps |
| CPU time | 16.49 seconds |
| Started | Aug 16 04:24:50 PM PDT 24 |
| Finished | Aug 16 04:25:21 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-d19edfb6-1ed5-4ecc-8824-d36c026a6d13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228375948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.228375948 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2162175616 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7598100000 ps |
| CPU time | 26.14 seconds |
| Started | Aug 16 04:23:39 PM PDT 24 |
| Finished | Aug 16 04:24:29 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-1ba3cd16-698e-4040-b318-1742ccaccfc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162175616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2162175616 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.608483680 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6340740000 ps |
| CPU time | 20.94 seconds |
| Started | Aug 16 04:19:13 PM PDT 24 |
| Finished | Aug 16 04:19:52 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-23167900-08b2-44b2-abf5-d64003d0df16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608483680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.608483680 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.804681416 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8645900000 ps |
| CPU time | 33.12 seconds |
| Started | Aug 16 04:23:02 PM PDT 24 |
| Finished | Aug 16 04:24:05 PM PDT 24 |
| Peak memory | 143428 kb |
| Host | smart-ebeb091f-0224-4578-8743-6a21f00e1868 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804681416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.804681416 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4067404788 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11869280000 ps |
| CPU time | 44.94 seconds |
| Started | Aug 16 04:20:28 PM PDT 24 |
| Finished | Aug 16 04:21:54 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-59faa919-4031-47fd-8765-f39c76bdcf3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067404788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4067404788 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.185081921 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12344820000 ps |
| CPU time | 40.59 seconds |
| Started | Aug 16 04:23:17 PM PDT 24 |
| Finished | Aug 16 04:24:32 PM PDT 24 |
| Peak memory | 143792 kb |
| Host | smart-e2668875-34ad-4d07-a758-76beedb4ec19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185081921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.185081921 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |