| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/13.prim_present_test.3481331330 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1415438555 |
| /workspace/coverage/default/1.prim_present_test.1004446367 |
| /workspace/coverage/default/10.prim_present_test.3192642614 |
| /workspace/coverage/default/11.prim_present_test.1175998202 |
| /workspace/coverage/default/12.prim_present_test.2100372382 |
| /workspace/coverage/default/14.prim_present_test.2175515417 |
| /workspace/coverage/default/15.prim_present_test.3743990700 |
| /workspace/coverage/default/16.prim_present_test.2029380428 |
| /workspace/coverage/default/17.prim_present_test.3209926914 |
| /workspace/coverage/default/18.prim_present_test.3984018099 |
| /workspace/coverage/default/19.prim_present_test.4031502024 |
| /workspace/coverage/default/2.prim_present_test.417631335 |
| /workspace/coverage/default/20.prim_present_test.935372144 |
| /workspace/coverage/default/21.prim_present_test.3406573182 |
| /workspace/coverage/default/22.prim_present_test.627577562 |
| /workspace/coverage/default/23.prim_present_test.457971282 |
| /workspace/coverage/default/24.prim_present_test.3392243323 |
| /workspace/coverage/default/25.prim_present_test.1250522828 |
| /workspace/coverage/default/26.prim_present_test.240609078 |
| /workspace/coverage/default/27.prim_present_test.2652636411 |
| /workspace/coverage/default/28.prim_present_test.3279000960 |
| /workspace/coverage/default/29.prim_present_test.1874695949 |
| /workspace/coverage/default/3.prim_present_test.4156552245 |
| /workspace/coverage/default/30.prim_present_test.2322338233 |
| /workspace/coverage/default/31.prim_present_test.487825204 |
| /workspace/coverage/default/32.prim_present_test.3199840632 |
| /workspace/coverage/default/33.prim_present_test.3816311522 |
| /workspace/coverage/default/34.prim_present_test.135723812 |
| /workspace/coverage/default/35.prim_present_test.3527459321 |
| /workspace/coverage/default/36.prim_present_test.688278439 |
| /workspace/coverage/default/37.prim_present_test.2977667638 |
| /workspace/coverage/default/38.prim_present_test.2294414746 |
| /workspace/coverage/default/39.prim_present_test.24221549 |
| /workspace/coverage/default/4.prim_present_test.1962556711 |
| /workspace/coverage/default/40.prim_present_test.2444350736 |
| /workspace/coverage/default/41.prim_present_test.663725756 |
| /workspace/coverage/default/42.prim_present_test.1452066506 |
| /workspace/coverage/default/43.prim_present_test.6527795 |
| /workspace/coverage/default/44.prim_present_test.3619575763 |
| /workspace/coverage/default/45.prim_present_test.3358391796 |
| /workspace/coverage/default/46.prim_present_test.2846111968 |
| /workspace/coverage/default/47.prim_present_test.1370188493 |
| /workspace/coverage/default/48.prim_present_test.3348784472 |
| /workspace/coverage/default/49.prim_present_test.514910664 |
| /workspace/coverage/default/5.prim_present_test.927639660 |
| /workspace/coverage/default/6.prim_present_test.1669142284 |
| /workspace/coverage/default/7.prim_present_test.1612204159 |
| /workspace/coverage/default/8.prim_present_test.2851899498 |
| /workspace/coverage/default/9.prim_present_test.992607143 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/44.prim_present_test.3619575763 | Aug 17 04:21:57 PM PDT 24 | Aug 17 04:22:56 PM PDT 24 | 8094720000 ps | ||
| T2 | /workspace/coverage/default/34.prim_present_test.135723812 | Aug 17 04:25:26 PM PDT 24 | Aug 17 04:26:44 PM PDT 24 | 13810500000 ps | ||
| T3 | /workspace/coverage/default/13.prim_present_test.3481331330 | Aug 17 04:23:25 PM PDT 24 | Aug 17 04:24:53 PM PDT 24 | 11466280000 ps | ||
| T4 | /workspace/coverage/default/5.prim_present_test.927639660 | Aug 17 04:24:48 PM PDT 24 | Aug 17 04:25:58 PM PDT 24 | 11692580000 ps | ||
| T5 | /workspace/coverage/default/38.prim_present_test.2294414746 | Aug 17 04:25:12 PM PDT 24 | Aug 17 04:26:05 PM PDT 24 | 8549180000 ps | ||
| T6 | /workspace/coverage/default/22.prim_present_test.627577562 | Aug 17 04:25:47 PM PDT 24 | Aug 17 04:26:33 PM PDT 24 | 8035200000 ps | ||
| T7 | /workspace/coverage/default/19.prim_present_test.4031502024 | Aug 17 04:25:10 PM PDT 24 | Aug 17 04:25:31 PM PDT 24 | 3541440000 ps | ||
| T8 | /workspace/coverage/default/9.prim_present_test.992607143 | Aug 17 04:21:12 PM PDT 24 | Aug 17 04:22:23 PM PDT 24 | 11001280000 ps | ||
| T9 | /workspace/coverage/default/30.prim_present_test.2322338233 | Aug 17 04:25:38 PM PDT 24 | Aug 17 04:27:29 PM PDT 24 | 14801880000 ps | ||
| T10 | /workspace/coverage/default/17.prim_present_test.3209926914 | Aug 17 04:21:10 PM PDT 24 | Aug 17 04:22:48 PM PDT 24 | 15072200000 ps | ||
| T11 | /workspace/coverage/default/7.prim_present_test.1612204159 | Aug 17 04:23:46 PM PDT 24 | Aug 17 04:24:55 PM PDT 24 | 9054480000 ps | ||
| T12 | /workspace/coverage/default/39.prim_present_test.24221549 | Aug 17 04:25:26 PM PDT 24 | Aug 17 04:26:46 PM PDT 24 | 12817880000 ps | ||
| T13 | /workspace/coverage/default/40.prim_present_test.2444350736 | Aug 17 04:25:46 PM PDT 24 | Aug 17 04:26:37 PM PDT 24 | 7838660000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.663725756 | Aug 17 04:25:46 PM PDT 24 | Aug 17 04:26:57 PM PDT 24 | 11372660000 ps | ||
| T15 | /workspace/coverage/default/37.prim_present_test.2977667638 | Aug 17 04:25:47 PM PDT 24 | Aug 17 04:27:04 PM PDT 24 | 12458900000 ps | ||
| T16 | /workspace/coverage/default/28.prim_present_test.3279000960 | Aug 17 04:21:13 PM PDT 24 | Aug 17 04:22:37 PM PDT 24 | 11788680000 ps | ||
| T17 | /workspace/coverage/default/11.prim_present_test.1175998202 | Aug 17 04:25:07 PM PDT 24 | Aug 17 04:26:31 PM PDT 24 | 14943240000 ps | ||
| T18 | /workspace/coverage/default/10.prim_present_test.3192642614 | Aug 17 04:25:04 PM PDT 24 | Aug 17 04:25:34 PM PDT 24 | 3892360000 ps | ||
| T19 | /workspace/coverage/default/29.prim_present_test.1874695949 | Aug 17 04:25:37 PM PDT 24 | Aug 17 04:26:10 PM PDT 24 | 5916660000 ps | ||
| T20 | /workspace/coverage/default/16.prim_present_test.2029380428 | Aug 17 04:25:12 PM PDT 24 | Aug 17 04:26:20 PM PDT 24 | 11106060000 ps | ||
| T21 | /workspace/coverage/default/42.prim_present_test.1452066506 | Aug 17 04:21:35 PM PDT 24 | Aug 17 04:22:42 PM PDT 24 | 9161740000 ps | ||
| T22 | /workspace/coverage/default/48.prim_present_test.3348784472 | Aug 17 04:21:47 PM PDT 24 | Aug 17 04:22:43 PM PDT 24 | 7543540000 ps | ||
| T23 | /workspace/coverage/default/32.prim_present_test.3199840632 | Aug 17 04:21:11 PM PDT 24 | Aug 17 04:22:35 PM PDT 24 | 11309420000 ps | ||
| T24 | /workspace/coverage/default/20.prim_present_test.935372144 | Aug 17 04:25:40 PM PDT 24 | Aug 17 04:26:08 PM PDT 24 | 4953800000 ps | ||
| T25 | /workspace/coverage/default/1.prim_present_test.1004446367 | Aug 17 04:25:08 PM PDT 24 | Aug 17 04:25:48 PM PDT 24 | 6792720000 ps | ||
| T26 | /workspace/coverage/default/43.prim_present_test.6527795 | Aug 17 04:24:53 PM PDT 24 | Aug 17 04:26:28 PM PDT 24 | 15244560000 ps | ||
| T27 | /workspace/coverage/default/3.prim_present_test.4156552245 | Aug 17 04:23:50 PM PDT 24 | Aug 17 04:24:18 PM PDT 24 | 4004580000 ps | ||
| T28 | /workspace/coverage/default/31.prim_present_test.487825204 | Aug 17 04:22:15 PM PDT 24 | Aug 17 04:23:07 PM PDT 24 | 8081080000 ps | ||
| T29 | /workspace/coverage/default/18.prim_present_test.3984018099 | Aug 17 04:25:32 PM PDT 24 | Aug 17 04:26:48 PM PDT 24 | 13789420000 ps | ||
| T30 | /workspace/coverage/default/36.prim_present_test.688278439 | Aug 17 04:25:48 PM PDT 24 | Aug 17 04:26:18 PM PDT 24 | 4667980000 ps | ||
| T31 | /workspace/coverage/default/26.prim_present_test.240609078 | Aug 17 04:25:39 PM PDT 24 | Aug 17 04:26:01 PM PDT 24 | 3387680000 ps | ||
| T32 | /workspace/coverage/default/14.prim_present_test.2175515417 | Aug 17 04:21:14 PM PDT 24 | Aug 17 04:21:43 PM PDT 24 | 4261260000 ps | ||
| T33 | /workspace/coverage/default/24.prim_present_test.3392243323 | Aug 17 04:26:00 PM PDT 24 | Aug 17 04:27:25 PM PDT 24 | 15317100000 ps | ||
| T34 | /workspace/coverage/default/33.prim_present_test.3816311522 | Aug 17 04:25:25 PM PDT 24 | Aug 17 04:26:18 PM PDT 24 | 8946600000 ps | ||
| T35 | /workspace/coverage/default/4.prim_present_test.1962556711 | Aug 17 04:23:05 PM PDT 24 | Aug 17 04:24:08 PM PDT 24 | 9303100000 ps | ||
| T36 | /workspace/coverage/default/0.prim_present_test.1415438555 | Aug 17 04:24:17 PM PDT 24 | Aug 17 04:24:59 PM PDT 24 | 6304780000 ps | ||
| T37 | /workspace/coverage/default/23.prim_present_test.457971282 | Aug 17 04:25:10 PM PDT 24 | Aug 17 04:26:09 PM PDT 24 | 9995640000 ps | ||
| T38 | /workspace/coverage/default/6.prim_present_test.1669142284 | Aug 17 04:23:33 PM PDT 24 | Aug 17 04:24:53 PM PDT 24 | 11496660000 ps | ||
| T39 | /workspace/coverage/default/35.prim_present_test.3527459321 | Aug 17 04:21:13 PM PDT 24 | Aug 17 04:22:37 PM PDT 24 | 12383880000 ps | ||
| T40 | /workspace/coverage/default/8.prim_present_test.2851899498 | Aug 17 04:22:56 PM PDT 24 | Aug 17 04:23:25 PM PDT 24 | 3978540000 ps | ||
| T41 | /workspace/coverage/default/46.prim_present_test.2846111968 | Aug 17 04:23:42 PM PDT 24 | Aug 17 04:24:28 PM PDT 24 | 5798860000 ps | ||
| T42 | /workspace/coverage/default/49.prim_present_test.514910664 | Aug 17 04:25:26 PM PDT 24 | Aug 17 04:26:37 PM PDT 24 | 11843240000 ps | ||
| T43 | /workspace/coverage/default/15.prim_present_test.3743990700 | Aug 17 04:25:05 PM PDT 24 | Aug 17 04:26:01 PM PDT 24 | 7635920000 ps | ||
| T44 | /workspace/coverage/default/2.prim_present_test.417631335 | Aug 17 04:22:30 PM PDT 24 | Aug 17 04:23:33 PM PDT 24 | 10078720000 ps | ||
| T45 | /workspace/coverage/default/45.prim_present_test.3358391796 | Aug 17 04:25:14 PM PDT 24 | Aug 17 04:25:34 PM PDT 24 | 3274840000 ps | ||
| T46 | /workspace/coverage/default/27.prim_present_test.2652636411 | Aug 17 04:24:25 PM PDT 24 | Aug 17 04:25:38 PM PDT 24 | 9939840000 ps | ||
| T47 | /workspace/coverage/default/47.prim_present_test.1370188493 | Aug 17 04:25:26 PM PDT 24 | Aug 17 04:25:57 PM PDT 24 | 4702080000 ps | ||
| T48 | /workspace/coverage/default/21.prim_present_test.3406573182 | Aug 17 04:25:00 PM PDT 24 | Aug 17 04:25:23 PM PDT 24 | 3914680000 ps | ||
| T49 | /workspace/coverage/default/12.prim_present_test.2100372382 | Aug 17 04:24:48 PM PDT 24 | Aug 17 04:25:20 PM PDT 24 | 5110040000 ps | ||
| T50 | /workspace/coverage/default/25.prim_present_test.1250522828 | Aug 17 04:24:04 PM PDT 24 | Aug 17 04:25:15 PM PDT 24 | 10822100000 ps |
| Test location | /workspace/coverage/default/13.prim_present_test.3481331330 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11466280000 ps |
| CPU time | 45.19 seconds |
| Started | Aug 17 04:23:25 PM PDT 24 |
| Finished | Aug 17 04:24:53 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-e197a29c-6457-4076-acfc-33910e9e1872 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481331330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3481331330 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1415438555 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6304780000 ps |
| CPU time | 22.61 seconds |
| Started | Aug 17 04:24:17 PM PDT 24 |
| Finished | Aug 17 04:24:59 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-42126bc2-6c60-4d6e-ae3f-045310e5f61d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415438555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1415438555 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1004446367 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6792720000 ps |
| CPU time | 21.75 seconds |
| Started | Aug 17 04:25:08 PM PDT 24 |
| Finished | Aug 17 04:25:48 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-966fcb83-95a4-443c-b96d-f6074e48dc6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004446367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1004446367 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3192642614 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3892360000 ps |
| CPU time | 15.64 seconds |
| Started | Aug 17 04:25:04 PM PDT 24 |
| Finished | Aug 17 04:25:34 PM PDT 24 |
| Peak memory | 144740 kb |
| Host | smart-7a933f6d-4056-4622-9a53-db962ca96313 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192642614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3192642614 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1175998202 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 14943240000 ps |
| CPU time | 45.65 seconds |
| Started | Aug 17 04:25:07 PM PDT 24 |
| Finished | Aug 17 04:26:31 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-6c20da61-0e29-43b1-a7c9-e299546470ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1175998202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1175998202 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2100372382 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5110040000 ps |
| CPU time | 17.33 seconds |
| Started | Aug 17 04:24:48 PM PDT 24 |
| Finished | Aug 17 04:25:20 PM PDT 24 |
| Peak memory | 143668 kb |
| Host | smart-fba84974-e853-4bf5-9446-fac187e56de4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100372382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2100372382 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2175515417 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4261260000 ps |
| CPU time | 15.63 seconds |
| Started | Aug 17 04:21:14 PM PDT 24 |
| Finished | Aug 17 04:21:43 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-58b97b5e-03d2-4a81-bba7-7512447f303d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175515417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2175515417 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3743990700 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7635920000 ps |
| CPU time | 29.19 seconds |
| Started | Aug 17 04:25:05 PM PDT 24 |
| Finished | Aug 17 04:26:01 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-ca172725-1164-405d-ad5f-aff6f24ed9aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3743990700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3743990700 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2029380428 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11106060000 ps |
| CPU time | 36.29 seconds |
| Started | Aug 17 04:25:12 PM PDT 24 |
| Finished | Aug 17 04:26:20 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-c97c7a61-8f35-4faa-b1e3-a3f29910d0ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029380428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2029380428 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3209926914 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 15072200000 ps |
| CPU time | 53.21 seconds |
| Started | Aug 17 04:21:10 PM PDT 24 |
| Finished | Aug 17 04:22:48 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-33d392bd-2706-4667-95ad-066971189e32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3209926914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3209926914 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3984018099 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13789420000 ps |
| CPU time | 41.62 seconds |
| Started | Aug 17 04:25:32 PM PDT 24 |
| Finished | Aug 17 04:26:48 PM PDT 24 |
| Peak memory | 144676 kb |
| Host | smart-aacf2729-e6ba-4899-afb4-6d1cc03ece56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984018099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3984018099 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.4031502024 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3541440000 ps |
| CPU time | 11.6 seconds |
| Started | Aug 17 04:25:10 PM PDT 24 |
| Finished | Aug 17 04:25:31 PM PDT 24 |
| Peak memory | 144528 kb |
| Host | smart-f9f7fa23-7ba3-4487-857c-98b6ab85e86b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031502024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.4031502024 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.417631335 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10078720000 ps |
| CPU time | 33.75 seconds |
| Started | Aug 17 04:22:30 PM PDT 24 |
| Finished | Aug 17 04:23:33 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-a122bde6-59d6-4a67-9452-e0ddbb835ad1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417631335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.417631335 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.935372144 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4953800000 ps |
| CPU time | 15.56 seconds |
| Started | Aug 17 04:25:40 PM PDT 24 |
| Finished | Aug 17 04:26:08 PM PDT 24 |
| Peak memory | 144480 kb |
| Host | smart-682c4ee5-efbf-474b-89bd-7a1c83fe2aa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935372144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.935372144 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3406573182 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3914680000 ps |
| CPU time | 12.53 seconds |
| Started | Aug 17 04:25:00 PM PDT 24 |
| Finished | Aug 17 04:25:23 PM PDT 24 |
| Peak memory | 144400 kb |
| Host | smart-84414ddd-1b58-4436-bb65-f695cf4c159d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3406573182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3406573182 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.627577562 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 8035200000 ps |
| CPU time | 24.54 seconds |
| Started | Aug 17 04:25:47 PM PDT 24 |
| Finished | Aug 17 04:26:33 PM PDT 24 |
| Peak memory | 143616 kb |
| Host | smart-3bce5952-fce0-41b0-a51e-dfcda237672f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627577562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.627577562 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.457971282 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9995640000 ps |
| CPU time | 32.48 seconds |
| Started | Aug 17 04:25:10 PM PDT 24 |
| Finished | Aug 17 04:26:09 PM PDT 24 |
| Peak memory | 144676 kb |
| Host | smart-e116b83a-86e0-4a58-9ff3-1c7d181b7157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457971282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.457971282 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3392243323 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 15317100000 ps |
| CPU time | 45.95 seconds |
| Started | Aug 17 04:26:00 PM PDT 24 |
| Finished | Aug 17 04:27:25 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-e5be3687-f698-4686-804d-2ea24bb540e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392243323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3392243323 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1250522828 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10822100000 ps |
| CPU time | 38.49 seconds |
| Started | Aug 17 04:24:04 PM PDT 24 |
| Finished | Aug 17 04:25:15 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-c4e44808-921a-4a51-a516-d68d44049c2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250522828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1250522828 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.240609078 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3387680000 ps |
| CPU time | 11.69 seconds |
| Started | Aug 17 04:25:39 PM PDT 24 |
| Finished | Aug 17 04:26:01 PM PDT 24 |
| Peak memory | 144424 kb |
| Host | smart-bed198b8-e101-4568-a5e6-8752de5b3760 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240609078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.240609078 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2652636411 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9939840000 ps |
| CPU time | 38.52 seconds |
| Started | Aug 17 04:24:25 PM PDT 24 |
| Finished | Aug 17 04:25:38 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-537b0432-35b6-401c-89b1-14cce241cc5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652636411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2652636411 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3279000960 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11788680000 ps |
| CPU time | 44.31 seconds |
| Started | Aug 17 04:21:13 PM PDT 24 |
| Finished | Aug 17 04:22:37 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-5be4f46a-4293-4481-9be9-9f99786c26f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279000960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3279000960 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1874695949 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5916660000 ps |
| CPU time | 18.33 seconds |
| Started | Aug 17 04:25:37 PM PDT 24 |
| Finished | Aug 17 04:26:10 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-9536973b-b9e8-4ba1-9d5c-6776144fd012 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1874695949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1874695949 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.4156552245 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4004580000 ps |
| CPU time | 15.12 seconds |
| Started | Aug 17 04:23:50 PM PDT 24 |
| Finished | Aug 17 04:24:18 PM PDT 24 |
| Peak memory | 144852 kb |
| Host | smart-8f77acce-612d-4f5b-9c16-a15eacddf5dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156552245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.4156552245 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2322338233 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 14801880000 ps |
| CPU time | 58.05 seconds |
| Started | Aug 17 04:25:38 PM PDT 24 |
| Finished | Aug 17 04:27:29 PM PDT 24 |
| Peak memory | 144528 kb |
| Host | smart-b8143652-9f8a-4577-bb9e-2d3a5a163f09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322338233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2322338233 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.487825204 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8081080000 ps |
| CPU time | 28.55 seconds |
| Started | Aug 17 04:22:15 PM PDT 24 |
| Finished | Aug 17 04:23:07 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-aaba6d7a-802b-436f-a4a6-f7c00f6d4440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487825204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.487825204 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3199840632 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11309420000 ps |
| CPU time | 43.55 seconds |
| Started | Aug 17 04:21:11 PM PDT 24 |
| Finished | Aug 17 04:22:35 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-88e3b644-b136-4e5a-953d-561eba567ba4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199840632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3199840632 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3816311522 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8946600000 ps |
| CPU time | 29.18 seconds |
| Started | Aug 17 04:25:25 PM PDT 24 |
| Finished | Aug 17 04:26:18 PM PDT 24 |
| Peak memory | 144676 kb |
| Host | smart-440de761-cb48-4fb4-9a53-d44067fa016f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816311522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3816311522 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.135723812 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13810500000 ps |
| CPU time | 42.54 seconds |
| Started | Aug 17 04:25:26 PM PDT 24 |
| Finished | Aug 17 04:26:44 PM PDT 24 |
| Peak memory | 144676 kb |
| Host | smart-b8368cec-33a5-4b9c-8c8e-1d27c19fd4ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135723812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.135723812 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3527459321 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12383880000 ps |
| CPU time | 44.84 seconds |
| Started | Aug 17 04:21:13 PM PDT 24 |
| Finished | Aug 17 04:22:37 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-95f86f9a-9ff8-4a8d-bfed-489d3e5790d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527459321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3527459321 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.688278439 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4667980000 ps |
| CPU time | 16.29 seconds |
| Started | Aug 17 04:25:48 PM PDT 24 |
| Finished | Aug 17 04:26:18 PM PDT 24 |
| Peak memory | 144708 kb |
| Host | smart-7a2d871f-324a-43f2-aca6-6f0e848ce585 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688278439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.688278439 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2977667638 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12458900000 ps |
| CPU time | 41.03 seconds |
| Started | Aug 17 04:25:47 PM PDT 24 |
| Finished | Aug 17 04:27:04 PM PDT 24 |
| Peak memory | 143864 kb |
| Host | smart-a5661891-63bf-44a4-94ea-2afe6095718f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977667638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2977667638 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2294414746 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8549180000 ps |
| CPU time | 29.16 seconds |
| Started | Aug 17 04:25:12 PM PDT 24 |
| Finished | Aug 17 04:26:05 PM PDT 24 |
| Peak memory | 144740 kb |
| Host | smart-a43e7a4d-d0bc-49b2-9ae4-daa24b06c365 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294414746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2294414746 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.24221549 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12817880000 ps |
| CPU time | 42.84 seconds |
| Started | Aug 17 04:25:26 PM PDT 24 |
| Finished | Aug 17 04:26:46 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-31da43da-0646-423c-bb86-18fbee12fe98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24221549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.24221549 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1962556711 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9303100000 ps |
| CPU time | 34 seconds |
| Started | Aug 17 04:23:05 PM PDT 24 |
| Finished | Aug 17 04:24:08 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-be4413b9-2e1f-4ead-81d2-960e25f154a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962556711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1962556711 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2444350736 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7838660000 ps |
| CPU time | 27.06 seconds |
| Started | Aug 17 04:25:46 PM PDT 24 |
| Finished | Aug 17 04:26:37 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-c6df38f0-5cfc-4126-80c3-8698573d89cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444350736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2444350736 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.663725756 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11372660000 ps |
| CPU time | 38.08 seconds |
| Started | Aug 17 04:25:46 PM PDT 24 |
| Finished | Aug 17 04:26:57 PM PDT 24 |
| Peak memory | 144672 kb |
| Host | smart-2e1d8264-4022-434a-b19c-91aeddaaaeae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663725756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.663725756 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1452066506 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9161740000 ps |
| CPU time | 35.54 seconds |
| Started | Aug 17 04:21:35 PM PDT 24 |
| Finished | Aug 17 04:22:42 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-c54d5431-78c4-4907-926e-1c6fa41f0280 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452066506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1452066506 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.6527795 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 15244560000 ps |
| CPU time | 50.37 seconds |
| Started | Aug 17 04:24:53 PM PDT 24 |
| Finished | Aug 17 04:26:28 PM PDT 24 |
| Peak memory | 144700 kb |
| Host | smart-255088a7-e6ea-4a88-adcf-8862b8d81f08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6527795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.6527795 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3619575763 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 8094720000 ps |
| CPU time | 31.39 seconds |
| Started | Aug 17 04:21:57 PM PDT 24 |
| Finished | Aug 17 04:22:56 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-3db15360-7d30-48d6-8dfe-5bfd6b5bffa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3619575763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3619575763 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3358391796 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3274840000 ps |
| CPU time | 10.78 seconds |
| Started | Aug 17 04:25:14 PM PDT 24 |
| Finished | Aug 17 04:25:34 PM PDT 24 |
| Peak memory | 144720 kb |
| Host | smart-9680b1f3-9274-44c1-a86c-51717addc1a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3358391796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3358391796 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2846111968 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5798860000 ps |
| CPU time | 23.8 seconds |
| Started | Aug 17 04:23:42 PM PDT 24 |
| Finished | Aug 17 04:24:28 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-fc294902-8c9a-467d-9467-a31218ac57f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846111968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2846111968 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1370188493 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4702080000 ps |
| CPU time | 16.76 seconds |
| Started | Aug 17 04:25:26 PM PDT 24 |
| Finished | Aug 17 04:25:57 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-7088d39b-fe54-4cb4-9542-40aaba7f65f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370188493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1370188493 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3348784472 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7543540000 ps |
| CPU time | 29.69 seconds |
| Started | Aug 17 04:21:47 PM PDT 24 |
| Finished | Aug 17 04:22:43 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-9854d6f4-271f-43b2-844f-a42ead8b9881 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348784472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3348784472 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.514910664 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11843240000 ps |
| CPU time | 38.21 seconds |
| Started | Aug 17 04:25:26 PM PDT 24 |
| Finished | Aug 17 04:26:37 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-a479c1c1-5ee2-42d7-8bac-aa88bb67e0a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514910664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.514910664 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.927639660 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11692580000 ps |
| CPU time | 38.07 seconds |
| Started | Aug 17 04:24:48 PM PDT 24 |
| Finished | Aug 17 04:25:58 PM PDT 24 |
| Peak memory | 144528 kb |
| Host | smart-2a66a228-ceb1-4ce8-9362-7f283e8ad470 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927639660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.927639660 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1669142284 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11496660000 ps |
| CPU time | 42.54 seconds |
| Started | Aug 17 04:23:33 PM PDT 24 |
| Finished | Aug 17 04:24:53 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-78c8741a-b6a2-4d5a-aa1a-dafbbaef5918 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669142284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1669142284 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1612204159 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9054480000 ps |
| CPU time | 37.02 seconds |
| Started | Aug 17 04:23:46 PM PDT 24 |
| Finished | Aug 17 04:24:55 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-2835905d-714b-40e1-a6c6-331cf8468cb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612204159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1612204159 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2851899498 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3978540000 ps |
| CPU time | 15.52 seconds |
| Started | Aug 17 04:22:56 PM PDT 24 |
| Finished | Aug 17 04:23:25 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-74f32afd-2fef-4aec-9ba5-b07742f77f72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851899498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2851899498 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.992607143 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11001280000 ps |
| CPU time | 38.17 seconds |
| Started | Aug 17 04:21:12 PM PDT 24 |
| Finished | Aug 17 04:22:23 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-a3c3b5e1-80a3-42de-b2ab-2d8d3374aed0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992607143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.992607143 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |