| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/15.prim_present_test.3906125793 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1944292111 |
| /workspace/coverage/default/1.prim_present_test.55584959 |
| /workspace/coverage/default/10.prim_present_test.4064227084 |
| /workspace/coverage/default/11.prim_present_test.2965964633 |
| /workspace/coverage/default/12.prim_present_test.3550941056 |
| /workspace/coverage/default/13.prim_present_test.960031253 |
| /workspace/coverage/default/14.prim_present_test.3710241064 |
| /workspace/coverage/default/16.prim_present_test.411977331 |
| /workspace/coverage/default/17.prim_present_test.4071994298 |
| /workspace/coverage/default/18.prim_present_test.1024125967 |
| /workspace/coverage/default/19.prim_present_test.1734111695 |
| /workspace/coverage/default/2.prim_present_test.1501730450 |
| /workspace/coverage/default/20.prim_present_test.737240570 |
| /workspace/coverage/default/21.prim_present_test.4065709322 |
| /workspace/coverage/default/22.prim_present_test.396042131 |
| /workspace/coverage/default/23.prim_present_test.1602863256 |
| /workspace/coverage/default/24.prim_present_test.816960506 |
| /workspace/coverage/default/25.prim_present_test.2262865369 |
| /workspace/coverage/default/26.prim_present_test.2163020988 |
| /workspace/coverage/default/27.prim_present_test.1037550308 |
| /workspace/coverage/default/28.prim_present_test.3267955391 |
| /workspace/coverage/default/29.prim_present_test.1073317847 |
| /workspace/coverage/default/3.prim_present_test.3119585214 |
| /workspace/coverage/default/30.prim_present_test.2238574620 |
| /workspace/coverage/default/31.prim_present_test.1663567809 |
| /workspace/coverage/default/32.prim_present_test.1271804441 |
| /workspace/coverage/default/33.prim_present_test.2661155732 |
| /workspace/coverage/default/34.prim_present_test.14268401 |
| /workspace/coverage/default/35.prim_present_test.1164638780 |
| /workspace/coverage/default/36.prim_present_test.4179866419 |
| /workspace/coverage/default/37.prim_present_test.272958579 |
| /workspace/coverage/default/38.prim_present_test.1840825404 |
| /workspace/coverage/default/39.prim_present_test.3023416026 |
| /workspace/coverage/default/4.prim_present_test.2577807434 |
| /workspace/coverage/default/40.prim_present_test.2168266804 |
| /workspace/coverage/default/41.prim_present_test.2468680223 |
| /workspace/coverage/default/42.prim_present_test.1915029214 |
| /workspace/coverage/default/43.prim_present_test.3533687207 |
| /workspace/coverage/default/44.prim_present_test.3327832360 |
| /workspace/coverage/default/45.prim_present_test.3589676308 |
| /workspace/coverage/default/46.prim_present_test.188725342 |
| /workspace/coverage/default/47.prim_present_test.1632320155 |
| /workspace/coverage/default/48.prim_present_test.1622496738 |
| /workspace/coverage/default/49.prim_present_test.4033250516 |
| /workspace/coverage/default/5.prim_present_test.1918060565 |
| /workspace/coverage/default/6.prim_present_test.3180362805 |
| /workspace/coverage/default/7.prim_present_test.1075913897 |
| /workspace/coverage/default/8.prim_present_test.74765363 |
| /workspace/coverage/default/9.prim_present_test.2318572229 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/48.prim_present_test.1622496738 | Aug 18 04:23:33 PM PDT 24 | Aug 18 04:25:13 PM PDT 24 | 14735540000 ps | ||
| T2 | /workspace/coverage/default/5.prim_present_test.1918060565 | Aug 18 04:20:16 PM PDT 24 | Aug 18 04:21:49 PM PDT 24 | 13644340000 ps | ||
| T3 | /workspace/coverage/default/16.prim_present_test.411977331 | Aug 18 04:23:13 PM PDT 24 | Aug 18 04:24:12 PM PDT 24 | 9583340000 ps | ||
| T4 | /workspace/coverage/default/17.prim_present_test.4071994298 | Aug 18 04:23:12 PM PDT 24 | Aug 18 04:24:13 PM PDT 24 | 11175500000 ps | ||
| T5 | /workspace/coverage/default/6.prim_present_test.3180362805 | Aug 18 04:21:55 PM PDT 24 | Aug 18 04:22:54 PM PDT 24 | 10148780000 ps | ||
| T6 | /workspace/coverage/default/29.prim_present_test.1073317847 | Aug 18 04:23:13 PM PDT 24 | Aug 18 04:23:35 PM PDT 24 | 3581120000 ps | ||
| T7 | /workspace/coverage/default/46.prim_present_test.188725342 | Aug 18 04:23:18 PM PDT 24 | Aug 18 04:23:44 PM PDT 24 | 4149040000 ps | ||
| T8 | /workspace/coverage/default/28.prim_present_test.3267955391 | Aug 18 04:23:36 PM PDT 24 | Aug 18 04:24:41 PM PDT 24 | 9462440000 ps | ||
| T9 | /workspace/coverage/default/2.prim_present_test.1501730450 | Aug 18 04:22:47 PM PDT 24 | Aug 18 04:23:17 PM PDT 24 | 6159700000 ps | ||
| T10 | /workspace/coverage/default/15.prim_present_test.3906125793 | Aug 18 04:23:10 PM PDT 24 | Aug 18 04:24:40 PM PDT 24 | 14535900000 ps | ||
| T11 | /workspace/coverage/default/18.prim_present_test.1024125967 | Aug 18 04:23:11 PM PDT 24 | Aug 18 04:24:03 PM PDT 24 | 10054540000 ps | ||
| T12 | /workspace/coverage/default/8.prim_present_test.74765363 | Aug 18 04:23:09 PM PDT 24 | Aug 18 04:24:05 PM PDT 24 | 9961540000 ps | ||
| T13 | /workspace/coverage/default/38.prim_present_test.1840825404 | Aug 18 04:23:09 PM PDT 24 | Aug 18 04:24:33 PM PDT 24 | 13233280000 ps | ||
| T14 | /workspace/coverage/default/49.prim_present_test.4033250516 | Aug 18 04:23:17 PM PDT 24 | Aug 18 04:24:34 PM PDT 24 | 13703860000 ps | ||
| T15 | /workspace/coverage/default/26.prim_present_test.2163020988 | Aug 18 04:23:18 PM PDT 24 | Aug 18 04:24:43 PM PDT 24 | 12620100000 ps | ||
| T16 | /workspace/coverage/default/35.prim_present_test.1164638780 | Aug 18 04:23:14 PM PDT 24 | Aug 18 04:23:44 PM PDT 24 | 4745480000 ps | ||
| T17 | /workspace/coverage/default/39.prim_present_test.3023416026 | Aug 18 04:23:09 PM PDT 24 | Aug 18 04:24:10 PM PDT 24 | 11178600000 ps | ||
| T18 | /workspace/coverage/default/7.prim_present_test.1075913897 | Aug 18 04:23:01 PM PDT 24 | Aug 18 04:24:22 PM PDT 24 | 14962460000 ps | ||
| T19 | /workspace/coverage/default/33.prim_present_test.2661155732 | Aug 18 04:23:34 PM PDT 24 | Aug 18 04:24:26 PM PDT 24 | 8672560000 ps | ||
| T20 | /workspace/coverage/default/37.prim_present_test.272958579 | Aug 18 04:23:14 PM PDT 24 | Aug 18 04:24:01 PM PDT 24 | 8081700000 ps | ||
| T21 | /workspace/coverage/default/20.prim_present_test.737240570 | Aug 18 04:23:10 PM PDT 24 | Aug 18 04:24:46 PM PDT 24 | 14199240000 ps | ||
| T22 | /workspace/coverage/default/23.prim_present_test.1602863256 | Aug 18 04:23:33 PM PDT 24 | Aug 18 04:24:45 PM PDT 24 | 12565540000 ps | ||
| T23 | /workspace/coverage/default/27.prim_present_test.1037550308 | Aug 18 04:23:34 PM PDT 24 | Aug 18 04:24:16 PM PDT 24 | 6392200000 ps | ||
| T24 | /workspace/coverage/default/0.prim_present_test.1944292111 | Aug 18 04:17:17 PM PDT 24 | Aug 18 04:18:43 PM PDT 24 | 11873620000 ps | ||
| T25 | /workspace/coverage/default/1.prim_present_test.55584959 | Aug 18 04:22:29 PM PDT 24 | Aug 18 04:23:19 PM PDT 24 | 7648940000 ps | ||
| T26 | /workspace/coverage/default/32.prim_present_test.1271804441 | Aug 18 04:23:09 PM PDT 24 | Aug 18 04:23:34 PM PDT 24 | 4251340000 ps | ||
| T27 | /workspace/coverage/default/10.prim_present_test.4064227084 | Aug 18 04:23:08 PM PDT 24 | Aug 18 04:24:27 PM PDT 24 | 13932020000 ps | ||
| T28 | /workspace/coverage/default/45.prim_present_test.3589676308 | Aug 18 04:23:12 PM PDT 24 | Aug 18 04:24:09 PM PDT 24 | 9164220000 ps | ||
| T29 | /workspace/coverage/default/3.prim_present_test.3119585214 | Aug 18 04:21:03 PM PDT 24 | Aug 18 04:23:05 PM PDT 24 | 14806840000 ps | ||
| T30 | /workspace/coverage/default/41.prim_present_test.2468680223 | Aug 18 04:23:18 PM PDT 24 | Aug 18 04:24:31 PM PDT 24 | 11215800000 ps | ||
| T31 | /workspace/coverage/default/19.prim_present_test.1734111695 | Aug 18 04:23:12 PM PDT 24 | Aug 18 04:24:03 PM PDT 24 | 9301240000 ps | ||
| T32 | /workspace/coverage/default/42.prim_present_test.1915029214 | Aug 18 04:23:29 PM PDT 24 | Aug 18 04:25:13 PM PDT 24 | 15230300000 ps | ||
| T33 | /workspace/coverage/default/13.prim_present_test.960031253 | Aug 18 04:23:03 PM PDT 24 | Aug 18 04:24:16 PM PDT 24 | 13837160000 ps | ||
| T34 | /workspace/coverage/default/22.prim_present_test.396042131 | Aug 18 04:23:09 PM PDT 24 | Aug 18 04:23:33 PM PDT 24 | 4293500000 ps | ||
| T35 | /workspace/coverage/default/30.prim_present_test.2238574620 | Aug 18 04:23:36 PM PDT 24 | Aug 18 04:24:02 PM PDT 24 | 3847100000 ps | ||
| T36 | /workspace/coverage/default/4.prim_present_test.2577807434 | Aug 18 04:22:16 PM PDT 24 | Aug 18 04:23:13 PM PDT 24 | 9549860000 ps | ||
| T37 | /workspace/coverage/default/25.prim_present_test.2262865369 | Aug 18 04:23:14 PM PDT 24 | Aug 18 04:23:36 PM PDT 24 | 3438520000 ps | ||
| T38 | /workspace/coverage/default/9.prim_present_test.2318572229 | Aug 18 04:23:07 PM PDT 24 | Aug 18 04:24:34 PM PDT 24 | 13823520000 ps | ||
| T39 | /workspace/coverage/default/24.prim_present_test.816960506 | Aug 18 04:23:12 PM PDT 24 | Aug 18 04:24:14 PM PDT 24 | 10128940000 ps | ||
| T40 | /workspace/coverage/default/34.prim_present_test.14268401 | Aug 18 04:23:14 PM PDT 24 | Aug 18 04:23:43 PM PDT 24 | 5199320000 ps | ||
| T41 | /workspace/coverage/default/21.prim_present_test.4065709322 | Aug 18 04:23:15 PM PDT 24 | Aug 18 04:23:40 PM PDT 24 | 3817340000 ps | ||
| T42 | /workspace/coverage/default/40.prim_present_test.2168266804 | Aug 18 04:23:26 PM PDT 24 | Aug 18 04:24:03 PM PDT 24 | 6106380000 ps | ||
| T43 | /workspace/coverage/default/47.prim_present_test.1632320155 | Aug 18 04:23:15 PM PDT 24 | Aug 18 04:24:07 PM PDT 24 | 8203840000 ps | ||
| T44 | /workspace/coverage/default/44.prim_present_test.3327832360 | Aug 18 04:23:10 PM PDT 24 | Aug 18 04:23:57 PM PDT 24 | 8195780000 ps | ||
| T45 | /workspace/coverage/default/14.prim_present_test.3710241064 | Aug 18 04:23:20 PM PDT 24 | Aug 18 04:23:55 PM PDT 24 | 5544040000 ps | ||
| T46 | /workspace/coverage/default/12.prim_present_test.3550941056 | Aug 18 04:23:04 PM PDT 24 | Aug 18 04:24:24 PM PDT 24 | 13383320000 ps | ||
| T47 | /workspace/coverage/default/11.prim_present_test.2965964633 | Aug 18 04:23:10 PM PDT 24 | Aug 18 04:24:30 PM PDT 24 | 14194280000 ps | ||
| T48 | /workspace/coverage/default/31.prim_present_test.1663567809 | Aug 18 04:23:11 PM PDT 24 | Aug 18 04:23:35 PM PDT 24 | 4535920000 ps | ||
| T49 | /workspace/coverage/default/43.prim_present_test.3533687207 | Aug 18 04:23:11 PM PDT 24 | Aug 18 04:23:38 PM PDT 24 | 4921560000 ps | ||
| T50 | /workspace/coverage/default/36.prim_present_test.4179866419 | Aug 18 04:23:12 PM PDT 24 | Aug 18 04:24:52 PM PDT 24 | 15009580000 ps |
| Test location | /workspace/coverage/default/15.prim_present_test.3906125793 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 14535900000 ps |
| CPU time | 47.65 seconds |
| Started | Aug 18 04:23:10 PM PDT 24 |
| Finished | Aug 18 04:24:40 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-14a883c9-56e7-47c1-ae29-dc772fb72b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906125793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3906125793 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1944292111 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11873620000 ps |
| CPU time | 44.94 seconds |
| Started | Aug 18 04:17:17 PM PDT 24 |
| Finished | Aug 18 04:18:43 PM PDT 24 |
| Peak memory | 143988 kb |
| Host | smart-3c1ace15-f937-414d-be8e-fb706aad7338 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944292111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1944292111 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.55584959 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7648940000 ps |
| CPU time | 26.82 seconds |
| Started | Aug 18 04:22:29 PM PDT 24 |
| Finished | Aug 18 04:23:19 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-de3391cf-a75e-4c49-950b-ac3a736040e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=55584959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.55584959 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.4064227084 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13932020000 ps |
| CPU time | 42.98 seconds |
| Started | Aug 18 04:23:08 PM PDT 24 |
| Finished | Aug 18 04:24:27 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-c77c734b-fbaa-4ce7-8b70-93bfaac4e257 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4064227084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.4064227084 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2965964633 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14194280000 ps |
| CPU time | 43.35 seconds |
| Started | Aug 18 04:23:10 PM PDT 24 |
| Finished | Aug 18 04:24:30 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-cde0ae7b-3f4e-4c5e-9fa5-193e7fd391f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2965964633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2965964633 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3550941056 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13383320000 ps |
| CPU time | 43.37 seconds |
| Started | Aug 18 04:23:04 PM PDT 24 |
| Finished | Aug 18 04:24:24 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-96d88934-2850-4eb8-aa7b-1b190947ed69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550941056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3550941056 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.960031253 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13837160000 ps |
| CPU time | 40.36 seconds |
| Started | Aug 18 04:23:03 PM PDT 24 |
| Finished | Aug 18 04:24:16 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-48a16a0d-b74a-4123-9c56-a109ffd85ee3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960031253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.960031253 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3710241064 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5544040000 ps |
| CPU time | 19.08 seconds |
| Started | Aug 18 04:23:20 PM PDT 24 |
| Finished | Aug 18 04:23:55 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-5921d53f-aef0-4a79-ad44-5a047b758b2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710241064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3710241064 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.411977331 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9583340000 ps |
| CPU time | 31.44 seconds |
| Started | Aug 18 04:23:13 PM PDT 24 |
| Finished | Aug 18 04:24:12 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-dd676d64-b3d9-4ce0-b576-5f3919ca54d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411977331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.411977331 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4071994298 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11175500000 ps |
| CPU time | 33.38 seconds |
| Started | Aug 18 04:23:12 PM PDT 24 |
| Finished | Aug 18 04:24:13 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-6f7dcae2-54f7-40e9-8c9f-c033d539ff73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4071994298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4071994298 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1024125967 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10054540000 ps |
| CPU time | 28.53 seconds |
| Started | Aug 18 04:23:11 PM PDT 24 |
| Finished | Aug 18 04:24:03 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-0329ec4e-20fb-4d50-946d-3a93c52839ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024125967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1024125967 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1734111695 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9301240000 ps |
| CPU time | 27.74 seconds |
| Started | Aug 18 04:23:12 PM PDT 24 |
| Finished | Aug 18 04:24:03 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-fd5c9df6-45f9-4b69-9489-ad692f3a9873 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734111695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1734111695 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1501730450 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6159700000 ps |
| CPU time | 16.29 seconds |
| Started | Aug 18 04:22:47 PM PDT 24 |
| Finished | Aug 18 04:23:17 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-ba28eebc-32e0-412f-9552-77e214d6a008 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1501730450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1501730450 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.737240570 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14199240000 ps |
| CPU time | 50.03 seconds |
| Started | Aug 18 04:23:10 PM PDT 24 |
| Finished | Aug 18 04:24:46 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-8e3803ad-c590-437b-9b0a-a49074eef670 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737240570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.737240570 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4065709322 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3817340000 ps |
| CPU time | 13.5 seconds |
| Started | Aug 18 04:23:15 PM PDT 24 |
| Finished | Aug 18 04:23:40 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-6b8ef2d3-832c-4ae6-a514-b5df1bc85185 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065709322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4065709322 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.396042131 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4293500000 ps |
| CPU time | 13.01 seconds |
| Started | Aug 18 04:23:09 PM PDT 24 |
| Finished | Aug 18 04:23:33 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-baa02cae-97a1-4272-a010-c1fc244fac63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396042131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.396042131 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1602863256 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12565540000 ps |
| CPU time | 38.54 seconds |
| Started | Aug 18 04:23:33 PM PDT 24 |
| Finished | Aug 18 04:24:45 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-914fd385-5678-439f-9988-ae27b242af1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1602863256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1602863256 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.816960506 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10128940000 ps |
| CPU time | 33.36 seconds |
| Started | Aug 18 04:23:12 PM PDT 24 |
| Finished | Aug 18 04:24:14 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-8c57acec-03ee-4453-b958-bb75813cbb7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816960506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.816960506 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2262865369 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3438520000 ps |
| CPU time | 11.6 seconds |
| Started | Aug 18 04:23:14 PM PDT 24 |
| Finished | Aug 18 04:23:36 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-5c14a8a1-8754-4116-8779-af18cae08002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2262865369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2262865369 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2163020988 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12620100000 ps |
| CPU time | 44.53 seconds |
| Started | Aug 18 04:23:18 PM PDT 24 |
| Finished | Aug 18 04:24:43 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-720c55f4-7cbc-414d-8ec3-7536b2e4d7f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163020988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2163020988 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1037550308 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6392200000 ps |
| CPU time | 22.15 seconds |
| Started | Aug 18 04:23:34 PM PDT 24 |
| Finished | Aug 18 04:24:16 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-16398409-9cb7-4bc8-a4aa-59dd5548b1de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037550308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1037550308 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3267955391 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9462440000 ps |
| CPU time | 34.47 seconds |
| Started | Aug 18 04:23:36 PM PDT 24 |
| Finished | Aug 18 04:24:41 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-434fda60-dbc6-4c79-9b46-ded22a9ef099 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267955391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3267955391 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1073317847 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3581120000 ps |
| CPU time | 12.03 seconds |
| Started | Aug 18 04:23:13 PM PDT 24 |
| Finished | Aug 18 04:23:35 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-7cffd56b-c4b6-4e42-96c2-557a6db2582a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073317847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1073317847 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3119585214 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14806840000 ps |
| CPU time | 62.92 seconds |
| Started | Aug 18 04:21:03 PM PDT 24 |
| Finished | Aug 18 04:23:05 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-7bc475da-34ce-434a-900e-dafd18817843 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119585214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3119585214 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2238574620 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3847100000 ps |
| CPU time | 13.41 seconds |
| Started | Aug 18 04:23:36 PM PDT 24 |
| Finished | Aug 18 04:24:02 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-5a3d1a47-3b5d-4763-995b-6e40483c95c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238574620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2238574620 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1663567809 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4535920000 ps |
| CPU time | 13.16 seconds |
| Started | Aug 18 04:23:11 PM PDT 24 |
| Finished | Aug 18 04:23:35 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-1847edbf-64d8-45f4-84a3-18f99b020d07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663567809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1663567809 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1271804441 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4251340000 ps |
| CPU time | 13.54 seconds |
| Started | Aug 18 04:23:09 PM PDT 24 |
| Finished | Aug 18 04:23:34 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-c98f6199-5da3-472d-b821-8da3aa1e42e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1271804441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1271804441 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2661155732 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8672560000 ps |
| CPU time | 28.04 seconds |
| Started | Aug 18 04:23:34 PM PDT 24 |
| Finished | Aug 18 04:24:26 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-e2183068-2fd4-4780-ae8e-b95d62b33668 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661155732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2661155732 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.14268401 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5199320000 ps |
| CPU time | 15.9 seconds |
| Started | Aug 18 04:23:14 PM PDT 24 |
| Finished | Aug 18 04:23:43 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-40f4704e-d60c-4435-8083-8645d1f5dc7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14268401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.14268401 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1164638780 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4745480000 ps |
| CPU time | 15.89 seconds |
| Started | Aug 18 04:23:14 PM PDT 24 |
| Finished | Aug 18 04:23:44 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-c8b8f60c-af99-4de0-878d-31e963765e4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164638780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1164638780 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4179866419 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15009580000 ps |
| CPU time | 52.27 seconds |
| Started | Aug 18 04:23:12 PM PDT 24 |
| Finished | Aug 18 04:24:52 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-fa7b9ba5-1f16-43fc-be5d-10c2ac3ea84a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179866419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4179866419 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.272958579 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8081700000 ps |
| CPU time | 25.48 seconds |
| Started | Aug 18 04:23:14 PM PDT 24 |
| Finished | Aug 18 04:24:01 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-d8b3dc8d-d5d4-4942-8113-146d8f2c9a29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272958579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.272958579 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1840825404 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13233280000 ps |
| CPU time | 44.28 seconds |
| Started | Aug 18 04:23:09 PM PDT 24 |
| Finished | Aug 18 04:24:33 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-7e69f36c-9cd9-426e-b353-6a0f5e333853 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840825404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1840825404 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3023416026 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11178600000 ps |
| CPU time | 33.21 seconds |
| Started | Aug 18 04:23:09 PM PDT 24 |
| Finished | Aug 18 04:24:10 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-21829687-7f07-483f-ae36-0f93136a18aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023416026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3023416026 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2577807434 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9549860000 ps |
| CPU time | 31.06 seconds |
| Started | Aug 18 04:22:16 PM PDT 24 |
| Finished | Aug 18 04:23:13 PM PDT 24 |
| Peak memory | 144792 kb |
| Host | smart-3848a7ce-a241-41ce-a26e-298888cc0bae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2577807434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2577807434 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2168266804 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6106380000 ps |
| CPU time | 19.55 seconds |
| Started | Aug 18 04:23:26 PM PDT 24 |
| Finished | Aug 18 04:24:03 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-8ab64a9c-87ae-4093-8327-9bfe52ed4711 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2168266804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2168266804 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2468680223 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11215800000 ps |
| CPU time | 38.43 seconds |
| Started | Aug 18 04:23:18 PM PDT 24 |
| Finished | Aug 18 04:24:31 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-e00e8185-89ae-4dd3-bf13-baf6023b43d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468680223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2468680223 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1915029214 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 15230300000 ps |
| CPU time | 54.71 seconds |
| Started | Aug 18 04:23:29 PM PDT 24 |
| Finished | Aug 18 04:25:13 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-4992ba86-d7d2-44e1-a0a1-0a76ab74899f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915029214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1915029214 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3533687207 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4921560000 ps |
| CPU time | 14.55 seconds |
| Started | Aug 18 04:23:11 PM PDT 24 |
| Finished | Aug 18 04:23:38 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-d4e3da51-f2f9-4558-b03c-5e383d34f93f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533687207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3533687207 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3327832360 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8195780000 ps |
| CPU time | 25.26 seconds |
| Started | Aug 18 04:23:10 PM PDT 24 |
| Finished | Aug 18 04:23:57 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-7100a766-a630-429f-9323-00b8f386c9d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3327832360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3327832360 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3589676308 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9164220000 ps |
| CPU time | 30.39 seconds |
| Started | Aug 18 04:23:12 PM PDT 24 |
| Finished | Aug 18 04:24:09 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-0847c5c3-1a53-46ac-ac91-305a06a6c867 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589676308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3589676308 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.188725342 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4149040000 ps |
| CPU time | 14.2 seconds |
| Started | Aug 18 04:23:18 PM PDT 24 |
| Finished | Aug 18 04:23:44 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-2d681e20-9de2-42cc-9402-45d01bfe72ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=188725342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.188725342 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1632320155 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8203840000 ps |
| CPU time | 27.47 seconds |
| Started | Aug 18 04:23:15 PM PDT 24 |
| Finished | Aug 18 04:24:07 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-38218412-1108-4bc2-a174-733fe380ad23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632320155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1632320155 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1622496738 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14735540000 ps |
| CPU time | 52.26 seconds |
| Started | Aug 18 04:23:33 PM PDT 24 |
| Finished | Aug 18 04:25:13 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-fde9cf1d-cadb-4c19-bc2b-0f4347031f88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622496738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1622496738 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.4033250516 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13703860000 ps |
| CPU time | 42.01 seconds |
| Started | Aug 18 04:23:17 PM PDT 24 |
| Finished | Aug 18 04:24:34 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-19b6b517-a174-48ba-8cd7-e9883ffea21e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033250516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4033250516 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1918060565 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13644340000 ps |
| CPU time | 48.76 seconds |
| Started | Aug 18 04:20:16 PM PDT 24 |
| Finished | Aug 18 04:21:49 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-7fe00ef1-430b-4268-b2ed-555d754819b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1918060565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1918060565 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3180362805 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 10148780000 ps |
| CPU time | 32.19 seconds |
| Started | Aug 18 04:21:55 PM PDT 24 |
| Finished | Aug 18 04:22:54 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-2de9963b-7dfe-417d-9f61-d8cd99849aee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180362805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3180362805 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1075913897 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14962460000 ps |
| CPU time | 44.08 seconds |
| Started | Aug 18 04:23:01 PM PDT 24 |
| Finished | Aug 18 04:24:22 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-f4789535-8054-4841-825e-ef67160ce92c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075913897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1075913897 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.74765363 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9961540000 ps |
| CPU time | 29.97 seconds |
| Started | Aug 18 04:23:09 PM PDT 24 |
| Finished | Aug 18 04:24:05 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-625c7520-15e8-4bd9-a5c7-63089b1aa771 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74765363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.74765363 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2318572229 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13823520000 ps |
| CPU time | 46.06 seconds |
| Started | Aug 18 04:23:07 PM PDT 24 |
| Finished | Aug 18 04:24:34 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-811e4282-bc79-4005-929a-d973d829f5c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318572229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2318572229 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |