| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.1184104304 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.3466520719 |
| /workspace/coverage/default/10.prim_present_test.2168734476 |
| /workspace/coverage/default/11.prim_present_test.4219182846 |
| /workspace/coverage/default/12.prim_present_test.3029806113 |
| /workspace/coverage/default/13.prim_present_test.2895902683 |
| /workspace/coverage/default/14.prim_present_test.2809966680 |
| /workspace/coverage/default/15.prim_present_test.189848413 |
| /workspace/coverage/default/16.prim_present_test.3266529605 |
| /workspace/coverage/default/17.prim_present_test.2005468245 |
| /workspace/coverage/default/18.prim_present_test.1947447674 |
| /workspace/coverage/default/19.prim_present_test.3352229939 |
| /workspace/coverage/default/2.prim_present_test.1315850626 |
| /workspace/coverage/default/20.prim_present_test.3415105349 |
| /workspace/coverage/default/21.prim_present_test.1441224985 |
| /workspace/coverage/default/22.prim_present_test.3291365779 |
| /workspace/coverage/default/23.prim_present_test.3903386376 |
| /workspace/coverage/default/24.prim_present_test.3449357879 |
| /workspace/coverage/default/25.prim_present_test.2591606245 |
| /workspace/coverage/default/26.prim_present_test.99058763 |
| /workspace/coverage/default/27.prim_present_test.1915986652 |
| /workspace/coverage/default/28.prim_present_test.2831477034 |
| /workspace/coverage/default/29.prim_present_test.1956721579 |
| /workspace/coverage/default/3.prim_present_test.1377301409 |
| /workspace/coverage/default/30.prim_present_test.3325693159 |
| /workspace/coverage/default/31.prim_present_test.3695417859 |
| /workspace/coverage/default/32.prim_present_test.558971219 |
| /workspace/coverage/default/33.prim_present_test.3934503995 |
| /workspace/coverage/default/34.prim_present_test.3778960895 |
| /workspace/coverage/default/35.prim_present_test.3864175911 |
| /workspace/coverage/default/36.prim_present_test.762325872 |
| /workspace/coverage/default/37.prim_present_test.2551141430 |
| /workspace/coverage/default/38.prim_present_test.2696608034 |
| /workspace/coverage/default/39.prim_present_test.2160312753 |
| /workspace/coverage/default/4.prim_present_test.288427425 |
| /workspace/coverage/default/40.prim_present_test.1394980184 |
| /workspace/coverage/default/41.prim_present_test.1950184669 |
| /workspace/coverage/default/42.prim_present_test.1293019217 |
| /workspace/coverage/default/43.prim_present_test.2796224753 |
| /workspace/coverage/default/44.prim_present_test.3401654788 |
| /workspace/coverage/default/45.prim_present_test.1475643263 |
| /workspace/coverage/default/46.prim_present_test.769839952 |
| /workspace/coverage/default/47.prim_present_test.2423658284 |
| /workspace/coverage/default/48.prim_present_test.4039273655 |
| /workspace/coverage/default/49.prim_present_test.532267255 |
| /workspace/coverage/default/5.prim_present_test.3635733280 |
| /workspace/coverage/default/6.prim_present_test.980381431 |
| /workspace/coverage/default/7.prim_present_test.2998193767 |
| /workspace/coverage/default/8.prim_present_test.1474575461 |
| /workspace/coverage/default/9.prim_present_test.687576040 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/42.prim_present_test.1293019217 | Aug 19 04:31:10 PM PDT 24 | Aug 19 04:32:27 PM PDT 24 | 13085100000 ps | ||
| T2 | /workspace/coverage/default/47.prim_present_test.2423658284 | Aug 19 04:31:16 PM PDT 24 | Aug 19 04:32:20 PM PDT 24 | 8198880000 ps | ||
| T3 | /workspace/coverage/default/6.prim_present_test.980381431 | Aug 19 04:30:51 PM PDT 24 | Aug 19 04:32:33 PM PDT 24 | 13742300000 ps | ||
| T4 | /workspace/coverage/default/22.prim_present_test.3291365779 | Aug 19 04:31:19 PM PDT 24 | Aug 19 04:32:39 PM PDT 24 | 12393800000 ps | ||
| T5 | /workspace/coverage/default/49.prim_present_test.532267255 | Aug 19 04:31:21 PM PDT 24 | Aug 19 04:31:41 PM PDT 24 | 3560660000 ps | ||
| T6 | /workspace/coverage/default/13.prim_present_test.2895902683 | Aug 19 04:31:18 PM PDT 24 | Aug 19 04:32:33 PM PDT 24 | 11373280000 ps | ||
| T7 | /workspace/coverage/default/0.prim_present_test.1184104304 | Aug 19 04:31:01 PM PDT 24 | Aug 19 04:31:52 PM PDT 24 | 9047040000 ps | ||
| T8 | /workspace/coverage/default/8.prim_present_test.1474575461 | Aug 19 04:31:02 PM PDT 24 | Aug 19 04:32:09 PM PDT 24 | 12098680000 ps | ||
| T9 | /workspace/coverage/default/4.prim_present_test.288427425 | Aug 19 04:31:20 PM PDT 24 | Aug 19 04:32:55 PM PDT 24 | 12479980000 ps | ||
| T10 | /workspace/coverage/default/44.prim_present_test.3401654788 | Aug 19 04:31:15 PM PDT 24 | Aug 19 04:33:07 PM PDT 24 | 13537080000 ps | ||
| T11 | /workspace/coverage/default/43.prim_present_test.2796224753 | Aug 19 04:30:54 PM PDT 24 | Aug 19 04:32:12 PM PDT 24 | 11333600000 ps | ||
| T12 | /workspace/coverage/default/19.prim_present_test.3352229939 | Aug 19 04:31:08 PM PDT 24 | Aug 19 04:31:28 PM PDT 24 | 3204780000 ps | ||
| T13 | /workspace/coverage/default/36.prim_present_test.762325872 | Aug 19 04:30:57 PM PDT 24 | Aug 19 04:32:18 PM PDT 24 | 14746080000 ps | ||
| T14 | /workspace/coverage/default/11.prim_present_test.4219182846 | Aug 19 04:30:58 PM PDT 24 | Aug 19 04:31:32 PM PDT 24 | 5185060000 ps | ||
| T15 | /workspace/coverage/default/31.prim_present_test.3695417859 | Aug 19 04:31:01 PM PDT 24 | Aug 19 04:32:18 PM PDT 24 | 12611420000 ps | ||
| T16 | /workspace/coverage/default/23.prim_present_test.3903386376 | Aug 19 04:31:22 PM PDT 24 | Aug 19 04:32:28 PM PDT 24 | 9795380000 ps | ||
| T17 | /workspace/coverage/default/29.prim_present_test.1956721579 | Aug 19 04:31:21 PM PDT 24 | Aug 19 04:32:25 PM PDT 24 | 8799660000 ps | ||
| T18 | /workspace/coverage/default/7.prim_present_test.2998193767 | Aug 19 04:31:18 PM PDT 24 | Aug 19 04:32:26 PM PDT 24 | 11342900000 ps | ||
| T19 | /workspace/coverage/default/35.prim_present_test.3864175911 | Aug 19 04:31:02 PM PDT 24 | Aug 19 04:32:47 PM PDT 24 | 14586740000 ps | ||
| T20 | /workspace/coverage/default/32.prim_present_test.558971219 | Aug 19 04:30:53 PM PDT 24 | Aug 19 04:32:29 PM PDT 24 | 14123600000 ps | ||
| T21 | /workspace/coverage/default/21.prim_present_test.1441224985 | Aug 19 04:31:16 PM PDT 24 | Aug 19 04:32:51 PM PDT 24 | 14184360000 ps | ||
| T22 | /workspace/coverage/default/26.prim_present_test.99058763 | Aug 19 04:31:14 PM PDT 24 | Aug 19 04:32:42 PM PDT 24 | 14092600000 ps | ||
| T23 | /workspace/coverage/default/5.prim_present_test.3635733280 | Aug 19 04:31:01 PM PDT 24 | Aug 19 04:32:16 PM PDT 24 | 12859420000 ps | ||
| T24 | /workspace/coverage/default/12.prim_present_test.3029806113 | Aug 19 04:31:11 PM PDT 24 | Aug 19 04:32:08 PM PDT 24 | 10034080000 ps | ||
| T25 | /workspace/coverage/default/25.prim_present_test.2591606245 | Aug 19 04:30:51 PM PDT 24 | Aug 19 04:31:36 PM PDT 24 | 8180280000 ps | ||
| T26 | /workspace/coverage/default/40.prim_present_test.1394980184 | Aug 19 04:31:19 PM PDT 24 | Aug 19 04:32:37 PM PDT 24 | 10939900000 ps | ||
| T27 | /workspace/coverage/default/16.prim_present_test.3266529605 | Aug 19 04:31:18 PM PDT 24 | Aug 19 04:32:08 PM PDT 24 | 7456120000 ps | ||
| T28 | /workspace/coverage/default/34.prim_present_test.3778960895 | Aug 19 04:30:59 PM PDT 24 | Aug 19 04:31:25 PM PDT 24 | 3798120000 ps | ||
| T29 | /workspace/coverage/default/27.prim_present_test.1915986652 | Aug 19 04:31:16 PM PDT 24 | Aug 19 04:32:18 PM PDT 24 | 10927500000 ps | ||
| T30 | /workspace/coverage/default/10.prim_present_test.2168734476 | Aug 19 04:30:57 PM PDT 24 | Aug 19 04:31:56 PM PDT 24 | 10270300000 ps | ||
| T31 | /workspace/coverage/default/37.prim_present_test.2551141430 | Aug 19 04:31:06 PM PDT 24 | Aug 19 04:31:45 PM PDT 24 | 6315940000 ps | ||
| T32 | /workspace/coverage/default/39.prim_present_test.2160312753 | Aug 19 04:30:52 PM PDT 24 | Aug 19 04:32:34 PM PDT 24 | 14028120000 ps | ||
| T33 | /workspace/coverage/default/17.prim_present_test.2005468245 | Aug 19 04:31:14 PM PDT 24 | Aug 19 04:31:40 PM PDT 24 | 4022560000 ps | ||
| T34 | /workspace/coverage/default/2.prim_present_test.1315850626 | Aug 19 04:31:19 PM PDT 24 | Aug 19 04:32:14 PM PDT 24 | 6479620000 ps | ||
| T35 | /workspace/coverage/default/24.prim_present_test.3449357879 | Aug 19 04:31:18 PM PDT 24 | Aug 19 04:32:54 PM PDT 24 | 14132900000 ps | ||
| T36 | /workspace/coverage/default/38.prim_present_test.2696608034 | Aug 19 04:30:59 PM PDT 24 | Aug 19 04:32:19 PM PDT 24 | 10858060000 ps | ||
| T37 | /workspace/coverage/default/14.prim_present_test.2809966680 | Aug 19 04:31:17 PM PDT 24 | Aug 19 04:32:23 PM PDT 24 | 10345940000 ps | ||
| T38 | /workspace/coverage/default/30.prim_present_test.3325693159 | Aug 19 04:31:04 PM PDT 24 | Aug 19 04:32:49 PM PDT 24 | 14842800000 ps | ||
| T39 | /workspace/coverage/default/15.prim_present_test.189848413 | Aug 19 04:30:52 PM PDT 24 | Aug 19 04:31:33 PM PDT 24 | 7507580000 ps | ||
| T40 | /workspace/coverage/default/28.prim_present_test.2831477034 | Aug 19 04:31:20 PM PDT 24 | Aug 19 04:32:31 PM PDT 24 | 12142080000 ps | ||
| T41 | /workspace/coverage/default/20.prim_present_test.3415105349 | Aug 19 04:30:52 PM PDT 24 | Aug 19 04:31:20 PM PDT 24 | 5020140000 ps | ||
| T42 | /workspace/coverage/default/33.prim_present_test.3934503995 | Aug 19 04:30:52 PM PDT 24 | Aug 19 04:32:13 PM PDT 24 | 14095700000 ps | ||
| T43 | /workspace/coverage/default/45.prim_present_test.1475643263 | Aug 19 04:30:51 PM PDT 24 | Aug 19 04:31:48 PM PDT 24 | 8674420000 ps | ||
| T44 | /workspace/coverage/default/46.prim_present_test.769839952 | Aug 19 04:31:18 PM PDT 24 | Aug 19 04:32:11 PM PDT 24 | 8988140000 ps | ||
| T45 | /workspace/coverage/default/1.prim_present_test.3466520719 | Aug 19 04:31:07 PM PDT 24 | Aug 19 04:31:31 PM PDT 24 | 3870040000 ps | ||
| T46 | /workspace/coverage/default/48.prim_present_test.4039273655 | Aug 19 04:31:34 PM PDT 24 | Aug 19 04:32:25 PM PDT 24 | 6918580000 ps | ||
| T47 | /workspace/coverage/default/18.prim_present_test.1947447674 | Aug 19 04:31:07 PM PDT 24 | Aug 19 04:32:28 PM PDT 24 | 13305820000 ps | ||
| T48 | /workspace/coverage/default/41.prim_present_test.1950184669 | Aug 19 04:30:55 PM PDT 24 | Aug 19 04:31:44 PM PDT 24 | 7440000000 ps | ||
| T49 | /workspace/coverage/default/3.prim_present_test.1377301409 | Aug 19 04:31:21 PM PDT 24 | Aug 19 04:32:47 PM PDT 24 | 10745840000 ps | ||
| T50 | /workspace/coverage/default/9.prim_present_test.687576040 | Aug 19 04:31:14 PM PDT 24 | Aug 19 04:32:38 PM PDT 24 | 11707460000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.1184104304 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9047040000 ps |
| CPU time | 27.68 seconds |
| Started | Aug 19 04:31:01 PM PDT 24 |
| Finished | Aug 19 04:31:52 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-630e4cff-0510-447d-b32e-20f75749bce8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184104304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1184104304 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3466520719 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3870040000 ps |
| CPU time | 12.73 seconds |
| Started | Aug 19 04:31:07 PM PDT 24 |
| Finished | Aug 19 04:31:31 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-3f093f60-a186-47aa-a931-87356b99591b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466520719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3466520719 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2168734476 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10270300000 ps |
| CPU time | 31.46 seconds |
| Started | Aug 19 04:30:57 PM PDT 24 |
| Finished | Aug 19 04:31:56 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-c48e7e47-0c57-48c6-b7d4-bbaa948f9105 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2168734476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2168734476 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.4219182846 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5185060000 ps |
| CPU time | 18.03 seconds |
| Started | Aug 19 04:30:58 PM PDT 24 |
| Finished | Aug 19 04:31:32 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-53110724-7e8b-41f5-bef2-e71b4cba173f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219182846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4219182846 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3029806113 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10034080000 ps |
| CPU time | 30.67 seconds |
| Started | Aug 19 04:31:11 PM PDT 24 |
| Finished | Aug 19 04:32:08 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-37847876-b4f1-41cb-b484-c48454ee4b5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3029806113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3029806113 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2895902683 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11373280000 ps |
| CPU time | 39.41 seconds |
| Started | Aug 19 04:31:18 PM PDT 24 |
| Finished | Aug 19 04:32:33 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-21f506e6-56a0-4021-be58-24df016e4eab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895902683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2895902683 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2809966680 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10345940000 ps |
| CPU time | 34.82 seconds |
| Started | Aug 19 04:31:17 PM PDT 24 |
| Finished | Aug 19 04:32:23 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-3abcb9ef-83de-43fb-9bce-625b057f8704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809966680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2809966680 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.189848413 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7507580000 ps |
| CPU time | 21.96 seconds |
| Started | Aug 19 04:30:52 PM PDT 24 |
| Finished | Aug 19 04:31:33 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-5ef670ea-d862-4251-985d-08007616aeee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189848413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.189848413 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3266529605 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7456120000 ps |
| CPU time | 26.21 seconds |
| Started | Aug 19 04:31:18 PM PDT 24 |
| Finished | Aug 19 04:32:08 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-ce797ccf-3b2e-4101-ae81-ca8e554b0314 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266529605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3266529605 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2005468245 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4022560000 ps |
| CPU time | 13.48 seconds |
| Started | Aug 19 04:31:14 PM PDT 24 |
| Finished | Aug 19 04:31:40 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-5861dda8-9680-4ea1-95c3-23ae78114789 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005468245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2005468245 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1947447674 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13305820000 ps |
| CPU time | 44.17 seconds |
| Started | Aug 19 04:31:07 PM PDT 24 |
| Finished | Aug 19 04:32:28 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-0b3681cf-1cb7-4eff-85ca-9357f6887ff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947447674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1947447674 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3352229939 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3204780000 ps |
| CPU time | 10.69 seconds |
| Started | Aug 19 04:31:08 PM PDT 24 |
| Finished | Aug 19 04:31:28 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-e55a8947-35c2-427c-9c3c-2dfe694a3431 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352229939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3352229939 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1315850626 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6479620000 ps |
| CPU time | 28.19 seconds |
| Started | Aug 19 04:31:19 PM PDT 24 |
| Finished | Aug 19 04:32:14 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-0c884284-febe-47ed-a96f-1af132822fad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315850626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1315850626 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3415105349 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5020140000 ps |
| CPU time | 15.34 seconds |
| Started | Aug 19 04:30:52 PM PDT 24 |
| Finished | Aug 19 04:31:20 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-b9b6146c-5434-4f78-a053-9cbb7d4609f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415105349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3415105349 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1441224985 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14184360000 ps |
| CPU time | 50.08 seconds |
| Started | Aug 19 04:31:16 PM PDT 24 |
| Finished | Aug 19 04:32:51 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-eed30d08-2845-43db-94b8-467cf97c071d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441224985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1441224985 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3291365779 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12393800000 ps |
| CPU time | 42.25 seconds |
| Started | Aug 19 04:31:19 PM PDT 24 |
| Finished | Aug 19 04:32:39 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-ae0c8079-4413-48b6-83ec-687c586fa045 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291365779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3291365779 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3903386376 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9795380000 ps |
| CPU time | 34.87 seconds |
| Started | Aug 19 04:31:22 PM PDT 24 |
| Finished | Aug 19 04:32:28 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-74f853c4-3a86-491a-a0be-e8e239c678c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903386376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3903386376 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3449357879 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14132900000 ps |
| CPU time | 50.94 seconds |
| Started | Aug 19 04:31:18 PM PDT 24 |
| Finished | Aug 19 04:32:54 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-6288dabc-a00f-49cf-b672-3e5629fa88d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449357879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3449357879 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2591606245 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8180280000 ps |
| CPU time | 24.57 seconds |
| Started | Aug 19 04:30:51 PM PDT 24 |
| Finished | Aug 19 04:31:36 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-f69960f4-ad33-4c7a-a0e4-88b02bfb6bfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591606245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2591606245 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.99058763 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 14092600000 ps |
| CPU time | 47.11 seconds |
| Started | Aug 19 04:31:14 PM PDT 24 |
| Finished | Aug 19 04:32:42 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-e7179c55-34ee-4b13-bc3c-c757fb5016a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99058763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.99058763 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1915986652 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10927500000 ps |
| CPU time | 33.29 seconds |
| Started | Aug 19 04:31:16 PM PDT 24 |
| Finished | Aug 19 04:32:18 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-3f4eeb0d-03ec-4683-90b8-45807a78058b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915986652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1915986652 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2831477034 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12142080000 ps |
| CPU time | 38.76 seconds |
| Started | Aug 19 04:31:20 PM PDT 24 |
| Finished | Aug 19 04:32:31 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-2c73afe2-256b-40e3-b9f1-03c749cd0dfc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831477034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2831477034 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1956721579 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8799660000 ps |
| CPU time | 33.51 seconds |
| Started | Aug 19 04:31:21 PM PDT 24 |
| Finished | Aug 19 04:32:25 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-ce6ae6c0-8ade-42cd-9de7-f2c21778f171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1956721579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1956721579 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1377301409 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10745840000 ps |
| CPU time | 43.97 seconds |
| Started | Aug 19 04:31:21 PM PDT 24 |
| Finished | Aug 19 04:32:47 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-63f7ba23-3830-4021-a64c-37507da89cbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377301409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1377301409 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3325693159 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14842800000 ps |
| CPU time | 55.46 seconds |
| Started | Aug 19 04:31:04 PM PDT 24 |
| Finished | Aug 19 04:32:49 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-3a50224a-7f04-4c25-9874-8e9bc515b38a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325693159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3325693159 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3695417859 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12611420000 ps |
| CPU time | 41.13 seconds |
| Started | Aug 19 04:31:01 PM PDT 24 |
| Finished | Aug 19 04:32:18 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-ed1b7ac5-6754-4dd1-bcb8-2c04db59105b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3695417859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3695417859 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.558971219 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14123600000 ps |
| CPU time | 50.38 seconds |
| Started | Aug 19 04:30:53 PM PDT 24 |
| Finished | Aug 19 04:32:29 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-1d41af34-2e15-43b0-875f-d5b1d7cd1124 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=558971219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.558971219 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3934503995 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14095700000 ps |
| CPU time | 43.01 seconds |
| Started | Aug 19 04:30:52 PM PDT 24 |
| Finished | Aug 19 04:32:13 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-610c654f-b214-4104-b8a5-76c42f38a007 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934503995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3934503995 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3778960895 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3798120000 ps |
| CPU time | 13.73 seconds |
| Started | Aug 19 04:30:59 PM PDT 24 |
| Finished | Aug 19 04:31:25 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-c29b9d06-bf72-434a-b964-1ab4f5bf47d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778960895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3778960895 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3864175911 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14586740000 ps |
| CPU time | 54.63 seconds |
| Started | Aug 19 04:31:02 PM PDT 24 |
| Finished | Aug 19 04:32:47 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-7df8b32e-13ef-4636-adc8-8e1e15efd677 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864175911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3864175911 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.762325872 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14746080000 ps |
| CPU time | 43.86 seconds |
| Started | Aug 19 04:30:57 PM PDT 24 |
| Finished | Aug 19 04:32:18 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-c0ea9fb2-a276-446b-b3cd-ec7625157d8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762325872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.762325872 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2551141430 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6315940000 ps |
| CPU time | 20.87 seconds |
| Started | Aug 19 04:31:06 PM PDT 24 |
| Finished | Aug 19 04:31:45 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-261994be-1f3c-4832-94d5-253dd6dc7711 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551141430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2551141430 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2696608034 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10858060000 ps |
| CPU time | 42.83 seconds |
| Started | Aug 19 04:30:59 PM PDT 24 |
| Finished | Aug 19 04:32:19 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-cadee879-ebc7-42a7-829e-553c7fb06f00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2696608034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2696608034 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2160312753 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14028120000 ps |
| CPU time | 53.72 seconds |
| Started | Aug 19 04:30:52 PM PDT 24 |
| Finished | Aug 19 04:32:34 PM PDT 24 |
| Peak memory | 144284 kb |
| Host | smart-6ade7c46-ad41-46b6-b0da-43abb1f77d17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160312753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2160312753 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.288427425 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12479980000 ps |
| CPU time | 49.29 seconds |
| Started | Aug 19 04:31:20 PM PDT 24 |
| Finished | Aug 19 04:32:55 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-3a00c181-d855-40af-8229-81740e2c23f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288427425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.288427425 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1394980184 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10939900000 ps |
| CPU time | 41.04 seconds |
| Started | Aug 19 04:31:19 PM PDT 24 |
| Finished | Aug 19 04:32:37 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-77411371-88aa-45e5-ae53-036ffd24c64d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394980184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1394980184 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1950184669 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7440000000 ps |
| CPU time | 23.71 seconds |
| Started | Aug 19 04:30:55 PM PDT 24 |
| Finished | Aug 19 04:31:44 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-1da78bd9-25c1-4675-9cf1-c15114763acd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950184669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1950184669 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1293019217 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13085100000 ps |
| CPU time | 41.87 seconds |
| Started | Aug 19 04:31:10 PM PDT 24 |
| Finished | Aug 19 04:32:27 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-03423cfb-7589-4a62-8ed7-0e5218e5cac1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293019217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1293019217 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2796224753 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11333600000 ps |
| CPU time | 41.83 seconds |
| Started | Aug 19 04:30:54 PM PDT 24 |
| Finished | Aug 19 04:32:12 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-885ea57f-e6e9-4f8a-adf5-9a8edd2321d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796224753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2796224753 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3401654788 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13537080000 ps |
| CPU time | 56.94 seconds |
| Started | Aug 19 04:31:15 PM PDT 24 |
| Finished | Aug 19 04:33:07 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-5c373bd3-4afc-4b28-a064-dbbaa87d9a12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3401654788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3401654788 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1475643263 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8674420000 ps |
| CPU time | 30.43 seconds |
| Started | Aug 19 04:30:51 PM PDT 24 |
| Finished | Aug 19 04:31:48 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-0014ab57-f260-4123-a2d9-8878499ff6ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475643263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1475643263 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.769839952 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8988140000 ps |
| CPU time | 28.29 seconds |
| Started | Aug 19 04:31:18 PM PDT 24 |
| Finished | Aug 19 04:32:11 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-63a93069-bdae-459d-ba2e-9753fff7d86a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=769839952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.769839952 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2423658284 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8198880000 ps |
| CPU time | 32.93 seconds |
| Started | Aug 19 04:31:16 PM PDT 24 |
| Finished | Aug 19 04:32:20 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-b10aed8f-af56-485e-8a64-76c0f10be9e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423658284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2423658284 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4039273655 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6918580000 ps |
| CPU time | 26.77 seconds |
| Started | Aug 19 04:31:34 PM PDT 24 |
| Finished | Aug 19 04:32:25 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-795269df-a504-4f26-9bb6-045dea10c8a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4039273655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4039273655 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.532267255 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3560660000 ps |
| CPU time | 10.99 seconds |
| Started | Aug 19 04:31:21 PM PDT 24 |
| Finished | Aug 19 04:31:41 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-052ae617-ea1a-472e-95a7-4a906b2def75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532267255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.532267255 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3635733280 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12859420000 ps |
| CPU time | 39.63 seconds |
| Started | Aug 19 04:31:01 PM PDT 24 |
| Finished | Aug 19 04:32:16 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-bfe8c5b8-0d6b-4b7f-b2f7-085a8cd72735 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3635733280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3635733280 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.980381431 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13742300000 ps |
| CPU time | 52.94 seconds |
| Started | Aug 19 04:30:51 PM PDT 24 |
| Finished | Aug 19 04:32:33 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-aac93c3b-d64f-4628-8a1a-be0bd74fa746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980381431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.980381431 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2998193767 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11342900000 ps |
| CPU time | 36.49 seconds |
| Started | Aug 19 04:31:18 PM PDT 24 |
| Finished | Aug 19 04:32:26 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-761f14e6-fb90-4a11-9dba-9920a4ba5278 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998193767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2998193767 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1474575461 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12098680000 ps |
| CPU time | 36.05 seconds |
| Started | Aug 19 04:31:02 PM PDT 24 |
| Finished | Aug 19 04:32:09 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-57ef5fa8-e401-4d7b-8bbf-26d2b1aa1ed5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1474575461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1474575461 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.687576040 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11707460000 ps |
| CPU time | 43.49 seconds |
| Started | Aug 19 04:31:14 PM PDT 24 |
| Finished | Aug 19 04:32:38 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-46ae3b04-d2ba-49fe-bc63-ecbb2ba1a0ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687576040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.687576040 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |