| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/0.prim_present_test.1488095824 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/1.prim_present_test.1794012877 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/10.prim_present_test.3911603772 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/11.prim_present_test.922246629 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/12.prim_present_test.3714088657 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/13.prim_present_test.871423979 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/14.prim_present_test.526088213 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/15.prim_present_test.1645782365 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/16.prim_present_test.4263791470 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/17.prim_present_test.505995117 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/18.prim_present_test.3552481140 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/19.prim_present_test.1292962772 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/2.prim_present_test.3336899737 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/20.prim_present_test.4227308618 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/21.prim_present_test.1159570383 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/22.prim_present_test.630952485 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/23.prim_present_test.3240017985 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/24.prim_present_test.94944750 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/25.prim_present_test.4284199176 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/26.prim_present_test.3292656154 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/27.prim_present_test.5624254 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/28.prim_present_test.1811421497 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/29.prim_present_test.3091587029 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/3.prim_present_test.1746265366 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/30.prim_present_test.4058590033 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/31.prim_present_test.3453695379 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/32.prim_present_test.2920109893 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/33.prim_present_test.534555080 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/34.prim_present_test.3663401152 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/35.prim_present_test.2205037149 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/36.prim_present_test.1246734140 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/37.prim_present_test.3071448333 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/38.prim_present_test.2177288932 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/39.prim_present_test.1253389747 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/4.prim_present_test.1397992123 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/40.prim_present_test.2893716022 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/41.prim_present_test.2552679889 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/42.prim_present_test.530881013 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/43.prim_present_test.1166558225 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/44.prim_present_test.1581221877 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/45.prim_present_test.2869726799 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/46.prim_present_test.4206151093 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/47.prim_present_test.354231900 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/48.prim_present_test.2195040969 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/49.prim_present_test.167613192 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/5.prim_present_test.3458154204 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/6.prim_present_test.1084302446 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/7.prim_present_test.3232079993 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/8.prim_present_test.2168255093 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/9.prim_present_test.921584450 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/7.prim_present_test.3232079993 | Aug 22 10:29:23 PM UTC 24 | Aug 22 10:29:50 PM UTC 24 | 3574920000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/17.prim_present_test.505995117 | Aug 22 10:29:26 PM UTC 24 | Aug 22 10:29:51 PM UTC 24 | 3330020000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/1.prim_present_test.1794012877 | Aug 22 10:29:22 PM UTC 24 | Aug 22 10:30:00 PM UTC 24 | 5233420000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/0.prim_present_test.1488095824 | Aug 22 10:29:22 PM UTC 24 | Aug 22 10:30:02 PM UTC 24 | 5427480000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/11.prim_present_test.922246629 | Aug 22 10:29:23 PM UTC 24 | Aug 22 10:30:02 PM UTC 24 | 5230320000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/21.prim_present_test.1159570383 | Aug 22 10:29:34 PM UTC 24 | Aug 22 10:30:08 PM UTC 24 | 4540260000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/5.prim_present_test.3458154204 | Aug 22 10:29:22 PM UTC 24 | Aug 22 10:30:15 PM UTC 24 | 7396600000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/23.prim_present_test.3240017985 | Aug 22 10:29:52 PM UTC 24 | Aug 22 10:30:20 PM UTC 24 | 3763400000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/19.prim_present_test.1292962772 | Aug 22 10:29:28 PM UTC 24 | Aug 22 10:30:21 PM UTC 24 | 7314140000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/16.prim_present_test.4263791470 | Aug 22 10:29:26 PM UTC 24 | Aug 22 10:30:22 PM UTC 24 | 7719000000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/4.prim_present_test.1397992123 | Aug 22 10:29:22 PM UTC 24 | Aug 22 10:30:23 PM UTC 24 | 8425180000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/12.prim_present_test.3714088657 | Aug 22 10:29:23 PM UTC 24 | Aug 22 10:30:27 PM UTC 24 | 8857940000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/10.prim_present_test.3911603772 | Aug 22 10:29:23 PM UTC 24 | Aug 22 10:30:30 PM UTC 24 | 9198940000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/3.prim_present_test.1746265366 | Aug 22 10:29:22 PM UTC 24 | Aug 22 10:30:31 PM UTC 24 | 9609380000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/27.prim_present_test.5624254 | Aug 22 10:30:08 PM UTC 24 | Aug 22 10:30:37 PM UTC 24 | 3809280000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/22.prim_present_test.630952485 | Aug 22 10:29:51 PM UTC 24 | Aug 22 10:30:40 PM UTC 24 | 6652600000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/2.prim_present_test.3336899737 | Aug 22 10:29:22 PM UTC 24 | Aug 22 10:30:42 PM UTC 24 | 11202160000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/9.prim_present_test.921584450 | Aug 22 10:29:23 PM UTC 24 | Aug 22 10:30:43 PM UTC 24 | 11084980000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/26.prim_present_test.3292656154 | Aug 22 10:30:02 PM UTC 24 | Aug 22 10:30:43 PM UTC 24 | 5602320000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/18.prim_present_test.3552481140 | Aug 22 10:29:26 PM UTC 24 | Aug 22 10:30:44 PM UTC 24 | 10848760000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/20.prim_present_test.4227308618 | Aug 22 10:29:33 PM UTC 24 | Aug 22 10:30:46 PM UTC 24 | 10099180000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/14.prim_present_test.526088213 | Aug 22 10:29:25 PM UTC 24 | Aug 22 10:30:47 PM UTC 24 | 11456360000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/15.prim_present_test.1645782365 | Aug 22 10:29:26 PM UTC 24 | Aug 22 10:30:55 PM UTC 24 | 12378300000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/13.prim_present_test.871423979 | Aug 22 10:29:25 PM UTC 24 | Aug 22 10:30:55 PM UTC 24 | 12677140000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/35.prim_present_test.2205037149 | Aug 22 10:30:31 PM UTC 24 | Aug 22 10:30:57 PM UTC 24 | 3568100000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/6.prim_present_test.1084302446 | Aug 22 10:29:22 PM UTC 24 | Aug 22 10:31:03 PM UTC 24 | 14042380000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/34.prim_present_test.3663401152 | Aug 22 10:30:29 PM UTC 24 | Aug 22 10:31:07 PM UTC 24 | 5232800000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/8.prim_present_test.2168255093 | Aug 22 10:29:23 PM UTC 24 | Aug 22 10:31:10 PM UTC 24 | 14892400000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/28.prim_present_test.1811421497 | Aug 22 10:30:16 PM UTC 24 | Aug 22 10:31:14 PM UTC 24 | 7923600000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/37.prim_present_test.3071448333 | Aug 22 10:30:38 PM UTC 24 | Aug 22 10:31:14 PM UTC 24 | 4928380000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/33.prim_present_test.534555080 | Aug 22 10:30:23 PM UTC 24 | Aug 22 10:31:15 PM UTC 24 | 6978100000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/39.prim_present_test.1253389747 | Aug 22 10:30:43 PM UTC 24 | Aug 22 10:31:22 PM UTC 24 | 5356180000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/29.prim_present_test.3091587029 | Aug 22 10:30:21 PM UTC 24 | Aug 22 10:31:26 PM UTC 24 | 9006740000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/38.prim_present_test.2177288932 | Aug 22 10:30:41 PM UTC 24 | Aug 22 10:31:26 PM UTC 24 | 6272540000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/25.prim_present_test.4284199176 | Aug 22 10:30:02 PM UTC 24 | Aug 22 10:31:28 PM UTC 24 | 11904620000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/30.prim_present_test.4058590033 | Aug 22 10:30:21 PM UTC 24 | Aug 22 10:31:29 PM UTC 24 | 9396100000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/24.prim_present_test.94944750 | Aug 22 10:30:01 PM UTC 24 | Aug 22 10:31:39 PM UTC 24 | 13930780000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/31.prim_present_test.3453695379 | Aug 22 10:30:22 PM UTC 24 | Aug 22 10:31:52 PM UTC 24 | 12806100000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/32.prim_present_test.2920109893 | Aug 22 10:30:23 PM UTC 24 | Aug 22 10:31:52 PM UTC 24 | 12761460000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/36.prim_present_test.1246734140 | Aug 22 10:30:32 PM UTC 24 | Aug 22 10:31:53 PM UTC 24 | 11686380000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/41.prim_present_test.2552679889 | Aug 22 10:30:44 PM UTC 24 | Aug 22 10:31:57 PM UTC 24 | 10660280000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/40.prim_present_test.2893716022 | Aug 22 10:30:44 PM UTC 24 | Aug 22 10:32:04 PM UTC 24 | 11756440000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/42.prim_present_test.530881013 | Aug 22 10:30:45 PM UTC 24 | Aug 22 10:32:15 PM UTC 24 | 13356040000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/43.prim_present_test.1166558225 | Aug 22 10:30:47 PM UTC 24 | Aug 22 10:32:20 PM UTC 24 | 14021920000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/45.prim_present_test.2869726799 | Aug 22 10:30:56 PM UTC 24 | Aug 22 10:32:21 PM UTC 24 | 12792460000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/48.prim_present_test.2195040969 | Aug 22 10:31:03 PM UTC 24 | Aug 22 10:32:23 PM UTC 24 | 12098060000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/44.prim_present_test.1581221877 | Aug 22 10:30:48 PM UTC 24 | Aug 22 10:32:25 PM UTC 24 | 14591080000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/46.prim_present_test.4206151093 | Aug 22 10:30:56 PM UTC 24 | Aug 22 10:32:26 PM UTC 24 | 13659220000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/47.prim_present_test.354231900 | Aug 22 10:30:58 PM UTC 24 | Aug 22 10:32:31 PM UTC 24 | 14234580000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/49.prim_present_test.167613192 | Aug 22 10:31:08 PM UTC 24 | Aug 22 10:32:41 PM UTC 24 | 14501800000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/0.prim_present_test.1488095824 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5427480000 ps |
| CPU time | 11.37 seconds |
| Started | Aug 22 10:29:22 PM UTC 24 |
| Finished | Aug 22 10:30:02 PM UTC 24 |
| Peak memory | 151740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488095824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1488095824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/1.prim_present_test.1794012877 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5233420000 ps |
| CPU time | 11.12 seconds |
| Started | Aug 22 10:29:22 PM UTC 24 |
| Finished | Aug 22 10:30:00 PM UTC 24 |
| Peak memory | 151444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794012877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1794012877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/10.prim_present_test.3911603772 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9198940000 ps |
| CPU time | 18.22 seconds |
| Started | Aug 22 10:29:23 PM UTC 24 |
| Finished | Aug 22 10:30:30 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911603772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3911603772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/11.prim_present_test.922246629 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5230320000 ps |
| CPU time | 10.79 seconds |
| Started | Aug 22 10:29:23 PM UTC 24 |
| Finished | Aug 22 10:30:02 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922246629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.922246629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/12.prim_present_test.3714088657 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8857940000 ps |
| CPU time | 17.58 seconds |
| Started | Aug 22 10:29:23 PM UTC 24 |
| Finished | Aug 22 10:30:27 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714088657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3714088657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/13.prim_present_test.871423979 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12677140000 ps |
| CPU time | 25.15 seconds |
| Started | Aug 22 10:29:25 PM UTC 24 |
| Finished | Aug 22 10:30:55 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871423979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.871423979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/14.prim_present_test.526088213 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11456360000 ps |
| CPU time | 25.24 seconds |
| Started | Aug 22 10:29:25 PM UTC 24 |
| Finished | Aug 22 10:30:47 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526088213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.526088213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/15.prim_present_test.1645782365 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12378300000 ps |
| CPU time | 24.87 seconds |
| Started | Aug 22 10:29:26 PM UTC 24 |
| Finished | Aug 22 10:30:55 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645782365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1645782365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/16.prim_present_test.4263791470 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7719000000 ps |
| CPU time | 15.51 seconds |
| Started | Aug 22 10:29:26 PM UTC 24 |
| Finished | Aug 22 10:30:22 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263791470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.4263791470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/17.prim_present_test.505995117 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3330020000 ps |
| CPU time | 7.45 seconds |
| Started | Aug 22 10:29:26 PM UTC 24 |
| Finished | Aug 22 10:29:51 PM UTC 24 |
| Peak memory | 151844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505995117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.505995117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/18.prim_present_test.3552481140 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10848760000 ps |
| CPU time | 23.98 seconds |
| Started | Aug 22 10:29:26 PM UTC 24 |
| Finished | Aug 22 10:30:44 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552481140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3552481140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/19.prim_present_test.1292962772 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7314140000 ps |
| CPU time | 14.96 seconds |
| Started | Aug 22 10:29:28 PM UTC 24 |
| Finished | Aug 22 10:30:21 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292962772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1292962772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/2.prim_present_test.3336899737 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11202160000 ps |
| CPU time | 22.6 seconds |
| Started | Aug 22 10:29:22 PM UTC 24 |
| Finished | Aug 22 10:30:42 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336899737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3336899737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/20.prim_present_test.4227308618 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10099180000 ps |
| CPU time | 19.9 seconds |
| Started | Aug 22 10:29:33 PM UTC 24 |
| Finished | Aug 22 10:30:46 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227308618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.4227308618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/21.prim_present_test.1159570383 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4540260000 ps |
| CPU time | 9.78 seconds |
| Started | Aug 22 10:29:34 PM UTC 24 |
| Finished | Aug 22 10:30:08 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159570383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1159570383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/22.prim_present_test.630952485 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6652600000 ps |
| CPU time | 14.03 seconds |
| Started | Aug 22 10:29:51 PM UTC 24 |
| Finished | Aug 22 10:30:40 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630952485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.630952485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/23.prim_present_test.3240017985 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3763400000 ps |
| CPU time | 8.39 seconds |
| Started | Aug 22 10:29:52 PM UTC 24 |
| Finished | Aug 22 10:30:20 PM UTC 24 |
| Peak memory | 151840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240017985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3240017985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/24.prim_present_test.94944750 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13930780000 ps |
| CPU time | 30.37 seconds |
| Started | Aug 22 10:30:01 PM UTC 24 |
| Finished | Aug 22 10:31:39 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94944750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 24.prim_present_test.94944750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/25.prim_present_test.4284199176 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11904620000 ps |
| CPU time | 25.07 seconds |
| Started | Aug 22 10:30:02 PM UTC 24 |
| Finished | Aug 22 10:31:28 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284199176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4284199176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/26.prim_present_test.3292656154 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5602320000 ps |
| CPU time | 12.42 seconds |
| Started | Aug 22 10:30:02 PM UTC 24 |
| Finished | Aug 22 10:30:43 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292656154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3292656154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/27.prim_present_test.5624254 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3809280000 ps |
| CPU time | 8.77 seconds |
| Started | Aug 22 10:30:08 PM UTC 24 |
| Finished | Aug 22 10:30:37 PM UTC 24 |
| Peak memory | 152096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5624254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 27.prim_present_test.5624254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/28.prim_present_test.1811421497 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7923600000 ps |
| CPU time | 17.35 seconds |
| Started | Aug 22 10:30:16 PM UTC 24 |
| Finished | Aug 22 10:31:14 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811421497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1811421497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/29.prim_present_test.3091587029 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9006740000 ps |
| CPU time | 17.94 seconds |
| Started | Aug 22 10:30:21 PM UTC 24 |
| Finished | Aug 22 10:31:26 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091587029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3091587029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/3.prim_present_test.1746265366 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9609380000 ps |
| CPU time | 20.34 seconds |
| Started | Aug 22 10:29:22 PM UTC 24 |
| Finished | Aug 22 10:30:31 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746265366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1746265366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/30.prim_present_test.4058590033 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9396100000 ps |
| CPU time | 18.42 seconds |
| Started | Aug 22 10:30:21 PM UTC 24 |
| Finished | Aug 22 10:31:29 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058590033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4058590033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/31.prim_present_test.3453695379 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12806100000 ps |
| CPU time | 25.05 seconds |
| Started | Aug 22 10:30:22 PM UTC 24 |
| Finished | Aug 22 10:31:52 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453695379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3453695379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/32.prim_present_test.2920109893 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12761460000 ps |
| CPU time | 24.68 seconds |
| Started | Aug 22 10:30:23 PM UTC 24 |
| Finished | Aug 22 10:31:52 PM UTC 24 |
| Peak memory | 152084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920109893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2920109893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/33.prim_present_test.534555080 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6978100000 ps |
| CPU time | 14.26 seconds |
| Started | Aug 22 10:30:23 PM UTC 24 |
| Finished | Aug 22 10:31:15 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534555080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.534555080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/34.prim_present_test.3663401152 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5232800000 ps |
| CPU time | 10.6 seconds |
| Started | Aug 22 10:30:29 PM UTC 24 |
| Finished | Aug 22 10:31:07 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663401152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3663401152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/35.prim_present_test.2205037149 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3568100000 ps |
| CPU time | 8.63 seconds |
| Started | Aug 22 10:30:31 PM UTC 24 |
| Finished | Aug 22 10:30:57 PM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205037149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2205037149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/36.prim_present_test.1246734140 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11686380000 ps |
| CPU time | 25.26 seconds |
| Started | Aug 22 10:30:32 PM UTC 24 |
| Finished | Aug 22 10:31:53 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246734140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1246734140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/37.prim_present_test.3071448333 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4928380000 ps |
| CPU time | 10.01 seconds |
| Started | Aug 22 10:30:38 PM UTC 24 |
| Finished | Aug 22 10:31:14 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071448333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3071448333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/38.prim_present_test.2177288932 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6272540000 ps |
| CPU time | 12.23 seconds |
| Started | Aug 22 10:30:41 PM UTC 24 |
| Finished | Aug 22 10:31:26 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177288932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2177288932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/39.prim_present_test.1253389747 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5356180000 ps |
| CPU time | 10.97 seconds |
| Started | Aug 22 10:30:43 PM UTC 24 |
| Finished | Aug 22 10:31:22 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253389747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1253389747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/4.prim_present_test.1397992123 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8425180000 ps |
| CPU time | 17.21 seconds |
| Started | Aug 22 10:29:22 PM UTC 24 |
| Finished | Aug 22 10:30:23 PM UTC 24 |
| Peak memory | 151940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397992123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1397992123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/40.prim_present_test.2893716022 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11756440000 ps |
| CPU time | 24.21 seconds |
| Started | Aug 22 10:30:44 PM UTC 24 |
| Finished | Aug 22 10:32:04 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893716022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2893716022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/41.prim_present_test.2552679889 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10660280000 ps |
| CPU time | 22.43 seconds |
| Started | Aug 22 10:30:44 PM UTC 24 |
| Finished | Aug 22 10:31:57 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552679889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2552679889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/42.prim_present_test.530881013 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13356040000 ps |
| CPU time | 27.51 seconds |
| Started | Aug 22 10:30:45 PM UTC 24 |
| Finished | Aug 22 10:32:15 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530881013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.530881013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/43.prim_present_test.1166558225 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14021920000 ps |
| CPU time | 28.3 seconds |
| Started | Aug 22 10:30:47 PM UTC 24 |
| Finished | Aug 22 10:32:20 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166558225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1166558225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/44.prim_present_test.1581221877 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14591080000 ps |
| CPU time | 27.71 seconds |
| Started | Aug 22 10:30:48 PM UTC 24 |
| Finished | Aug 22 10:32:25 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581221877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1581221877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/45.prim_present_test.2869726799 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12792460000 ps |
| CPU time | 24.45 seconds |
| Started | Aug 22 10:30:56 PM UTC 24 |
| Finished | Aug 22 10:32:21 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869726799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2869726799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/46.prim_present_test.4206151093 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13659220000 ps |
| CPU time | 25.53 seconds |
| Started | Aug 22 10:30:56 PM UTC 24 |
| Finished | Aug 22 10:32:26 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206151093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4206151093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/47.prim_present_test.354231900 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14234580000 ps |
| CPU time | 27.01 seconds |
| Started | Aug 22 10:30:58 PM UTC 24 |
| Finished | Aug 22 10:32:31 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354231900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.354231900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/48.prim_present_test.2195040969 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12098060000 ps |
| CPU time | 22.6 seconds |
| Started | Aug 22 10:31:03 PM UTC 24 |
| Finished | Aug 22 10:32:23 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195040969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2195040969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/49.prim_present_test.167613192 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14501800000 ps |
| CPU time | 27.2 seconds |
| Started | Aug 22 10:31:08 PM UTC 24 |
| Finished | Aug 22 10:32:41 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167613192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.167613192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/5.prim_present_test.3458154204 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7396600000 ps |
| CPU time | 14.77 seconds |
| Started | Aug 22 10:29:22 PM UTC 24 |
| Finished | Aug 22 10:30:15 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458154204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3458154204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/6.prim_present_test.1084302446 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14042380000 ps |
| CPU time | 27.72 seconds |
| Started | Aug 22 10:29:22 PM UTC 24 |
| Finished | Aug 22 10:31:03 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084302446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1084302446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/7.prim_present_test.3232079993 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3574920000 ps |
| CPU time | 7.47 seconds |
| Started | Aug 22 10:29:23 PM UTC 24 |
| Finished | Aug 22 10:29:50 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232079993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3232079993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/8.prim_present_test.2168255093 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14892400000 ps |
| CPU time | 28.88 seconds |
| Started | Aug 22 10:29:23 PM UTC 24 |
| Finished | Aug 22 10:31:10 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168255093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2168255093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default/9.prim_present_test.921584450 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11084980000 ps |
| CPU time | 22.42 seconds |
| Started | Aug 22 10:29:23 PM UTC 24 |
| Finished | Aug 22 10:30:43 PM UTC 24 |
| Peak memory | 151980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921584450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.921584450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_present-sim-vcs/9.prim_present_test/latest |
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