| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/12.prim_present_test.1193871571 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/0.prim_present_test.2200484393 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/1.prim_present_test.465050381 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/10.prim_present_test.2670667367 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/11.prim_present_test.211878056 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/13.prim_present_test.1717005058 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/14.prim_present_test.2543647230 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/15.prim_present_test.1818251012 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/16.prim_present_test.2103245743 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/17.prim_present_test.1625491718 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/18.prim_present_test.369787766 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/19.prim_present_test.2423283451 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/2.prim_present_test.2530829238 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/20.prim_present_test.3655725266 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/21.prim_present_test.309954451 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/22.prim_present_test.1267957273 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/23.prim_present_test.130664479 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/24.prim_present_test.2360664426 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/25.prim_present_test.4049673627 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/26.prim_present_test.2303158567 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/27.prim_present_test.987314053 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/28.prim_present_test.3159486878 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/29.prim_present_test.2113162686 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/3.prim_present_test.969541449 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/30.prim_present_test.4149170295 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/31.prim_present_test.301509452 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/32.prim_present_test.781515699 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/33.prim_present_test.2118103816 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/34.prim_present_test.3817613667 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/35.prim_present_test.770026286 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/36.prim_present_test.490642628 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/37.prim_present_test.2382826727 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/38.prim_present_test.1705224046 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/39.prim_present_test.272853434 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/4.prim_present_test.2791394291 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/40.prim_present_test.345032464 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/41.prim_present_test.4174306789 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/42.prim_present_test.3592474867 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/43.prim_present_test.3814442300 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/44.prim_present_test.1484023331 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/45.prim_present_test.1168643998 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/46.prim_present_test.3337194715 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/47.prim_present_test.3755981932 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/48.prim_present_test.3350293518 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/49.prim_present_test.2602653603 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/5.prim_present_test.387524944 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/6.prim_present_test.2369139899 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/7.prim_present_test.3403205285 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/8.prim_present_test.304414355 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/9.prim_present_test.3003058467 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/27.prim_present_test.987314053 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:21 PM UTC 24 | 3785720000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/30.prim_present_test.4149170295 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:30 PM UTC 24 | 3669780000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/29.prim_present_test.2113162686 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:34 PM UTC 24 | 5525440000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/33.prim_present_test.2118103816 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:34 PM UTC 24 | 3289720000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/22.prim_present_test.1267957273 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:35 PM UTC 24 | 5738100000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/39.prim_present_test.272853434 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:38 PM UTC 24 | 3754720000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/6.prim_present_test.2369139899 | Aug 24 09:46:50 PM UTC 24 | Aug 24 09:47:40 PM UTC 24 | 6672440000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/12.prim_present_test.1193871571 | Aug 24 09:46:51 PM UTC 24 | Aug 24 09:47:47 PM UTC 24 | 7378620000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/47.prim_present_test.3755981932 | Aug 24 09:46:53 PM UTC 24 | Aug 24 09:47:48 PM UTC 24 | 4966200000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/17.prim_present_test.1625491718 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:49 PM UTC 24 | 7562760000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/3.prim_present_test.969541449 | Aug 24 09:46:47 PM UTC 24 | Aug 24 09:47:51 PM UTC 24 | 8689300000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/43.prim_present_test.3814442300 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:53 PM UTC 24 | 5797620000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/10.prim_present_test.2670667367 | Aug 24 09:46:51 PM UTC 24 | Aug 24 09:47:54 PM UTC 24 | 8269560000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/37.prim_present_test.2382826727 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:54 PM UTC 24 | 5948280000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/14.prim_present_test.2543647230 | Aug 24 09:46:51 PM UTC 24 | Aug 24 09:47:55 PM UTC 24 | 8365660000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/9.prim_present_test.3003058467 | Aug 24 09:46:51 PM UTC 24 | Aug 24 09:47:55 PM UTC 24 | 8562820000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/4.prim_present_test.2791394291 | Aug 24 09:46:50 PM UTC 24 | Aug 24 09:47:57 PM UTC 24 | 9094160000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/25.prim_present_test.4049673627 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:47:58 PM UTC 24 | 8778580000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/8.prim_present_test.304414355 | Aug 24 09:46:50 PM UTC 24 | Aug 24 09:48:00 PM UTC 24 | 9298140000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/2.prim_present_test.2530829238 | Aug 24 09:46:47 PM UTC 24 | Aug 24 09:48:04 PM UTC 24 | 10566660000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/1.prim_present_test.465050381 | Aug 24 09:46:44 PM UTC 24 | Aug 24 09:48:05 PM UTC 24 | 11101720000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/5.prim_present_test.387524944 | Aug 24 09:46:50 PM UTC 24 | Aug 24 09:48:09 PM UTC 24 | 10557360000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/28.prim_present_test.3159486878 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:11 PM UTC 24 | 10195280000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/40.prim_present_test.345032464 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:12 PM UTC 24 | 8259640000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/0.prim_present_test.2200484393 | Aug 24 09:46:44 PM UTC 24 | Aug 24 09:48:13 PM UTC 24 | 12014360000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/13.prim_present_test.1717005058 | Aug 24 09:46:51 PM UTC 24 | Aug 24 09:48:19 PM UTC 24 | 11447060000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/23.prim_present_test.130664479 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:22 PM UTC 24 | 12081320000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/11.prim_present_test.211878056 | Aug 24 09:46:51 PM UTC 24 | Aug 24 09:48:24 PM UTC 24 | 12303280000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/7.prim_present_test.3403205285 | Aug 24 09:46:50 PM UTC 24 | Aug 24 09:48:24 PM UTC 24 | 12654200000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/19.prim_present_test.2423283451 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:28 PM UTC 24 | 12799280000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/48.prim_present_test.3350293518 | Aug 24 09:46:53 PM UTC 24 | Aug 24 09:48:32 PM UTC 24 | 11010580000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/16.prim_present_test.2103245743 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:33 PM UTC 24 | 13291560000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/32.prim_present_test.781515699 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:33 PM UTC 24 | 10931220000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/31.prim_present_test.301509452 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:33 PM UTC 24 | 11255480000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/36.prim_present_test.490642628 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:34 PM UTC 24 | 11186660000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/18.prim_present_test.369787766 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:35 PM UTC 24 | 13532740000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/41.prim_present_test.4174306789 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:35 PM UTC 24 | 11271600000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/21.prim_present_test.309954451 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:35 PM UTC 24 | 13609620000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/15.prim_present_test.1818251012 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:36 PM UTC 24 | 13810500000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/20.prim_present_test.3655725266 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:38 PM UTC 24 | 13927680000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/24.prim_present_test.2360664426 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:39 PM UTC 24 | 14242020000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/38.prim_present_test.1705224046 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:41 PM UTC 24 | 11957320000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/26.prim_present_test.2303158567 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:41 PM UTC 24 | 14566900000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/44.prim_present_test.1484023331 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:51 PM UTC 24 | 13308920000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/49.prim_present_test.2602653603 | Aug 24 09:46:53 PM UTC 24 | Aug 24 09:48:54 PM UTC 24 | 13723700000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/45.prim_present_test.1168643998 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:48:57 PM UTC 24 | 14168240000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/42.prim_present_test.3592474867 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:49:00 PM UTC 24 | 14690900000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/35.prim_present_test.770026286 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:49:01 PM UTC 24 | 14606580000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/46.prim_present_test.3337194715 | Aug 24 09:46:53 PM UTC 24 | Aug 24 09:49:02 PM UTC 24 | 14791340000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/34.prim_present_test.3817613667 | Aug 24 09:46:52 PM UTC 24 | Aug 24 09:49:02 PM UTC 24 | 14856440000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/12.prim_present_test.1193871571 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7378620000 ps |
| CPU time | 16.63 seconds |
| Started | Aug 24 09:46:51 PM UTC 24 |
| Finished | Aug 24 09:47:47 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193871571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1193871571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/0.prim_present_test.2200484393 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12014360000 ps |
| CPU time | 26.56 seconds |
| Started | Aug 24 09:46:44 PM UTC 24 |
| Finished | Aug 24 09:48:13 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200484393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2200484393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/1.prim_present_test.465050381 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11101720000 ps |
| CPU time | 24.28 seconds |
| Started | Aug 24 09:46:44 PM UTC 24 |
| Finished | Aug 24 09:48:05 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465050381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.465050381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/10.prim_present_test.2670667367 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 8269560000 ps |
| CPU time | 18.66 seconds |
| Started | Aug 24 09:46:51 PM UTC 24 |
| Finished | Aug 24 09:47:54 PM UTC 24 |
| Peak memory | 152100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670667367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2670667367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/11.prim_present_test.211878056 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12303280000 ps |
| CPU time | 28.01 seconds |
| Started | Aug 24 09:46:51 PM UTC 24 |
| Finished | Aug 24 09:48:24 PM UTC 24 |
| Peak memory | 152124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211878056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.211878056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/13.prim_present_test.1717005058 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11447060000 ps |
| CPU time | 26.2 seconds |
| Started | Aug 24 09:46:51 PM UTC 24 |
| Finished | Aug 24 09:48:19 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717005058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1717005058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/14.prim_present_test.2543647230 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8365660000 ps |
| CPU time | 19.2 seconds |
| Started | Aug 24 09:46:51 PM UTC 24 |
| Finished | Aug 24 09:47:55 PM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543647230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2543647230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/15.prim_present_test.1818251012 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13810500000 ps |
| CPU time | 31.69 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:36 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818251012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1818251012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/16.prim_present_test.2103245743 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13291560000 ps |
| CPU time | 30.24 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:33 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103245743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2103245743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/17.prim_present_test.1625491718 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7562760000 ps |
| CPU time | 16.98 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:49 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625491718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1625491718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/18.prim_present_test.369787766 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13532740000 ps |
| CPU time | 30.66 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:35 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369787766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.369787766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/19.prim_present_test.2423283451 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 12799280000 ps |
| CPU time | 29.18 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:28 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423283451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2423283451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/2.prim_present_test.2530829238 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10566660000 ps |
| CPU time | 23.42 seconds |
| Started | Aug 24 09:46:47 PM UTC 24 |
| Finished | Aug 24 09:48:04 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530829238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2530829238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/20.prim_present_test.3655725266 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13927680000 ps |
| CPU time | 32.09 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:38 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655725266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3655725266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/21.prim_present_test.309954451 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13609620000 ps |
| CPU time | 31.08 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:35 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309954451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.309954451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/22.prim_present_test.1267957273 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5738100000 ps |
| CPU time | 12.71 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:35 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267957273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1267957273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/23.prim_present_test.130664479 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12081320000 ps |
| CPU time | 27.42 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:22 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130664479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.130664479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/24.prim_present_test.2360664426 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14242020000 ps |
| CPU time | 32.34 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:39 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360664426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2360664426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/25.prim_present_test.4049673627 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8778580000 ps |
| CPU time | 19.97 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:58 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049673627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4049673627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/26.prim_present_test.2303158567 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14566900000 ps |
| CPU time | 33.31 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:41 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303158567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2303158567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/27.prim_present_test.987314053 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3785720000 ps |
| CPU time | 8.25 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:21 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987314053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.987314053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/28.prim_present_test.3159486878 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10195280000 ps |
| CPU time | 23.51 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:11 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159486878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3159486878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/29.prim_present_test.2113162686 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5525440000 ps |
| CPU time | 12.13 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:34 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113162686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2113162686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/3.prim_present_test.969541449 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8689300000 ps |
| CPU time | 19.51 seconds |
| Started | Aug 24 09:46:47 PM UTC 24 |
| Finished | Aug 24 09:47:51 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969541449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.969541449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/30.prim_present_test.4149170295 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3669780000 ps |
| CPU time | 8.59 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:30 PM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149170295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4149170295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/31.prim_present_test.301509452 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11255480000 ps |
| CPU time | 26.23 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:33 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301509452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.301509452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/32.prim_present_test.781515699 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10931220000 ps |
| CPU time | 25.63 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:33 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781515699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.781515699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/33.prim_present_test.2118103816 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3289720000 ps |
| CPU time | 7.82 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:34 PM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118103816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2118103816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/34.prim_present_test.3817613667 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14856440000 ps |
| CPU time | 34.84 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:49:02 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817613667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3817613667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/35.prim_present_test.770026286 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14606580000 ps |
| CPU time | 34.31 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:49:01 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770026286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.770026286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/36.prim_present_test.490642628 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11186660000 ps |
| CPU time | 26.14 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:34 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490642628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.490642628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/37.prim_present_test.2382826727 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5948280000 ps |
| CPU time | 14.01 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:54 PM UTC 24 |
| Peak memory | 152116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382826727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2382826727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/38.prim_present_test.1705224046 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11957320000 ps |
| CPU time | 28.05 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:41 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705224046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1705224046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/39.prim_present_test.272853434 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3754720000 ps |
| CPU time | 8.99 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:38 PM UTC 24 |
| Peak memory | 152092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272853434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.272853434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/4.prim_present_test.2791394291 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9094160000 ps |
| CPU time | 20.08 seconds |
| Started | Aug 24 09:46:50 PM UTC 24 |
| Finished | Aug 24 09:47:57 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791394291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2791394291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/40.prim_present_test.345032464 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8259640000 ps |
| CPU time | 19.45 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:12 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345032464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.345032464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/41.prim_present_test.4174306789 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11271600000 ps |
| CPU time | 26.49 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:35 PM UTC 24 |
| Peak memory | 152100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174306789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.4174306789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/42.prim_present_test.3592474867 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14690900000 ps |
| CPU time | 34.19 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:49:00 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592474867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3592474867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/43.prim_present_test.3814442300 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5797620000 ps |
| CPU time | 13.61 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:47:53 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814442300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3814442300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/44.prim_present_test.1484023331 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13308920000 ps |
| CPU time | 31.19 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:51 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484023331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1484023331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/45.prim_present_test.1168643998 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14168240000 ps |
| CPU time | 32.99 seconds |
| Started | Aug 24 09:46:52 PM UTC 24 |
| Finished | Aug 24 09:48:57 PM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168643998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1168643998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/46.prim_present_test.3337194715 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14791340000 ps |
| CPU time | 34.41 seconds |
| Started | Aug 24 09:46:53 PM UTC 24 |
| Finished | Aug 24 09:49:02 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337194715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3337194715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/47.prim_present_test.3755981932 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4966200000 ps |
| CPU time | 11.75 seconds |
| Started | Aug 24 09:46:53 PM UTC 24 |
| Finished | Aug 24 09:47:48 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755981932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3755981932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/48.prim_present_test.3350293518 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11010580000 ps |
| CPU time | 25.56 seconds |
| Started | Aug 24 09:46:53 PM UTC 24 |
| Finished | Aug 24 09:48:32 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350293518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3350293518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/49.prim_present_test.2602653603 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13723700000 ps |
| CPU time | 32.23 seconds |
| Started | Aug 24 09:46:53 PM UTC 24 |
| Finished | Aug 24 09:48:54 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602653603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2602653603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/5.prim_present_test.387524944 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10557360000 ps |
| CPU time | 23.94 seconds |
| Started | Aug 24 09:46:50 PM UTC 24 |
| Finished | Aug 24 09:48:09 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387524944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.387524944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/6.prim_present_test.2369139899 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6672440000 ps |
| CPU time | 14.91 seconds |
| Started | Aug 24 09:46:50 PM UTC 24 |
| Finished | Aug 24 09:47:40 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369139899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2369139899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/7.prim_present_test.3403205285 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 12654200000 ps |
| CPU time | 28.64 seconds |
| Started | Aug 24 09:46:50 PM UTC 24 |
| Finished | Aug 24 09:48:24 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403205285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3403205285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/8.prim_present_test.304414355 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9298140000 ps |
| CPU time | 21.08 seconds |
| Started | Aug 24 09:46:50 PM UTC 24 |
| Finished | Aug 24 09:48:00 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304414355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.304414355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default/9.prim_present_test.3003058467 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8562820000 ps |
| CPU time | 19.22 seconds |
| Started | Aug 24 09:46:51 PM UTC 24 |
| Finished | Aug 24 09:47:55 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003058467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3003058467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_present-sim-vcs/9.prim_present_test/latest |
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