| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/1.prim_present_test.4189892154 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/0.prim_present_test.519119482 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/10.prim_present_test.3742694740 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/11.prim_present_test.310664496 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/12.prim_present_test.473431682 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/13.prim_present_test.2742160472 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/14.prim_present_test.186627670 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/15.prim_present_test.2619622047 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/16.prim_present_test.2876345243 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/17.prim_present_test.3257926721 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/18.prim_present_test.1781774066 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/19.prim_present_test.3726038899 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/2.prim_present_test.1348295758 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/20.prim_present_test.2523814213 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/21.prim_present_test.810988077 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/22.prim_present_test.3037220128 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/23.prim_present_test.2751491357 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/24.prim_present_test.1066739538 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/25.prim_present_test.2709457444 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/26.prim_present_test.1330773685 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/27.prim_present_test.4079768955 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/28.prim_present_test.298098004 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/29.prim_present_test.1229360851 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/3.prim_present_test.2105963734 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/30.prim_present_test.1972243585 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/31.prim_present_test.157062925 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/32.prim_present_test.4081277565 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/33.prim_present_test.443805708 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/34.prim_present_test.2354092200 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/35.prim_present_test.1143745519 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/36.prim_present_test.3154668299 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/37.prim_present_test.1583475088 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/38.prim_present_test.2026374714 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/39.prim_present_test.2581228030 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/4.prim_present_test.555243673 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/40.prim_present_test.411520183 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/41.prim_present_test.3472672229 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/42.prim_present_test.3402979379 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/43.prim_present_test.1437115116 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/44.prim_present_test.3237923184 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/45.prim_present_test.2484607431 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/46.prim_present_test.1829389649 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/47.prim_present_test.1784238653 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/48.prim_present_test.2615004735 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/49.prim_present_test.1443690071 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/5.prim_present_test.2011414296 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/6.prim_present_test.1790018704 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/7.prim_present_test.45433337 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/8.prim_present_test.382664501 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/9.prim_present_test.2781006800 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/1.prim_present_test.4189892154 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:03:55 AM UTC 24 | 3639400000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/30.prim_present_test.1972243585 | Aug 27 12:03:29 AM UTC 24 | Aug 27 12:03:57 AM UTC 24 | 3107440000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/34.prim_present_test.2354092200 | Aug 27 12:03:30 AM UTC 24 | Aug 27 12:03:58 AM UTC 24 | 3158900000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/28.prim_present_test.298098004 | Aug 27 12:03:29 AM UTC 24 | Aug 27 12:04:04 AM UTC 24 | 4010160000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/35.prim_present_test.1143745519 | Aug 27 12:03:30 AM UTC 24 | Aug 27 12:04:09 AM UTC 24 | 4481980000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/23.prim_present_test.2751491357 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:10 AM UTC 24 | 5088340000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/41.prim_present_test.3472672229 | Aug 27 12:03:35 AM UTC 24 | Aug 27 12:04:11 AM UTC 24 | 4193680000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/16.prim_present_test.2876345243 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:14 AM UTC 24 | 5651300000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/11.prim_present_test.310664496 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:15 AM UTC 24 | 5769720000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/27.prim_present_test.4079768955 | Aug 27 12:03:29 AM UTC 24 | Aug 27 12:04:17 AM UTC 24 | 5642620000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/4.prim_present_test.555243673 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:18 AM UTC 24 | 6250840000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/6.prim_present_test.1790018704 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:19 AM UTC 24 | 6412040000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/22.prim_present_test.3037220128 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:22 AM UTC 24 | 6848520000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/9.prim_present_test.2781006800 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:24 AM UTC 24 | 7312280000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/26.prim_present_test.1330773685 | Aug 27 12:03:28 AM UTC 24 | Aug 27 12:04:25 AM UTC 24 | 7213080000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/0.prim_present_test.519119482 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:04:25 AM UTC 24 | 7830600000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/29.prim_present_test.1229360851 | Aug 27 12:03:29 AM UTC 24 | Aug 27 12:04:25 AM UTC 24 | 7105820000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/13.prim_present_test.2742160472 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:26 AM UTC 24 | 7647080000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/43.prim_present_test.1437115116 | Aug 27 12:03:57 AM UTC 24 | Aug 27 12:04:27 AM UTC 24 | 3977300000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/39.prim_present_test.2581228030 | Aug 27 12:03:30 AM UTC 24 | Aug 27 12:04:28 AM UTC 24 | 7405280000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/20.prim_present_test.2523814213 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:28 AM UTC 24 | 8020320000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/36.prim_present_test.3154668299 | Aug 27 12:03:30 AM UTC 24 | Aug 27 12:04:29 AM UTC 24 | 7577020000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/32.prim_present_test.4081277565 | Aug 27 12:03:29 AM UTC 24 | Aug 27 12:04:32 AM UTC 24 | 8262120000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/8.prim_present_test.382664501 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:33 AM UTC 24 | 8913120000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/5.prim_present_test.2011414296 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:36 AM UTC 24 | 9451280000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/15.prim_present_test.2619622047 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:37 AM UTC 24 | 9471740000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/47.prim_present_test.1784238653 | Aug 27 12:04:05 AM UTC 24 | Aug 27 12:04:38 AM UTC 24 | 5026340000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/14.prim_present_test.186627670 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:40 AM UTC 24 | 10085540000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/18.prim_present_test.1781774066 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:42 AM UTC 24 | 10327960000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/44.prim_present_test.3237923184 | Aug 27 12:03:58 AM UTC 24 | Aug 27 12:04:43 AM UTC 24 | 6647020000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/46.prim_present_test.1829389649 | Aug 27 12:04:02 AM UTC 24 | Aug 27 12:04:43 AM UTC 24 | 6166520000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/33.prim_present_test.443805708 | Aug 27 12:03:29 AM UTC 24 | Aug 27 12:04:43 AM UTC 24 | 10105380000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/2.prim_present_test.1348295758 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:04:44 AM UTC 24 | 11104820000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/40.prim_present_test.411520183 | Aug 27 12:03:35 AM UTC 24 | Aug 27 12:04:46 AM UTC 24 | 9983860000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/37.prim_present_test.1583475088 | Aug 27 12:03:30 AM UTC 24 | Aug 27 12:04:49 AM UTC 24 | 10964080000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/3.prim_present_test.2105963734 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:52 AM UTC 24 | 12089380000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/17.prim_present_test.3257926721 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:54 AM UTC 24 | 12415500000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/19.prim_present_test.3726038899 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:04:55 AM UTC 24 | 12580420000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/49.prim_present_test.1443690071 | Aug 27 12:04:11 AM UTC 24 | Aug 27 12:04:58 AM UTC 24 | 7752480000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/10.prim_present_test.3742694740 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:05:00 AM UTC 24 | 13572420000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/7.prim_present_test.45433337 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:05:01 AM UTC 24 | 13684020000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/48.prim_present_test.2615004735 | Aug 27 12:04:10 AM UTC 24 | Aug 27 12:05:01 AM UTC 24 | 8260880000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/25.prim_present_test.2709457444 | Aug 27 12:03:27 AM UTC 24 | Aug 27 12:05:01 AM UTC 24 | 13551960000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/38.prim_present_test.2026374714 | Aug 27 12:03:30 AM UTC 24 | Aug 27 12:05:02 AM UTC 24 | 13177480000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/21.prim_present_test.810988077 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:05:07 AM UTC 24 | 14541480000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/24.prim_present_test.1066739538 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:05:08 AM UTC 24 | 14770880000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/12.prim_present_test.473431682 | Aug 27 12:03:26 AM UTC 24 | Aug 27 12:05:10 AM UTC 24 | 15184420000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/31.prim_present_test.157062925 | Aug 27 12:03:29 AM UTC 24 | Aug 27 12:05:12 AM UTC 24 | 15089560000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/45.prim_present_test.2484607431 | Aug 27 12:03:59 AM UTC 24 | Aug 27 12:05:16 AM UTC 24 | 12223300000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/42.prim_present_test.3402979379 | Aug 27 12:03:56 AM UTC 24 | Aug 27 12:05:17 AM UTC 24 | 12806100000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/1.prim_present_test.4189892154 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3639400000 ps |
| CPU time | 8.62 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:03:55 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189892154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4189892154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/0.prim_present_test.519119482 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7830600000 ps |
| CPU time | 18.12 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:04:25 AM UTC 24 |
| Peak memory | 152168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519119482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.519119482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/10.prim_present_test.3742694740 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13572420000 ps |
| CPU time | 30.73 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:05:00 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742694740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3742694740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/11.prim_present_test.310664496 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5769720000 ps |
| CPU time | 13.57 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:15 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310664496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.310664496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/12.prim_present_test.473431682 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 15184420000 ps |
| CPU time | 34.36 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:05:10 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473431682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.473431682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/13.prim_present_test.2742160472 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7647080000 ps |
| CPU time | 17.86 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:26 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742160472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2742160472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/14.prim_present_test.186627670 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10085540000 ps |
| CPU time | 23 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:40 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186627670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.186627670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/15.prim_present_test.2619622047 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9471740000 ps |
| CPU time | 22.12 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:37 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619622047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2619622047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/16.prim_present_test.2876345243 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5651300000 ps |
| CPU time | 13.4 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:14 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876345243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2876345243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/17.prim_present_test.3257926721 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12415500000 ps |
| CPU time | 28.21 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:54 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257926721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3257926721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/18.prim_present_test.1781774066 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10327960000 ps |
| CPU time | 23.62 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:42 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781774066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1781774066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/19.prim_present_test.3726038899 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12580420000 ps |
| CPU time | 28.88 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:55 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726038899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3726038899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/2.prim_present_test.1348295758 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11104820000 ps |
| CPU time | 25.34 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:04:44 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348295758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1348295758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/20.prim_present_test.2523814213 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8020320000 ps |
| CPU time | 18.71 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:28 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523814213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2523814213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/21.prim_present_test.810988077 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14541480000 ps |
| CPU time | 33.05 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:05:07 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810988077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.810988077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/22.prim_present_test.3037220128 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6848520000 ps |
| CPU time | 15.95 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:22 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037220128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3037220128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/23.prim_present_test.2751491357 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5088340000 ps |
| CPU time | 11.96 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:10 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751491357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2751491357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/24.prim_present_test.1066739538 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14770880000 ps |
| CPU time | 33.56 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:05:08 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066739538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1066739538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/25.prim_present_test.2709457444 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13551960000 ps |
| CPU time | 31.16 seconds |
| Started | Aug 27 12:03:27 AM UTC 24 |
| Finished | Aug 27 12:05:01 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709457444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2709457444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/26.prim_present_test.1330773685 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7213080000 ps |
| CPU time | 17.16 seconds |
| Started | Aug 27 12:03:28 AM UTC 24 |
| Finished | Aug 27 12:04:25 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330773685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1330773685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/27.prim_present_test.4079768955 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5642620000 ps |
| CPU time | 13.28 seconds |
| Started | Aug 27 12:03:29 AM UTC 24 |
| Finished | Aug 27 12:04:17 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079768955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.4079768955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/28.prim_present_test.298098004 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4010160000 ps |
| CPU time | 9.95 seconds |
| Started | Aug 27 12:03:29 AM UTC 24 |
| Finished | Aug 27 12:04:04 AM UTC 24 |
| Peak memory | 152084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298098004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.298098004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/29.prim_present_test.1229360851 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7105820000 ps |
| CPU time | 16.67 seconds |
| Started | Aug 27 12:03:29 AM UTC 24 |
| Finished | Aug 27 12:04:25 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229360851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1229360851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/3.prim_present_test.2105963734 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 12089380000 ps |
| CPU time | 27.94 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:52 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105963734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2105963734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/30.prim_present_test.1972243585 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3107440000 ps |
| CPU time | 7.67 seconds |
| Started | Aug 27 12:03:29 AM UTC 24 |
| Finished | Aug 27 12:03:57 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972243585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1972243585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/31.prim_present_test.157062925 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 15089560000 ps |
| CPU time | 34.14 seconds |
| Started | Aug 27 12:03:29 AM UTC 24 |
| Finished | Aug 27 12:05:12 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157062925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.157062925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/32.prim_present_test.4081277565 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8262120000 ps |
| CPU time | 18.99 seconds |
| Started | Aug 27 12:03:29 AM UTC 24 |
| Finished | Aug 27 12:04:32 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081277565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4081277565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/33.prim_present_test.443805708 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10105380000 ps |
| CPU time | 23.05 seconds |
| Started | Aug 27 12:03:29 AM UTC 24 |
| Finished | Aug 27 12:04:43 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443805708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.443805708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/34.prim_present_test.2354092200 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3158900000 ps |
| CPU time | 7.88 seconds |
| Started | Aug 27 12:03:30 AM UTC 24 |
| Finished | Aug 27 12:03:58 AM UTC 24 |
| Peak memory | 152004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354092200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2354092200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/35.prim_present_test.1143745519 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4481980000 ps |
| CPU time | 10.89 seconds |
| Started | Aug 27 12:03:30 AM UTC 24 |
| Finished | Aug 27 12:04:09 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143745519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1143745519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/36.prim_present_test.3154668299 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7577020000 ps |
| CPU time | 17.74 seconds |
| Started | Aug 27 12:03:30 AM UTC 24 |
| Finished | Aug 27 12:04:29 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154668299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3154668299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/37.prim_present_test.1583475088 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10964080000 ps |
| CPU time | 25.02 seconds |
| Started | Aug 27 12:03:30 AM UTC 24 |
| Finished | Aug 27 12:04:49 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583475088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1583475088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/38.prim_present_test.2026374714 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13177480000 ps |
| CPU time | 30.26 seconds |
| Started | Aug 27 12:03:30 AM UTC 24 |
| Finished | Aug 27 12:05:02 AM UTC 24 |
| Peak memory | 152104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026374714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2026374714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/39.prim_present_test.2581228030 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7405280000 ps |
| CPU time | 17.36 seconds |
| Started | Aug 27 12:03:30 AM UTC 24 |
| Finished | Aug 27 12:04:28 AM UTC 24 |
| Peak memory | 152128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581228030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2581228030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/4.prim_present_test.555243673 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6250840000 ps |
| CPU time | 14.89 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:18 AM UTC 24 |
| Peak memory | 152168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555243673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.555243673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/40.prim_present_test.411520183 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9983860000 ps |
| CPU time | 23.14 seconds |
| Started | Aug 27 12:03:35 AM UTC 24 |
| Finished | Aug 27 12:04:46 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411520183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.411520183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/41.prim_present_test.3472672229 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4193680000 ps |
| CPU time | 10.09 seconds |
| Started | Aug 27 12:03:35 AM UTC 24 |
| Finished | Aug 27 12:04:11 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472672229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3472672229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/42.prim_present_test.3402979379 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12806100000 ps |
| CPU time | 29.17 seconds |
| Started | Aug 27 12:03:56 AM UTC 24 |
| Finished | Aug 27 12:05:17 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402979379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3402979379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/43.prim_present_test.1437115116 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3977300000 ps |
| CPU time | 9.53 seconds |
| Started | Aug 27 12:03:57 AM UTC 24 |
| Finished | Aug 27 12:04:27 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437115116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1437115116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/44.prim_present_test.3237923184 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6647020000 ps |
| CPU time | 15.25 seconds |
| Started | Aug 27 12:03:58 AM UTC 24 |
| Finished | Aug 27 12:04:43 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237923184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3237923184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/45.prim_present_test.2484607431 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12223300000 ps |
| CPU time | 27.8 seconds |
| Started | Aug 27 12:03:59 AM UTC 24 |
| Finished | Aug 27 12:05:16 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484607431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2484607431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/46.prim_present_test.1829389649 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6166520000 ps |
| CPU time | 14.33 seconds |
| Started | Aug 27 12:04:02 AM UTC 24 |
| Finished | Aug 27 12:04:43 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829389649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1829389649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/47.prim_present_test.1784238653 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5026340000 ps |
| CPU time | 11.6 seconds |
| Started | Aug 27 12:04:05 AM UTC 24 |
| Finished | Aug 27 12:04:38 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784238653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1784238653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/48.prim_present_test.2615004735 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8260880000 ps |
| CPU time | 18.98 seconds |
| Started | Aug 27 12:04:10 AM UTC 24 |
| Finished | Aug 27 12:05:01 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615004735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2615004735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/49.prim_present_test.1443690071 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7752480000 ps |
| CPU time | 17.75 seconds |
| Started | Aug 27 12:04:11 AM UTC 24 |
| Finished | Aug 27 12:04:58 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443690071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1443690071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/5.prim_present_test.2011414296 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9451280000 ps |
| CPU time | 21.6 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:36 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011414296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2011414296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/6.prim_present_test.1790018704 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6412040000 ps |
| CPU time | 14.87 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:19 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790018704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1790018704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/7.prim_present_test.45433337 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13684020000 ps |
| CPU time | 31.05 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:05:01 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45433337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 7.prim_present_test.45433337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/8.prim_present_test.382664501 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8913120000 ps |
| CPU time | 20.79 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:33 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382664501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.382664501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default/9.prim_present_test.2781006800 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7312280000 ps |
| CPU time | 16.93 seconds |
| Started | Aug 27 12:03:26 AM UTC 24 |
| Finished | Aug 27 12:04:24 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781006800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2781006800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_present-sim-vcs/9.prim_present_test/latest |
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