| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/0.prim_present_test.3076103249 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/1.prim_present_test.335927973 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/10.prim_present_test.1064327832 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/11.prim_present_test.1407902040 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/12.prim_present_test.2937890603 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/13.prim_present_test.3702871962 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/14.prim_present_test.2779389779 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/15.prim_present_test.1927408210 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/16.prim_present_test.1598542089 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/17.prim_present_test.334933554 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/18.prim_present_test.2810479355 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/19.prim_present_test.3149405023 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/2.prim_present_test.3491903834 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/20.prim_present_test.2275142618 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/21.prim_present_test.1864249440 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/22.prim_present_test.3186017945 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/23.prim_present_test.667270236 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/24.prim_present_test.3642857364 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/25.prim_present_test.3912130451 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/26.prim_present_test.2427984345 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/27.prim_present_test.2626469429 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/28.prim_present_test.3217236340 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/29.prim_present_test.3715826077 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/3.prim_present_test.2987034797 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/30.prim_present_test.2470109881 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/31.prim_present_test.3538572387 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/32.prim_present_test.4169050126 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/33.prim_present_test.1150265739 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/34.prim_present_test.2798056841 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/35.prim_present_test.1810975531 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/36.prim_present_test.2178492549 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/37.prim_present_test.972990089 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/38.prim_present_test.4246799505 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/39.prim_present_test.1809465265 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/4.prim_present_test.1492424889 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/40.prim_present_test.2063457097 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/41.prim_present_test.2744963902 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/42.prim_present_test.3769413503 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/43.prim_present_test.2444555660 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/44.prim_present_test.973529101 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/45.prim_present_test.830398459 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/46.prim_present_test.3346324960 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/47.prim_present_test.1869890553 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/48.prim_present_test.2592049244 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/49.prim_present_test.34812080 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/5.prim_present_test.663786755 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/6.prim_present_test.2872574410 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/7.prim_present_test.4075053266 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/8.prim_present_test.2990690151 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/9.prim_present_test.3541248236 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/2.prim_present_test.3491903834 | Aug 28 05:14:39 PM UTC 24 | Aug 28 05:15:09 PM UTC 24 | 4317060000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/7.prim_present_test.4075053266 | Aug 28 05:14:40 PM UTC 24 | Aug 28 05:15:10 PM UTC 24 | 4267460000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/4.prim_present_test.1492424889 | Aug 28 05:14:40 PM UTC 24 | Aug 28 05:15:11 PM UTC 24 | 4447260000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/1.prim_present_test.335927973 | Aug 28 05:14:39 PM UTC 24 | Aug 28 05:15:17 PM UTC 24 | 5595500000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/14.prim_present_test.2779389779 | Aug 28 05:14:57 PM UTC 24 | Aug 28 05:15:23 PM UTC 24 | 3908480000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/49.prim_present_test.34812080 | Aug 28 05:15:01 PM UTC 24 | Aug 28 05:15:28 PM UTC 24 | 4108740000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/26.prim_present_test.2427984345 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:15:31 PM UTC 24 | 4791980000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/0.prim_present_test.3076103249 | Aug 28 05:14:39 PM UTC 24 | Aug 28 05:15:34 PM UTC 24 | 8299320000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/5.prim_present_test.663786755 | Aug 28 05:14:40 PM UTC 24 | Aug 28 05:15:34 PM UTC 24 | 8184620000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/12.prim_present_test.2937890603 | Aug 28 05:14:57 PM UTC 24 | Aug 28 05:15:34 PM UTC 24 | 5642000000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/40.prim_present_test.2063457097 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:15:35 PM UTC 24 | 5239000000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/16.prim_present_test.1598542089 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:15:35 PM UTC 24 | 5668660000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/35.prim_present_test.1810975531 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:15:37 PM UTC 24 | 5764140000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/27.prim_present_test.2626469429 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:15:38 PM UTC 24 | 6029500000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/3.prim_present_test.2987034797 | Aug 28 05:14:40 PM UTC 24 | Aug 28 05:15:39 PM UTC 24 | 8961480000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/47.prim_present_test.1869890553 | Aug 28 05:15:01 PM UTC 24 | Aug 28 05:15:40 PM UTC 24 | 5962540000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/41.prim_present_test.2744963902 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:15:41 PM UTC 24 | 6274400000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/8.prim_present_test.2990690151 | Aug 28 05:14:45 PM UTC 24 | Aug 28 05:15:43 PM UTC 24 | 8817640000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/25.prim_present_test.3912130451 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:15:48 PM UTC 24 | 7626620000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/32.prim_present_test.4169050126 | Aug 28 05:14:59 PM UTC 24 | Aug 28 05:15:50 PM UTC 24 | 7719620000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/13.prim_present_test.3702871962 | Aug 28 05:14:57 PM UTC 24 | Aug 28 05:15:50 PM UTC 24 | 8228640000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/45.prim_present_test.830398459 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:15:55 PM UTC 24 | 8567780000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/33.prim_present_test.1150265739 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:15:57 PM UTC 24 | 8900100000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/44.prim_present_test.973529101 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:15:58 PM UTC 24 | 8932960000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/38.prim_present_test.4246799505 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:15:59 PM UTC 24 | 9216920000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/9.prim_present_test.3541248236 | Aug 28 05:14:47 PM UTC 24 | Aug 28 05:16:00 PM UTC 24 | 11241840000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/31.prim_present_test.3538572387 | Aug 28 05:14:59 PM UTC 24 | Aug 28 05:16:03 PM UTC 24 | 9802200000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/6.prim_present_test.2872574410 | Aug 28 05:14:40 PM UTC 24 | Aug 28 05:16:03 PM UTC 24 | 12743480000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/10.prim_present_test.1064327832 | Aug 28 05:14:47 PM UTC 24 | Aug 28 05:16:05 PM UTC 24 | 11987080000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/42.prim_present_test.3769413503 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:16:08 PM UTC 24 | 10682600000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/39.prim_present_test.1809465265 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:16:11 PM UTC 24 | 11107300000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/34.prim_present_test.2798056841 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:16:12 PM UTC 24 | 11381340000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/17.prim_present_test.334933554 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:16:13 PM UTC 24 | 11686380000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/37.prim_present_test.972990089 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:16:13 PM UTC 24 | 11506580000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/15.prim_present_test.1927408210 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:16:16 PM UTC 24 | 12188580000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/48.prim_present_test.2592049244 | Aug 28 05:15:01 PM UTC 24 | Aug 28 05:16:17 PM UTC 24 | 11877340000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/36.prim_present_test.2178492549 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:16:17 PM UTC 24 | 12221440000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/23.prim_present_test.667270236 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:16:19 PM UTC 24 | 12646760000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/43.prim_present_test.2444555660 | Aug 28 05:15:00 PM UTC 24 | Aug 28 05:16:19 PM UTC 24 | 12567400000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/11.prim_present_test.1407902040 | Aug 28 05:14:54 PM UTC 24 | Aug 28 05:16:19 PM UTC 24 | 13389520000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/19.prim_present_test.3149405023 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:16:20 PM UTC 24 | 12775100000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/20.prim_present_test.2275142618 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:16:20 PM UTC 24 | 12910880000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/22.prim_present_test.3186017945 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:16:21 PM UTC 24 | 12874920000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/21.prim_present_test.1864249440 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:16:22 PM UTC 24 | 13278540000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/29.prim_present_test.3715826077 | Aug 28 05:14:59 PM UTC 24 | Aug 28 05:16:30 PM UTC 24 | 14297200000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/18.prim_present_test.2810479355 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:16:30 PM UTC 24 | 14434840000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/30.prim_present_test.2470109881 | Aug 28 05:14:59 PM UTC 24 | Aug 28 05:16:31 PM UTC 24 | 14543960000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/28.prim_present_test.3217236340 | Aug 28 05:14:59 PM UTC 24 | Aug 28 05:16:32 PM UTC 24 | 14666100000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/24.prim_present_test.3642857364 | Aug 28 05:14:58 PM UTC 24 | Aug 28 05:16:34 PM UTC 24 | 15256960000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/46.prim_present_test.3346324960 | Aug 28 05:15:01 PM UTC 24 | Aug 28 05:16:36 PM UTC 24 | 15035620000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/0.prim_present_test.3076103249 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8299320000 ps |
| CPU time | 17.3 seconds |
| Started | Aug 28 05:14:39 PM UTC 24 |
| Finished | Aug 28 05:15:34 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076103249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3076103249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/1.prim_present_test.335927973 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5595500000 ps |
| CPU time | 11.47 seconds |
| Started | Aug 28 05:14:39 PM UTC 24 |
| Finished | Aug 28 05:15:17 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335927973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.335927973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/10.prim_present_test.1064327832 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11987080000 ps |
| CPU time | 26.42 seconds |
| Started | Aug 28 05:14:47 PM UTC 24 |
| Finished | Aug 28 05:16:05 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064327832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1064327832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/11.prim_present_test.1407902040 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13389520000 ps |
| CPU time | 29.81 seconds |
| Started | Aug 28 05:14:54 PM UTC 24 |
| Finished | Aug 28 05:16:19 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407902040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1407902040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/12.prim_present_test.2937890603 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5642000000 ps |
| CPU time | 12.87 seconds |
| Started | Aug 28 05:14:57 PM UTC 24 |
| Finished | Aug 28 05:15:34 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937890603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2937890603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/13.prim_present_test.3702871962 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8228640000 ps |
| CPU time | 18.65 seconds |
| Started | Aug 28 05:14:57 PM UTC 24 |
| Finished | Aug 28 05:15:50 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702871962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3702871962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/14.prim_present_test.2779389779 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3908480000 ps |
| CPU time | 8.89 seconds |
| Started | Aug 28 05:14:57 PM UTC 24 |
| Finished | Aug 28 05:15:23 PM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779389779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2779389779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/15.prim_present_test.1927408210 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12188580000 ps |
| CPU time | 27.41 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:16:16 PM UTC 24 |
| Peak memory | 152128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927408210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1927408210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/16.prim_present_test.1598542089 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5668660000 ps |
| CPU time | 12.77 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:15:35 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598542089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1598542089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/17.prim_present_test.334933554 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11686380000 ps |
| CPU time | 26.2 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:16:13 PM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334933554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.334933554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/18.prim_present_test.2810479355 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14434840000 ps |
| CPU time | 32.45 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:16:30 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810479355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2810479355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/19.prim_present_test.3149405023 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12775100000 ps |
| CPU time | 28.6 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:16:20 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149405023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3149405023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/2.prim_present_test.3491903834 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4317060000 ps |
| CPU time | 8.48 seconds |
| Started | Aug 28 05:14:39 PM UTC 24 |
| Finished | Aug 28 05:15:09 PM UTC 24 |
| Peak memory | 152216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491903834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3491903834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/20.prim_present_test.2275142618 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12910880000 ps |
| CPU time | 28.71 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:16:20 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275142618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2275142618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/21.prim_present_test.1864249440 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13278540000 ps |
| CPU time | 29.41 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:16:22 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864249440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1864249440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/22.prim_present_test.3186017945 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12874920000 ps |
| CPU time | 28.84 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:16:21 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186017945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3186017945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/23.prim_present_test.667270236 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12646760000 ps |
| CPU time | 28.24 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:16:19 PM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667270236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.667270236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/24.prim_present_test.3642857364 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15256960000 ps |
| CPU time | 33.69 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:16:34 PM UTC 24 |
| Peak memory | 152004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642857364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3642857364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/25.prim_present_test.3912130451 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7626620000 ps |
| CPU time | 17.09 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:15:48 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912130451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3912130451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/26.prim_present_test.2427984345 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4791980000 ps |
| CPU time | 11.13 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:15:31 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427984345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2427984345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/27.prim_present_test.2626469429 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6029500000 ps |
| CPU time | 13.58 seconds |
| Started | Aug 28 05:14:58 PM UTC 24 |
| Finished | Aug 28 05:15:38 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626469429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2626469429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/28.prim_present_test.3217236340 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14666100000 ps |
| CPU time | 32.62 seconds |
| Started | Aug 28 05:14:59 PM UTC 24 |
| Finished | Aug 28 05:16:32 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217236340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3217236340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/29.prim_present_test.3715826077 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14297200000 ps |
| CPU time | 31.63 seconds |
| Started | Aug 28 05:14:59 PM UTC 24 |
| Finished | Aug 28 05:16:30 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715826077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3715826077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/3.prim_present_test.2987034797 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8961480000 ps |
| CPU time | 18.75 seconds |
| Started | Aug 28 05:14:40 PM UTC 24 |
| Finished | Aug 28 05:15:39 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987034797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2987034797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/30.prim_present_test.2470109881 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14543960000 ps |
| CPU time | 32.26 seconds |
| Started | Aug 28 05:14:59 PM UTC 24 |
| Finished | Aug 28 05:16:31 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470109881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2470109881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/31.prim_present_test.3538572387 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9802200000 ps |
| CPU time | 22.12 seconds |
| Started | Aug 28 05:14:59 PM UTC 24 |
| Finished | Aug 28 05:16:03 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538572387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3538572387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/32.prim_present_test.4169050126 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7719620000 ps |
| CPU time | 17.57 seconds |
| Started | Aug 28 05:14:59 PM UTC 24 |
| Finished | Aug 28 05:15:50 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169050126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4169050126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/33.prim_present_test.1150265739 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8900100000 ps |
| CPU time | 19.87 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:15:57 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150265739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1150265739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/34.prim_present_test.2798056841 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 11381340000 ps |
| CPU time | 25.38 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:16:12 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798056841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2798056841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/35.prim_present_test.1810975531 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5764140000 ps |
| CPU time | 13.04 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:15:37 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810975531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1810975531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/36.prim_present_test.2178492549 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12221440000 ps |
| CPU time | 27.23 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:16:17 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178492549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2178492549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/37.prim_present_test.972990089 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11506580000 ps |
| CPU time | 26.03 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:16:13 PM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972990089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.972990089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/38.prim_present_test.4246799505 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9216920000 ps |
| CPU time | 20.66 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:15:59 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246799505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.4246799505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/39.prim_present_test.1809465265 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11107300000 ps |
| CPU time | 25.07 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:16:11 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809465265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1809465265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/4.prim_present_test.1492424889 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4447260000 ps |
| CPU time | 9.02 seconds |
| Started | Aug 28 05:14:40 PM UTC 24 |
| Finished | Aug 28 05:15:11 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492424889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1492424889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/40.prim_present_test.2063457097 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5239000000 ps |
| CPU time | 11.97 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:15:35 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063457097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2063457097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/41.prim_present_test.2744963902 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6274400000 ps |
| CPU time | 14.42 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:15:41 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744963902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2744963902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/42.prim_present_test.3769413503 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10682600000 ps |
| CPU time | 24.05 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:16:08 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769413503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3769413503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/43.prim_present_test.2444555660 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12567400000 ps |
| CPU time | 27.83 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:16:19 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444555660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2444555660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/44.prim_present_test.973529101 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8932960000 ps |
| CPU time | 20.29 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:15:58 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973529101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.973529101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/45.prim_present_test.830398459 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8567780000 ps |
| CPU time | 19.35 seconds |
| Started | Aug 28 05:15:00 PM UTC 24 |
| Finished | Aug 28 05:15:55 PM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830398459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.830398459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/46.prim_present_test.3346324960 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15035620000 ps |
| CPU time | 33.72 seconds |
| Started | Aug 28 05:15:01 PM UTC 24 |
| Finished | Aug 28 05:16:36 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346324960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3346324960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/47.prim_present_test.1869890553 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5962540000 ps |
| CPU time | 13.5 seconds |
| Started | Aug 28 05:15:01 PM UTC 24 |
| Finished | Aug 28 05:15:40 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869890553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1869890553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/48.prim_present_test.2592049244 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11877340000 ps |
| CPU time | 26.77 seconds |
| Started | Aug 28 05:15:01 PM UTC 24 |
| Finished | Aug 28 05:16:17 PM UTC 24 |
| Peak memory | 152100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592049244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2592049244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/49.prim_present_test.34812080 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4108740000 ps |
| CPU time | 9.64 seconds |
| Started | Aug 28 05:15:01 PM UTC 24 |
| Finished | Aug 28 05:15:28 PM UTC 24 |
| Peak memory | 152092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34812080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 49.prim_present_test.34812080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/5.prim_present_test.663786755 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8184620000 ps |
| CPU time | 17.17 seconds |
| Started | Aug 28 05:14:40 PM UTC 24 |
| Finished | Aug 28 05:15:34 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663786755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.663786755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/6.prim_present_test.2872574410 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12743480000 ps |
| CPU time | 27.45 seconds |
| Started | Aug 28 05:14:40 PM UTC 24 |
| Finished | Aug 28 05:16:03 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872574410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2872574410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/7.prim_present_test.4075053266 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4267460000 ps |
| CPU time | 8.61 seconds |
| Started | Aug 28 05:14:40 PM UTC 24 |
| Finished | Aug 28 05:15:10 PM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075053266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.4075053266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/8.prim_present_test.2990690151 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8817640000 ps |
| CPU time | 19.05 seconds |
| Started | Aug 28 05:14:45 PM UTC 24 |
| Finished | Aug 28 05:15:43 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990690151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2990690151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default/9.prim_present_test.3541248236 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11241840000 ps |
| CPU time | 24.61 seconds |
| Started | Aug 28 05:14:47 PM UTC 24 |
| Finished | Aug 28 05:16:00 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541248236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3541248236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |