| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/1.prim_present_test.342816197 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/0.prim_present_test.879508444 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/10.prim_present_test.4084325240 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/11.prim_present_test.965378752 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/12.prim_present_test.3174688017 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/13.prim_present_test.3045991441 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/14.prim_present_test.2920337130 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/15.prim_present_test.2114599675 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/16.prim_present_test.3861921240 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/17.prim_present_test.1978706806 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/18.prim_present_test.1069978890 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/19.prim_present_test.2433136144 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/2.prim_present_test.2138780708 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/20.prim_present_test.1531582064 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/21.prim_present_test.374610844 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/22.prim_present_test.3982886995 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/23.prim_present_test.2770233459 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/24.prim_present_test.1857763595 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/25.prim_present_test.3243131839 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/26.prim_present_test.2660771994 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/27.prim_present_test.2939759044 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/28.prim_present_test.2394048176 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/29.prim_present_test.1337046398 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/3.prim_present_test.482661281 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/30.prim_present_test.3188000870 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/31.prim_present_test.2229385753 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/32.prim_present_test.789132566 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/33.prim_present_test.516401215 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/34.prim_present_test.3522289438 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/35.prim_present_test.1491413930 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/36.prim_present_test.153272871 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/37.prim_present_test.2992237380 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/38.prim_present_test.400879051 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/39.prim_present_test.610440331 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/4.prim_present_test.53572345 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/40.prim_present_test.1232216336 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/41.prim_present_test.2279883086 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/42.prim_present_test.3588186504 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/43.prim_present_test.939288892 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/44.prim_present_test.246183419 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/45.prim_present_test.352015925 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/46.prim_present_test.3836518811 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/47.prim_present_test.3169845960 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/48.prim_present_test.1643241697 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/49.prim_present_test.2940749575 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/5.prim_present_test.2772465760 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/6.prim_present_test.2886239290 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/7.prim_present_test.1082237894 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/8.prim_present_test.2178709015 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/9.prim_present_test.2416210693 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/6.prim_present_test.2886239290 | Sep 01 04:25:41 AM UTC 24 | Sep 01 04:26:06 AM UTC 24 | 3657380000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/7.prim_present_test.1082237894 | Sep 01 04:25:42 AM UTC 24 | Sep 01 04:26:29 AM UTC 24 | 6369880000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/3.prim_present_test.482661281 | Sep 01 04:25:40 AM UTC 24 | Sep 01 04:26:40 AM UTC 24 | 8433240000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/27.prim_present_test.2939759044 | Sep 01 04:26:11 AM UTC 24 | Sep 01 04:26:40 AM UTC 24 | 3722480000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/11.prim_present_test.965378752 | Sep 01 04:25:57 AM UTC 24 | Sep 01 04:26:41 AM UTC 24 | 5832960000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/35.prim_present_test.1491413930 | Sep 01 04:26:14 AM UTC 24 | Sep 01 04:26:41 AM UTC 24 | 3421160000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/24.prim_present_test.1857763595 | Sep 01 04:26:10 AM UTC 24 | Sep 01 04:26:41 AM UTC 24 | 4006440000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/1.prim_present_test.342816197 | Sep 01 04:25:40 AM UTC 24 | Sep 01 04:26:42 AM UTC 24 | 8753780000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/2.prim_present_test.2138780708 | Sep 01 04:25:40 AM UTC 24 | Sep 01 04:26:42 AM UTC 24 | 8785400000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/21.prim_present_test.374610844 | Sep 01 04:26:10 AM UTC 24 | Sep 01 04:26:44 AM UTC 24 | 4488180000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/17.prim_present_test.1978706806 | Sep 01 04:26:08 AM UTC 24 | Sep 01 04:26:48 AM UTC 24 | 5430580000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/29.prim_present_test.1337046398 | Sep 01 04:26:13 AM UTC 24 | Sep 01 04:26:49 AM UTC 24 | 4837240000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/39.prim_present_test.610440331 | Sep 01 04:26:19 AM UTC 24 | Sep 01 04:26:51 AM UTC 24 | 4393320000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/20.prim_present_test.1531582064 | Sep 01 04:26:09 AM UTC 24 | Sep 01 04:26:51 AM UTC 24 | 5630220000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/16.prim_present_test.3861921240 | Sep 01 04:26:08 AM UTC 24 | Sep 01 04:26:52 AM UTC 24 | 6109480000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/19.prim_present_test.2433136144 | Sep 01 04:26:09 AM UTC 24 | Sep 01 04:26:54 AM UTC 24 | 6010280000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/36.prim_present_test.153272871 | Sep 01 04:26:16 AM UTC 24 | Sep 01 04:26:55 AM UTC 24 | 5506220000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/9.prim_present_test.2416210693 | Sep 01 04:25:50 AM UTC 24 | Sep 01 04:26:58 AM UTC 24 | 9706100000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/10.prim_present_test.4084325240 | Sep 01 04:25:51 AM UTC 24 | Sep 01 04:27:00 AM UTC 24 | 9871640000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/4.prim_present_test.53572345 | Sep 01 04:25:40 AM UTC 24 | Sep 01 04:27:01 AM UTC 24 | 11890360000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/23.prim_present_test.2770233459 | Sep 01 04:26:10 AM UTC 24 | Sep 01 04:27:04 AM UTC 24 | 7601200000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/46.prim_present_test.3836518811 | Sep 01 04:26:26 AM UTC 24 | Sep 01 04:27:04 AM UTC 24 | 5702140000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/28.prim_present_test.2394048176 | Sep 01 04:26:13 AM UTC 24 | Sep 01 04:27:06 AM UTC 24 | 7578260000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/14.prim_present_test.2920337130 | Sep 01 04:26:06 AM UTC 24 | Sep 01 04:27:07 AM UTC 24 | 8642800000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/44.prim_present_test.246183419 | Sep 01 04:26:24 AM UTC 24 | Sep 01 04:27:09 AM UTC 24 | 6730720000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/41.prim_present_test.2279883086 | Sep 01 04:26:19 AM UTC 24 | Sep 01 04:27:12 AM UTC 24 | 7824400000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/0.prim_present_test.879508444 | Sep 01 04:25:39 AM UTC 24 | Sep 01 04:27:13 AM UTC 24 | 13967360000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/30.prim_present_test.3188000870 | Sep 01 04:26:13 AM UTC 24 | Sep 01 04:27:14 AM UTC 24 | 8799660000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/5.prim_present_test.2772465760 | Sep 01 04:25:40 AM UTC 24 | Sep 01 04:27:14 AM UTC 24 | 13898540000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/15.prim_present_test.2114599675 | Sep 01 04:26:08 AM UTC 24 | Sep 01 04:27:18 AM UTC 24 | 10125220000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/48.prim_present_test.1643241697 | Sep 01 04:26:29 AM UTC 24 | Sep 01 04:27:21 AM UTC 24 | 7962040000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/25.prim_present_test.3243131839 | Sep 01 04:26:10 AM UTC 24 | Sep 01 04:27:25 AM UTC 24 | 10931220000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/49.prim_present_test.2940749575 | Sep 01 04:26:30 AM UTC 24 | Sep 01 04:27:28 AM UTC 24 | 8964580000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/22.prim_present_test.3982886995 | Sep 01 04:26:10 AM UTC 24 | Sep 01 04:27:29 AM UTC 24 | 11530760000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/8.prim_present_test.2178709015 | Sep 01 04:25:49 AM UTC 24 | Sep 01 04:27:30 AM UTC 24 | 14885580000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/34.prim_present_test.3522289438 | Sep 01 04:26:13 AM UTC 24 | Sep 01 04:27:31 AM UTC 24 | 11509060000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/38.prim_present_test.400879051 | Sep 01 04:26:19 AM UTC 24 | Sep 01 04:27:32 AM UTC 24 | 10912000000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/45.prim_present_test.352015925 | Sep 01 04:26:25 AM UTC 24 | Sep 01 04:27:35 AM UTC 24 | 10722280000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/18.prim_present_test.1069978890 | Sep 01 04:26:09 AM UTC 24 | Sep 01 04:27:35 AM UTC 24 | 12548180000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/32.prim_present_test.789132566 | Sep 01 04:26:13 AM UTC 24 | Sep 01 04:27:39 AM UTC 24 | 12741620000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/33.prim_present_test.516401215 | Sep 01 04:26:13 AM UTC 24 | Sep 01 04:27:42 AM UTC 24 | 13135940000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/26.prim_present_test.2660771994 | Sep 01 04:26:11 AM UTC 24 | Sep 01 04:27:42 AM UTC 24 | 13458960000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/12.prim_present_test.3174688017 | Sep 01 04:26:03 AM UTC 24 | Sep 01 04:27:43 AM UTC 24 | 14849000000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/37.prim_present_test.2992237380 | Sep 01 04:26:18 AM UTC 24 | Sep 01 04:27:44 AM UTC 24 | 12974120000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/13.prim_present_test.3045991441 | Sep 01 04:26:04 AM UTC 24 | Sep 01 04:27:46 AM UTC 24 | 15212940000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/43.prim_present_test.939288892 | Sep 01 04:26:24 AM UTC 24 | Sep 01 04:27:48 AM UTC 24 | 12854460000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/47.prim_present_test.3169845960 | Sep 01 04:26:26 AM UTC 24 | Sep 01 04:27:48 AM UTC 24 | 12566160000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/42.prim_present_test.3588186504 | Sep 01 04:26:20 AM UTC 24 | Sep 01 04:27:52 AM UTC 24 | 13772060000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/31.prim_present_test.2229385753 | Sep 01 04:26:13 AM UTC 24 | Sep 01 04:27:53 AM UTC 24 | 14840940000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/40.prim_present_test.1232216336 | Sep 01 04:26:19 AM UTC 24 | Sep 01 04:27:55 AM UTC 24 | 14398880000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/1.prim_present_test.342816197 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8753780000 ps |
| CPU time | 17.53 seconds |
| Started | Sep 01 04:25:40 AM UTC 24 |
| Finished | Sep 01 04:26:42 AM UTC 24 |
| Peak memory | 151972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342816197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.342816197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/0.prim_present_test.879508444 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13967360000 ps |
| CPU time | 29.21 seconds |
| Started | Sep 01 04:25:39 AM UTC 24 |
| Finished | Sep 01 04:27:13 AM UTC 24 |
| Peak memory | 152172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879508444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.879508444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/10.prim_present_test.4084325240 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9871640000 ps |
| CPU time | 21.31 seconds |
| Started | Sep 01 04:25:51 AM UTC 24 |
| Finished | Sep 01 04:27:00 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084325240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.4084325240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/11.prim_present_test.965378752 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5832960000 ps |
| CPU time | 12.67 seconds |
| Started | Sep 01 04:25:57 AM UTC 24 |
| Finished | Sep 01 04:26:41 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965378752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.965378752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/12.prim_present_test.3174688017 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14849000000 ps |
| CPU time | 33.22 seconds |
| Started | Sep 01 04:26:03 AM UTC 24 |
| Finished | Sep 01 04:27:43 AM UTC 24 |
| Peak memory | 154784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174688017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3174688017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/13.prim_present_test.3045991441 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 15212940000 ps |
| CPU time | 34.19 seconds |
| Started | Sep 01 04:26:04 AM UTC 24 |
| Finished | Sep 01 04:27:46 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045991441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3045991441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/14.prim_present_test.2920337130 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8642800000 ps |
| CPU time | 19.52 seconds |
| Started | Sep 01 04:26:06 AM UTC 24 |
| Finished | Sep 01 04:27:07 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920337130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2920337130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/15.prim_present_test.2114599675 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10125220000 ps |
| CPU time | 23 seconds |
| Started | Sep 01 04:26:08 AM UTC 24 |
| Finished | Sep 01 04:27:18 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114599675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2114599675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/16.prim_present_test.3861921240 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6109480000 ps |
| CPU time | 13.65 seconds |
| Started | Sep 01 04:26:08 AM UTC 24 |
| Finished | Sep 01 04:26:52 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861921240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3861921240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/17.prim_present_test.1978706806 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5430580000 ps |
| CPU time | 12.24 seconds |
| Started | Sep 01 04:26:08 AM UTC 24 |
| Finished | Sep 01 04:26:48 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978706806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1978706806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/18.prim_present_test.1069978890 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12548180000 ps |
| CPU time | 28.42 seconds |
| Started | Sep 01 04:26:09 AM UTC 24 |
| Finished | Sep 01 04:27:35 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069978890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1069978890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/19.prim_present_test.2433136144 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6010280000 ps |
| CPU time | 13.67 seconds |
| Started | Sep 01 04:26:09 AM UTC 24 |
| Finished | Sep 01 04:26:54 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433136144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2433136144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/2.prim_present_test.2138780708 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8785400000 ps |
| CPU time | 17.7 seconds |
| Started | Sep 01 04:25:40 AM UTC 24 |
| Finished | Sep 01 04:26:42 AM UTC 24 |
| Peak memory | 151864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138780708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2138780708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/20.prim_present_test.1531582064 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5630220000 ps |
| CPU time | 12.79 seconds |
| Started | Sep 01 04:26:09 AM UTC 24 |
| Finished | Sep 01 04:26:51 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531582064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1531582064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/21.prim_present_test.374610844 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4488180000 ps |
| CPU time | 10.16 seconds |
| Started | Sep 01 04:26:10 AM UTC 24 |
| Finished | Sep 01 04:26:44 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374610844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.374610844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/22.prim_present_test.3982886995 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11530760000 ps |
| CPU time | 26.15 seconds |
| Started | Sep 01 04:26:10 AM UTC 24 |
| Finished | Sep 01 04:27:29 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982886995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3982886995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/23.prim_present_test.2770233459 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7601200000 ps |
| CPU time | 17.36 seconds |
| Started | Sep 01 04:26:10 AM UTC 24 |
| Finished | Sep 01 04:27:04 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770233459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2770233459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/24.prim_present_test.1857763595 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4006440000 ps |
| CPU time | 9.12 seconds |
| Started | Sep 01 04:26:10 AM UTC 24 |
| Finished | Sep 01 04:26:41 AM UTC 24 |
| Peak memory | 152092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857763595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1857763595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/25.prim_present_test.3243131839 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10931220000 ps |
| CPU time | 24.75 seconds |
| Started | Sep 01 04:26:10 AM UTC 24 |
| Finished | Sep 01 04:27:25 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243131839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3243131839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/26.prim_present_test.2660771994 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13458960000 ps |
| CPU time | 30.63 seconds |
| Started | Sep 01 04:26:11 AM UTC 24 |
| Finished | Sep 01 04:27:42 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660771994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2660771994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/27.prim_present_test.2939759044 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3722480000 ps |
| CPU time | 8.51 seconds |
| Started | Sep 01 04:26:11 AM UTC 24 |
| Finished | Sep 01 04:26:40 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939759044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2939759044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/28.prim_present_test.2394048176 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7578260000 ps |
| CPU time | 17.21 seconds |
| Started | Sep 01 04:26:13 AM UTC 24 |
| Finished | Sep 01 04:27:06 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394048176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2394048176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/29.prim_present_test.1337046398 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4837240000 ps |
| CPU time | 11.03 seconds |
| Started | Sep 01 04:26:13 AM UTC 24 |
| Finished | Sep 01 04:26:49 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337046398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1337046398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/3.prim_present_test.482661281 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8433240000 ps |
| CPU time | 17.22 seconds |
| Started | Sep 01 04:25:40 AM UTC 24 |
| Finished | Sep 01 04:26:40 AM UTC 24 |
| Peak memory | 152168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482661281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.482661281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/30.prim_present_test.3188000870 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8799660000 ps |
| CPU time | 20.07 seconds |
| Started | Sep 01 04:26:13 AM UTC 24 |
| Finished | Sep 01 04:27:14 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188000870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3188000870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/31.prim_present_test.2229385753 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14840940000 ps |
| CPU time | 34.03 seconds |
| Started | Sep 01 04:26:13 AM UTC 24 |
| Finished | Sep 01 04:27:53 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229385753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2229385753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/32.prim_present_test.789132566 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12741620000 ps |
| CPU time | 29.16 seconds |
| Started | Sep 01 04:26:13 AM UTC 24 |
| Finished | Sep 01 04:27:39 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789132566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.789132566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/33.prim_present_test.516401215 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13135940000 ps |
| CPU time | 30.04 seconds |
| Started | Sep 01 04:26:13 AM UTC 24 |
| Finished | Sep 01 04:27:42 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516401215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.516401215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/34.prim_present_test.3522289438 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11509060000 ps |
| CPU time | 26.36 seconds |
| Started | Sep 01 04:26:13 AM UTC 24 |
| Finished | Sep 01 04:27:31 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522289438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3522289438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/35.prim_present_test.1491413930 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3421160000 ps |
| CPU time | 7.86 seconds |
| Started | Sep 01 04:26:14 AM UTC 24 |
| Finished | Sep 01 04:26:41 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491413930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1491413930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/36.prim_present_test.153272871 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5506220000 ps |
| CPU time | 12.58 seconds |
| Started | Sep 01 04:26:16 AM UTC 24 |
| Finished | Sep 01 04:26:55 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153272871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.153272871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/37.prim_present_test.2992237380 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12974120000 ps |
| CPU time | 29.82 seconds |
| Started | Sep 01 04:26:18 AM UTC 24 |
| Finished | Sep 01 04:27:44 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992237380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2992237380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/38.prim_present_test.400879051 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10912000000 ps |
| CPU time | 25.01 seconds |
| Started | Sep 01 04:26:19 AM UTC 24 |
| Finished | Sep 01 04:27:32 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400879051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.400879051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/39.prim_present_test.610440331 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4393320000 ps |
| CPU time | 10.1 seconds |
| Started | Sep 01 04:26:19 AM UTC 24 |
| Finished | Sep 01 04:26:51 AM UTC 24 |
| Peak memory | 151320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610440331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.610440331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/4.prim_present_test.53572345 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11890360000 ps |
| CPU time | 24.88 seconds |
| Started | Sep 01 04:25:40 AM UTC 24 |
| Finished | Sep 01 04:27:01 AM UTC 24 |
| Peak memory | 153744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53572345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 4.prim_present_test.53572345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/40.prim_present_test.1232216336 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14398880000 ps |
| CPU time | 33.16 seconds |
| Started | Sep 01 04:26:19 AM UTC 24 |
| Finished | Sep 01 04:27:55 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232216336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1232216336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/41.prim_present_test.2279883086 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7824400000 ps |
| CPU time | 18.01 seconds |
| Started | Sep 01 04:26:19 AM UTC 24 |
| Finished | Sep 01 04:27:12 AM UTC 24 |
| Peak memory | 151392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279883086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2279883086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/42.prim_present_test.3588186504 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13772060000 ps |
| CPU time | 31.65 seconds |
| Started | Sep 01 04:26:20 AM UTC 24 |
| Finished | Sep 01 04:27:52 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588186504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3588186504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/43.prim_present_test.939288892 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12854460000 ps |
| CPU time | 29.41 seconds |
| Started | Sep 01 04:26:24 AM UTC 24 |
| Finished | Sep 01 04:27:48 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939288892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.939288892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/44.prim_present_test.246183419 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6730720000 ps |
| CPU time | 15.52 seconds |
| Started | Sep 01 04:26:24 AM UTC 24 |
| Finished | Sep 01 04:27:09 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246183419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.246183419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/45.prim_present_test.352015925 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10722280000 ps |
| CPU time | 24.48 seconds |
| Started | Sep 01 04:26:25 AM UTC 24 |
| Finished | Sep 01 04:27:35 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352015925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.352015925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/46.prim_present_test.3836518811 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5702140000 ps |
| CPU time | 13.23 seconds |
| Started | Sep 01 04:26:26 AM UTC 24 |
| Finished | Sep 01 04:27:04 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836518811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3836518811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/47.prim_present_test.3169845960 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12566160000 ps |
| CPU time | 29.01 seconds |
| Started | Sep 01 04:26:26 AM UTC 24 |
| Finished | Sep 01 04:27:48 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169845960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3169845960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/48.prim_present_test.1643241697 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7962040000 ps |
| CPU time | 18.4 seconds |
| Started | Sep 01 04:26:29 AM UTC 24 |
| Finished | Sep 01 04:27:21 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643241697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1643241697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/49.prim_present_test.2940749575 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8964580000 ps |
| CPU time | 20.68 seconds |
| Started | Sep 01 04:26:30 AM UTC 24 |
| Finished | Sep 01 04:27:28 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940749575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2940749575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/5.prim_present_test.2772465760 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13898540000 ps |
| CPU time | 29.43 seconds |
| Started | Sep 01 04:25:40 AM UTC 24 |
| Finished | Sep 01 04:27:14 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772465760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2772465760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/6.prim_present_test.2886239290 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3657380000 ps |
| CPU time | 6.78 seconds |
| Started | Sep 01 04:25:41 AM UTC 24 |
| Finished | Sep 01 04:26:06 AM UTC 24 |
| Peak memory | 151904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886239290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2886239290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/7.prim_present_test.1082237894 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6369880000 ps |
| CPU time | 12.46 seconds |
| Started | Sep 01 04:25:42 AM UTC 24 |
| Finished | Sep 01 04:26:29 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082237894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1082237894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/8.prim_present_test.2178709015 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14885580000 ps |
| CPU time | 32.26 seconds |
| Started | Sep 01 04:25:49 AM UTC 24 |
| Finished | Sep 01 04:27:30 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178709015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2178709015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default/9.prim_present_test.2416210693 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9706100000 ps |
| CPU time | 20.84 seconds |
| Started | Sep 01 04:25:50 AM UTC 24 |
| Finished | Sep 01 04:26:58 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416210693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2416210693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |