| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/13.prim_present_test.4254835478 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/0.prim_present_test.2368929574 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/1.prim_present_test.3780444270 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/10.prim_present_test.633603955 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/11.prim_present_test.4127797623 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/12.prim_present_test.3788787221 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/14.prim_present_test.2959325598 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/15.prim_present_test.2175786238 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/16.prim_present_test.2251375280 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/17.prim_present_test.1179065353 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/18.prim_present_test.2526526147 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/19.prim_present_test.522062270 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/2.prim_present_test.3851955330 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/20.prim_present_test.98987146 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/21.prim_present_test.2893174681 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/22.prim_present_test.3741556626 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/23.prim_present_test.3514588972 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/24.prim_present_test.4254677139 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/25.prim_present_test.2852307805 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/26.prim_present_test.2022969669 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/27.prim_present_test.2937259403 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/28.prim_present_test.4186643624 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/29.prim_present_test.2646445269 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/3.prim_present_test.527113400 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/30.prim_present_test.1632998051 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/31.prim_present_test.3099398600 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/32.prim_present_test.1996700661 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/33.prim_present_test.3309659 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/34.prim_present_test.466364098 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/35.prim_present_test.693007286 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/36.prim_present_test.2196031369 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/37.prim_present_test.2429044531 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/38.prim_present_test.3871879534 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/39.prim_present_test.123391015 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/4.prim_present_test.1269908289 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/40.prim_present_test.2951282014 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/41.prim_present_test.970982273 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/42.prim_present_test.1969660760 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/43.prim_present_test.826441103 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/44.prim_present_test.2746152587 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/45.prim_present_test.3234373243 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/46.prim_present_test.1481382141 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/47.prim_present_test.565382694 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/48.prim_present_test.3238054839 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/49.prim_present_test.4213584791 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/5.prim_present_test.3965401275 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/6.prim_present_test.493630682 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/7.prim_present_test.561482506 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/8.prim_present_test.3140190317 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/9.prim_present_test.3993418645 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/25.prim_present_test.2852307805 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:03 PM UTC 24 | 3217180000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/24.prim_present_test.4254677139 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:03 PM UTC 24 | 3295300000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/17.prim_present_test.1179065353 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:05 PM UTC 24 | 3496180000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/21.prim_present_test.2893174681 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:05 PM UTC 24 | 3586700000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/13.prim_present_test.4254835478 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:07 PM UTC 24 | 3931420000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/32.prim_present_test.1996700661 | Sep 03 09:14:39 PM UTC 24 | Sep 03 09:15:13 PM UTC 24 | 4687820000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/37.prim_present_test.2429044531 | Sep 03 09:14:42 PM UTC 24 | Sep 03 09:15:13 PM UTC 24 | 4285440000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/2.prim_present_test.3851955330 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:15:15 PM UTC 24 | 5400200000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/5.prim_present_test.3965401275 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:15:17 PM UTC 24 | 5652540000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/48.prim_present_test.3238054839 | Sep 03 09:14:43 PM UTC 24 | Sep 03 09:15:17 PM UTC 24 | 4876920000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/8.prim_present_test.3140190317 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:15:18 PM UTC 24 | 5870160000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/34.prim_present_test.466364098 | Sep 03 09:14:39 PM UTC 24 | Sep 03 09:15:22 PM UTC 24 | 6107620000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/3.prim_present_test.527113400 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:15:23 PM UTC 24 | 6599900000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/11.prim_present_test.4127797623 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:15:23 PM UTC 24 | 6616020000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/16.prim_present_test.2251375280 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:25 PM UTC 24 | 6554020000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/41.prim_present_test.970982273 | Sep 03 09:14:42 PM UTC 24 | Sep 03 09:15:25 PM UTC 24 | 6062980000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/31.prim_present_test.3099398600 | Sep 03 09:14:39 PM UTC 24 | Sep 03 09:15:28 PM UTC 24 | 6885720000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/35.prim_present_test.693007286 | Sep 03 09:14:39 PM UTC 24 | Sep 03 09:15:28 PM UTC 24 | 6914240000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/49.prim_present_test.4213584791 | Sep 03 09:14:43 PM UTC 24 | Sep 03 09:15:29 PM UTC 24 | 6534800000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/38.prim_present_test.3871879534 | Sep 03 09:14:42 PM UTC 24 | Sep 03 09:15:35 PM UTC 24 | 7395980000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/46.prim_present_test.1481382141 | Sep 03 09:14:43 PM UTC 24 | Sep 03 09:15:36 PM UTC 24 | 7435040000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/40.prim_present_test.2951282014 | Sep 03 09:14:42 PM UTC 24 | Sep 03 09:15:37 PM UTC 24 | 7662580000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/19.prim_present_test.522062270 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:38 PM UTC 24 | 8331560000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/4.prim_present_test.1269908289 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:15:40 PM UTC 24 | 8953420000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/9.prim_present_test.3993418645 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:15:42 PM UTC 24 | 9319840000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/30.prim_present_test.1632998051 | Sep 03 09:14:39 PM UTC 24 | Sep 03 09:15:44 PM UTC 24 | 9213820000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/28.prim_present_test.4186643624 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:46 PM UTC 24 | 9548620000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/47.prim_present_test.565382694 | Sep 03 09:14:43 PM UTC 24 | Sep 03 09:15:47 PM UTC 24 | 9188400000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/45.prim_present_test.3234373243 | Sep 03 09:14:43 PM UTC 24 | Sep 03 09:15:47 PM UTC 24 | 9233660000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/18.prim_present_test.2526526147 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:48 PM UTC 24 | 9851180000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/10.prim_present_test.633603955 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:15:49 PM UTC 24 | 10240540000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/29.prim_present_test.2646445269 | Sep 03 09:14:39 PM UTC 24 | Sep 03 09:15:51 PM UTC 24 | 10247980000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/22.prim_present_test.3741556626 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:52 PM UTC 24 | 10443280000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/26.prim_present_test.2022969669 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:15:55 PM UTC 24 | 10948580000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/1.prim_present_test.3780444270 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:15:58 PM UTC 24 | 11703120000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/7.prim_present_test.561482506 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:16:00 PM UTC 24 | 11946160000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/39.prim_present_test.123391015 | Sep 03 09:14:42 PM UTC 24 | Sep 03 09:16:03 PM UTC 24 | 11536340000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/42.prim_present_test.1969660760 | Sep 03 09:14:42 PM UTC 24 | Sep 03 09:16:06 PM UTC 24 | 12049080000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/6.prim_present_test.493630682 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:16:13 PM UTC 24 | 13958060000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/0.prim_present_test.2368929574 | Sep 03 09:14:36 PM UTC 24 | Sep 03 09:16:13 PM UTC 24 | 13984100000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/15.prim_present_test.2175786238 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:16:17 PM UTC 24 | 14313320000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/33.prim_present_test.3309659 | Sep 03 09:14:39 PM UTC 24 | Sep 03 09:16:18 PM UTC 24 | 14340600000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/14.prim_present_test.2959325598 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:16:20 PM UTC 24 | 14744220000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/23.prim_present_test.3514588972 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:16:21 PM UTC 24 | 14829780000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/12.prim_present_test.3788787221 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:16:21 PM UTC 24 | 14985400000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/43.prim_present_test.826441103 | Sep 03 09:14:42 PM UTC 24 | Sep 03 09:16:22 PM UTC 24 | 14437940000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/36.prim_present_test.2196031369 | Sep 03 09:14:42 PM UTC 24 | Sep 03 09:16:22 PM UTC 24 | 14515440000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/44.prim_present_test.2746152587 | Sep 03 09:14:43 PM UTC 24 | Sep 03 09:16:22 PM UTC 24 | 14528460000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/27.prim_present_test.2937259403 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:16:24 PM UTC 24 | 15344380000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/20.prim_present_test.98987146 | Sep 03 09:14:38 PM UTC 24 | Sep 03 09:16:25 PM UTC 24 | 15493800000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/13.prim_present_test.4254835478 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3931420000 ps |
| CPU time | 8.86 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:07 PM UTC 24 |
| Peak memory | 152092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254835478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.4254835478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/0.prim_present_test.2368929574 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13984100000 ps |
| CPU time | 30.2 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:16:13 PM UTC 24 |
| Peak memory | 151948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368929574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2368929574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/1.prim_present_test.3780444270 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11703120000 ps |
| CPU time | 25.18 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:15:58 PM UTC 24 |
| Peak memory | 150312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780444270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3780444270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/10.prim_present_test.633603955 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10240540000 ps |
| CPU time | 22.19 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:15:49 PM UTC 24 |
| Peak memory | 152068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633603955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.633603955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/11.prim_present_test.4127797623 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6616020000 ps |
| CPU time | 14.48 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:15:23 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127797623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4127797623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/12.prim_present_test.3788787221 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14985400000 ps |
| CPU time | 32.01 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:16:21 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788787221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3788787221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/14.prim_present_test.2959325598 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14744220000 ps |
| CPU time | 31.56 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:16:20 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959325598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2959325598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/15.prim_present_test.2175786238 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14313320000 ps |
| CPU time | 30.5 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:16:17 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175786238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2175786238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/16.prim_present_test.2251375280 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6554020000 ps |
| CPU time | 14.48 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:25 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251375280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2251375280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/17.prim_present_test.1179065353 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3496180000 ps |
| CPU time | 8.13 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:05 PM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179065353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1179065353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/18.prim_present_test.2526526147 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9851180000 ps |
| CPU time | 21.41 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:48 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526526147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2526526147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/19.prim_present_test.522062270 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8331560000 ps |
| CPU time | 18.35 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:38 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522062270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.522062270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/2.prim_present_test.3851955330 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5400200000 ps |
| CPU time | 11.86 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:15:15 PM UTC 24 |
| Peak memory | 149988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851955330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3851955330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/20.prim_present_test.98987146 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15493800000 ps |
| CPU time | 32.98 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:16:25 PM UTC 24 |
| Peak memory | 152168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98987146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 20.prim_present_test.98987146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/21.prim_present_test.2893174681 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3586700000 ps |
| CPU time | 8.09 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:05 PM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893174681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2893174681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/22.prim_present_test.3741556626 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10443280000 ps |
| CPU time | 22.61 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:52 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741556626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3741556626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/23.prim_present_test.3514588972 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14829780000 ps |
| CPU time | 31.56 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:16:21 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514588972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3514588972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/24.prim_present_test.4254677139 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3295300000 ps |
| CPU time | 7.5 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:03 PM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254677139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4254677139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/25.prim_present_test.2852307805 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3217180000 ps |
| CPU time | 7.35 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:03 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852307805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2852307805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/26.prim_present_test.2022969669 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10948580000 ps |
| CPU time | 23.35 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:55 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022969669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2022969669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/27.prim_present_test.2937259403 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15344380000 ps |
| CPU time | 32.47 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:16:24 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937259403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2937259403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/28.prim_present_test.4186643624 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9548620000 ps |
| CPU time | 20.76 seconds |
| Started | Sep 03 09:14:38 PM UTC 24 |
| Finished | Sep 03 09:15:46 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186643624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.4186643624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/29.prim_present_test.2646445269 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10247980000 ps |
| CPU time | 22.19 seconds |
| Started | Sep 03 09:14:39 PM UTC 24 |
| Finished | Sep 03 09:15:51 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646445269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2646445269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/3.prim_present_test.527113400 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6599900000 ps |
| CPU time | 14.53 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:15:23 PM UTC 24 |
| Peak memory | 151980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527113400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.527113400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/30.prim_present_test.1632998051 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9213820000 ps |
| CPU time | 19.91 seconds |
| Started | Sep 03 09:14:39 PM UTC 24 |
| Finished | Sep 03 09:15:44 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632998051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1632998051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/31.prim_present_test.3099398600 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6885720000 ps |
| CPU time | 15.04 seconds |
| Started | Sep 03 09:14:39 PM UTC 24 |
| Finished | Sep 03 09:15:28 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099398600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3099398600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/32.prim_present_test.1996700661 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4687820000 ps |
| CPU time | 10.49 seconds |
| Started | Sep 03 09:14:39 PM UTC 24 |
| Finished | Sep 03 09:15:13 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996700661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1996700661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/33.prim_present_test.3309659 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14340600000 ps |
| CPU time | 31.05 seconds |
| Started | Sep 03 09:14:39 PM UTC 24 |
| Finished | Sep 03 09:16:18 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 33.prim_present_test.3309659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/34.prim_present_test.466364098 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6107620000 ps |
| CPU time | 13.44 seconds |
| Started | Sep 03 09:14:39 PM UTC 24 |
| Finished | Sep 03 09:15:22 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466364098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.466364098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/35.prim_present_test.693007286 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6914240000 ps |
| CPU time | 15.06 seconds |
| Started | Sep 03 09:14:39 PM UTC 24 |
| Finished | Sep 03 09:15:28 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693007286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.693007286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/36.prim_present_test.2196031369 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14515440000 ps |
| CPU time | 31.02 seconds |
| Started | Sep 03 09:14:42 PM UTC 24 |
| Finished | Sep 03 09:16:22 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196031369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2196031369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/37.prim_present_test.2429044531 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4285440000 ps |
| CPU time | 9.67 seconds |
| Started | Sep 03 09:14:42 PM UTC 24 |
| Finished | Sep 03 09:15:13 PM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429044531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2429044531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/38.prim_present_test.3871879534 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7395980000 ps |
| CPU time | 16.16 seconds |
| Started | Sep 03 09:14:42 PM UTC 24 |
| Finished | Sep 03 09:15:35 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871879534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3871879534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/39.prim_present_test.123391015 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11536340000 ps |
| CPU time | 24.77 seconds |
| Started | Sep 03 09:14:42 PM UTC 24 |
| Finished | Sep 03 09:16:03 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123391015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.123391015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/4.prim_present_test.1269908289 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8953420000 ps |
| CPU time | 19.43 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:15:40 PM UTC 24 |
| Peak memory | 150252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269908289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1269908289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/40.prim_present_test.2951282014 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7662580000 ps |
| CPU time | 16.63 seconds |
| Started | Sep 03 09:14:42 PM UTC 24 |
| Finished | Sep 03 09:15:37 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951282014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2951282014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/41.prim_present_test.970982273 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6062980000 ps |
| CPU time | 13.39 seconds |
| Started | Sep 03 09:14:42 PM UTC 24 |
| Finished | Sep 03 09:15:25 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970982273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.970982273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/42.prim_present_test.1969660760 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12049080000 ps |
| CPU time | 25.47 seconds |
| Started | Sep 03 09:14:42 PM UTC 24 |
| Finished | Sep 03 09:16:06 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969660760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1969660760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/43.prim_present_test.826441103 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14437940000 ps |
| CPU time | 30.83 seconds |
| Started | Sep 03 09:14:42 PM UTC 24 |
| Finished | Sep 03 09:16:22 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826441103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.826441103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/44.prim_present_test.2746152587 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14528460000 ps |
| CPU time | 31.02 seconds |
| Started | Sep 03 09:14:43 PM UTC 24 |
| Finished | Sep 03 09:16:22 PM UTC 24 |
| Peak memory | 152096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746152587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2746152587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/45.prim_present_test.3234373243 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9233660000 ps |
| CPU time | 20.12 seconds |
| Started | Sep 03 09:14:43 PM UTC 24 |
| Finished | Sep 03 09:15:47 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234373243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3234373243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/46.prim_present_test.1481382141 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7435040000 ps |
| CPU time | 16.28 seconds |
| Started | Sep 03 09:14:43 PM UTC 24 |
| Finished | Sep 03 09:15:36 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481382141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1481382141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/47.prim_present_test.565382694 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9188400000 ps |
| CPU time | 20.12 seconds |
| Started | Sep 03 09:14:43 PM UTC 24 |
| Finished | Sep 03 09:15:47 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565382694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.565382694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/48.prim_present_test.3238054839 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4876920000 ps |
| CPU time | 10.99 seconds |
| Started | Sep 03 09:14:43 PM UTC 24 |
| Finished | Sep 03 09:15:17 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238054839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3238054839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/49.prim_present_test.4213584791 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6534800000 ps |
| CPU time | 14.31 seconds |
| Started | Sep 03 09:14:43 PM UTC 24 |
| Finished | Sep 03 09:15:29 PM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213584791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4213584791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/5.prim_present_test.3965401275 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5652540000 ps |
| CPU time | 12.56 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:15:17 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965401275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3965401275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/6.prim_present_test.493630682 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13958060000 ps |
| CPU time | 30.17 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:16:13 PM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493630682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.493630682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/7.prim_present_test.561482506 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11946160000 ps |
| CPU time | 25.28 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:16:00 PM UTC 24 |
| Peak memory | 151776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561482506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.561482506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/8.prim_present_test.3140190317 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5870160000 ps |
| CPU time | 12.95 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:15:18 PM UTC 24 |
| Peak memory | 151732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140190317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3140190317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default/9.prim_present_test.3993418645 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9319840000 ps |
| CPU time | 20.34 seconds |
| Started | Sep 03 09:14:36 PM UTC 24 |
| Finished | Sep 03 09:15:42 PM UTC 24 |
| Peak memory | 152036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993418645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3993418645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_present-sim-vcs/9.prim_present_test/latest |
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