| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/0.prim_present_test.629454952 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/1.prim_present_test.299227712 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/10.prim_present_test.2365685453 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/11.prim_present_test.926675089 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/12.prim_present_test.1485537769 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/13.prim_present_test.104384640 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/14.prim_present_test.1618761579 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/15.prim_present_test.47323012 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/16.prim_present_test.3062183677 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/17.prim_present_test.3492920981 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/18.prim_present_test.1186420834 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/19.prim_present_test.3415215378 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/2.prim_present_test.3292949200 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/20.prim_present_test.2839572253 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/21.prim_present_test.4169911831 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/22.prim_present_test.1035130635 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/23.prim_present_test.3869077821 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/24.prim_present_test.2146089632 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/25.prim_present_test.627050797 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/26.prim_present_test.1745052117 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/27.prim_present_test.2397715813 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/28.prim_present_test.1432253369 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/29.prim_present_test.301596601 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/3.prim_present_test.2455416400 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/30.prim_present_test.4208730023 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/31.prim_present_test.4086670878 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/32.prim_present_test.1317049638 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/33.prim_present_test.4237516295 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/34.prim_present_test.604333323 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/35.prim_present_test.739894366 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/36.prim_present_test.793506407 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/37.prim_present_test.3776436463 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/38.prim_present_test.3191222521 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/39.prim_present_test.2116047538 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/4.prim_present_test.1832689278 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/40.prim_present_test.4102028027 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/41.prim_present_test.4150381001 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/42.prim_present_test.395471571 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/43.prim_present_test.1386774314 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/44.prim_present_test.1349843268 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/45.prim_present_test.2841266773 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/46.prim_present_test.2352494402 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/47.prim_present_test.2940122289 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/48.prim_present_test.4286039443 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/49.prim_present_test.1893022840 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/5.prim_present_test.3297031950 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/6.prim_present_test.1771104682 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/7.prim_present_test.199209687 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/8.prim_present_test.3154901717 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/9.prim_present_test.3273722995 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/1.prim_present_test.299227712 | Sep 09 03:12:54 AM UTC 24 | Sep 09 03:13:19 AM UTC 24 | 3679700000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/4.prim_present_test.1832689278 | Sep 09 03:12:54 AM UTC 24 | Sep 09 03:13:25 AM UTC 24 | 4803140000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/3.prim_present_test.2455416400 | Sep 09 03:12:54 AM UTC 24 | Sep 09 03:13:27 AM UTC 24 | 4978600000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/0.prim_present_test.629454952 | Sep 09 03:12:53 AM UTC 24 | Sep 09 03:13:30 AM UTC 24 | 5729420000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/5.prim_present_test.3297031950 | Sep 09 03:12:56 AM UTC 24 | Sep 09 03:13:40 AM UTC 24 | 6897500000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/8.prim_present_test.3154901717 | Sep 09 03:13:26 AM UTC 24 | Sep 09 03:13:57 AM UTC 24 | 4865140000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/6.prim_present_test.1771104682 | Sep 09 03:12:57 AM UTC 24 | Sep 09 03:14:08 AM UTC 24 | 11215800000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/2.prim_present_test.3292949200 | Sep 09 03:12:54 AM UTC 24 | Sep 09 03:14:18 AM UTC 24 | 13435400000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/10.prim_present_test.2365685453 | Sep 09 03:13:31 AM UTC 24 | Sep 09 03:14:36 AM UTC 24 | 10238680000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/11.prim_present_test.926675089 | Sep 09 03:13:41 AM UTC 24 | Sep 09 03:14:38 AM UTC 24 | 9037740000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/9.prim_present_test.3273722995 | Sep 09 03:13:28 AM UTC 24 | Sep 09 03:14:41 AM UTC 24 | 11826500000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/7.prim_present_test.199209687 | Sep 09 03:13:20 AM UTC 24 | Sep 09 03:14:43 AM UTC 24 | 13232660000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/14.prim_present_test.1618761579 | Sep 09 03:14:19 AM UTC 24 | Sep 09 03:14:58 AM UTC 24 | 6036940000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/16.prim_present_test.3062183677 | Sep 09 03:14:38 AM UTC 24 | Sep 09 03:15:04 AM UTC 24 | 3918400000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/18.prim_present_test.1186420834 | Sep 09 03:14:44 AM UTC 24 | Sep 09 03:15:15 AM UTC 24 | 4713860000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/12.prim_present_test.1485537769 | Sep 09 03:13:58 AM UTC 24 | Sep 09 03:15:25 AM UTC 24 | 13648680000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/20.prim_present_test.2839572253 | Sep 09 03:15:04 AM UTC 24 | Sep 09 03:15:30 AM UTC 24 | 3910340000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/13.prim_present_test.104384640 | Sep 09 03:14:09 AM UTC 24 | Sep 09 03:15:33 AM UTC 24 | 13035500000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/15.prim_present_test.47323012 | Sep 09 03:14:36 AM UTC 24 | Sep 09 03:15:50 AM UTC 24 | 11496040000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/17.prim_present_test.3492920981 | Sep 09 03:14:42 AM UTC 24 | Sep 09 03:16:00 AM UTC 24 | 12215860000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/25.prim_present_test.627050797 | Sep 09 03:15:51 AM UTC 24 | Sep 09 03:16:14 AM UTC 24 | 3410000000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/19.prim_present_test.3415215378 | Sep 09 03:14:58 AM UTC 24 | Sep 09 03:16:22 AM UTC 24 | 13114240000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/21.prim_present_test.4169911831 | Sep 09 03:15:15 AM UTC 24 | Sep 09 03:16:26 AM UTC 24 | 10905180000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/22.prim_present_test.1035130635 | Sep 09 03:15:25 AM UTC 24 | Sep 09 03:16:26 AM UTC 24 | 9448800000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/24.prim_present_test.2146089632 | Sep 09 03:15:34 AM UTC 24 | Sep 09 03:16:37 AM UTC 24 | 9910080000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/23.prim_present_test.3869077821 | Sep 09 03:15:31 AM UTC 24 | Sep 09 03:17:01 AM UTC 24 | 14184360000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/30.prim_present_test.4208730023 | Sep 09 03:16:27 AM UTC 24 | Sep 09 03:17:06 AM UTC 24 | 6127460000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/27.prim_present_test.2397715813 | Sep 09 03:16:15 AM UTC 24 | Sep 09 03:17:19 AM UTC 24 | 10140100000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/26.prim_present_test.1745052117 | Sep 09 03:16:01 AM UTC 24 | Sep 09 03:17:29 AM UTC 24 | 14034940000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/31.prim_present_test.4086670878 | Sep 09 03:16:38 AM UTC 24 | Sep 09 03:17:31 AM UTC 24 | 8286920000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/28.prim_present_test.1432253369 | Sep 09 03:16:23 AM UTC 24 | Sep 09 03:17:32 AM UTC 24 | 10905800000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/29.prim_present_test.301596601 | Sep 09 03:16:26 AM UTC 24 | Sep 09 03:17:33 AM UTC 24 | 10535040000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/33.prim_present_test.4237516295 | Sep 09 03:17:07 AM UTC 24 | Sep 09 03:17:50 AM UTC 24 | 6675540000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/32.prim_present_test.1317049638 | Sep 09 03:17:01 AM UTC 24 | Sep 09 03:18:14 AM UTC 24 | 11533860000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/34.prim_present_test.604333323 | Sep 09 03:17:20 AM UTC 24 | Sep 09 03:18:21 AM UTC 24 | 9578380000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/35.prim_present_test.739894366 | Sep 09 03:17:30 AM UTC 24 | Sep 09 03:18:32 AM UTC 24 | 9600700000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/36.prim_present_test.793506407 | Sep 09 03:17:31 AM UTC 24 | Sep 09 03:18:45 AM UTC 24 | 11561140000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/38.prim_present_test.3191222521 | Sep 09 03:17:34 AM UTC 24 | Sep 09 03:18:58 AM UTC 24 | 13290940000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/37.prim_present_test.3776436463 | Sep 09 03:17:33 AM UTC 24 | Sep 09 03:19:04 AM UTC 24 | 14390820000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/39.prim_present_test.2116047538 | Sep 09 03:17:51 AM UTC 24 | Sep 09 03:19:17 AM UTC 24 | 13379600000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/40.prim_present_test.4102028027 | Sep 09 03:18:15 AM UTC 24 | Sep 09 03:19:26 AM UTC 24 | 10975240000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/42.prim_present_test.395471571 | Sep 09 03:18:33 AM UTC 24 | Sep 09 03:19:26 AM UTC 24 | 8130060000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/44.prim_present_test.1349843268 | Sep 09 03:18:59 AM UTC 24 | Sep 09 03:19:26 AM UTC 24 | 3961180000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/45.prim_present_test.2841266773 | Sep 09 03:19:05 AM UTC 24 | Sep 09 03:19:35 AM UTC 24 | 4292260000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/41.prim_present_test.4150381001 | Sep 09 03:18:22 AM UTC 24 | Sep 09 03:19:35 AM UTC 24 | 11356540000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/43.prim_present_test.1386774314 | Sep 09 03:18:46 AM UTC 24 | Sep 09 03:20:10 AM UTC 24 | 12945600000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/47.prim_present_test.2940122289 | Sep 09 03:19:26 AM UTC 24 | Sep 09 03:20:15 AM UTC 24 | 7367460000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/46.prim_present_test.2352494402 | Sep 09 03:19:17 AM UTC 24 | Sep 09 03:20:21 AM UTC 24 | 9676340000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/48.prim_present_test.4286039443 | Sep 09 03:19:26 AM UTC 24 | Sep 09 03:20:24 AM UTC 24 | 8759360000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/49.prim_present_test.1893022840 | Sep 09 03:19:26 AM UTC 24 | Sep 09 03:21:06 AM UTC 24 | 14744840000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/0.prim_present_test.629454952 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5729420000 ps |
| CPU time | 12.68 seconds |
| Started | Sep 09 03:12:53 AM UTC 24 |
| Finished | Sep 09 03:13:30 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629454952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.629454952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/1.prim_present_test.299227712 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3679700000 ps |
| CPU time | 8.33 seconds |
| Started | Sep 09 03:12:54 AM UTC 24 |
| Finished | Sep 09 03:13:19 AM UTC 24 |
| Peak memory | 152168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299227712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.299227712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/10.prim_present_test.2365685453 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10238680000 ps |
| CPU time | 22.51 seconds |
| Started | Sep 09 03:13:31 AM UTC 24 |
| Finished | Sep 09 03:14:36 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365685453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2365685453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/11.prim_present_test.926675089 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9037740000 ps |
| CPU time | 19.56 seconds |
| Started | Sep 09 03:13:41 AM UTC 24 |
| Finished | Sep 09 03:14:38 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926675089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.926675089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/12.prim_present_test.1485537769 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13648680000 ps |
| CPU time | 29.76 seconds |
| Started | Sep 09 03:13:58 AM UTC 24 |
| Finished | Sep 09 03:15:25 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485537769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1485537769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/13.prim_present_test.104384640 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13035500000 ps |
| CPU time | 28.54 seconds |
| Started | Sep 09 03:14:09 AM UTC 24 |
| Finished | Sep 09 03:15:33 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104384640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.104384640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/14.prim_present_test.1618761579 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6036940000 ps |
| CPU time | 13.13 seconds |
| Started | Sep 09 03:14:19 AM UTC 24 |
| Finished | Sep 09 03:14:58 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618761579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1618761579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/15.prim_present_test.47323012 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11496040000 ps |
| CPU time | 25.09 seconds |
| Started | Sep 09 03:14:36 AM UTC 24 |
| Finished | Sep 09 03:15:50 AM UTC 24 |
| Peak memory | 152168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47323012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 15.prim_present_test.47323012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/16.prim_present_test.3062183677 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3918400000 ps |
| CPU time | 8.74 seconds |
| Started | Sep 09 03:14:38 AM UTC 24 |
| Finished | Sep 09 03:15:04 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062183677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3062183677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/17.prim_present_test.3492920981 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12215860000 ps |
| CPU time | 26.15 seconds |
| Started | Sep 09 03:14:42 AM UTC 24 |
| Finished | Sep 09 03:16:00 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492920981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3492920981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/18.prim_present_test.1186420834 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4713860000 ps |
| CPU time | 10.46 seconds |
| Started | Sep 09 03:14:44 AM UTC 24 |
| Finished | Sep 09 03:15:15 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186420834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1186420834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/19.prim_present_test.3415215378 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13114240000 ps |
| CPU time | 28.66 seconds |
| Started | Sep 09 03:14:58 AM UTC 24 |
| Finished | Sep 09 03:16:22 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415215378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3415215378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/2.prim_present_test.3292949200 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13435400000 ps |
| CPU time | 28.59 seconds |
| Started | Sep 09 03:12:54 AM UTC 24 |
| Finished | Sep 09 03:14:18 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292949200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3292949200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/20.prim_present_test.2839572253 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3910340000 ps |
| CPU time | 8.74 seconds |
| Started | Sep 09 03:15:04 AM UTC 24 |
| Finished | Sep 09 03:15:30 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839572253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2839572253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/21.prim_present_test.4169911831 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10905180000 ps |
| CPU time | 23.99 seconds |
| Started | Sep 09 03:15:15 AM UTC 24 |
| Finished | Sep 09 03:16:26 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169911831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4169911831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/22.prim_present_test.1035130635 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9448800000 ps |
| CPU time | 20.54 seconds |
| Started | Sep 09 03:15:25 AM UTC 24 |
| Finished | Sep 09 03:16:26 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035130635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1035130635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/23.prim_present_test.3869077821 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14184360000 ps |
| CPU time | 30.81 seconds |
| Started | Sep 09 03:15:31 AM UTC 24 |
| Finished | Sep 09 03:17:01 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869077821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3869077821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/24.prim_present_test.2146089632 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9910080000 ps |
| CPU time | 21.68 seconds |
| Started | Sep 09 03:15:34 AM UTC 24 |
| Finished | Sep 09 03:16:37 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146089632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2146089632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/25.prim_present_test.627050797 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3410000000 ps |
| CPU time | 7.62 seconds |
| Started | Sep 09 03:15:51 AM UTC 24 |
| Finished | Sep 09 03:16:14 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627050797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.627050797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/26.prim_present_test.1745052117 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14034940000 ps |
| CPU time | 30.01 seconds |
| Started | Sep 09 03:16:01 AM UTC 24 |
| Finished | Sep 09 03:17:29 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745052117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1745052117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/27.prim_present_test.2397715813 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10140100000 ps |
| CPU time | 22.11 seconds |
| Started | Sep 09 03:16:15 AM UTC 24 |
| Finished | Sep 09 03:17:19 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397715813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2397715813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/28.prim_present_test.1432253369 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10905800000 ps |
| CPU time | 23.71 seconds |
| Started | Sep 09 03:16:23 AM UTC 24 |
| Finished | Sep 09 03:17:32 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432253369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1432253369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/29.prim_present_test.301596601 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10535040000 ps |
| CPU time | 23.03 seconds |
| Started | Sep 09 03:16:26 AM UTC 24 |
| Finished | Sep 09 03:17:33 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301596601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.301596601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/3.prim_present_test.2455416400 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4978600000 ps |
| CPU time | 11.05 seconds |
| Started | Sep 09 03:12:54 AM UTC 24 |
| Finished | Sep 09 03:13:27 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455416400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2455416400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/30.prim_present_test.4208730023 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6127460000 ps |
| CPU time | 13.44 seconds |
| Started | Sep 09 03:16:27 AM UTC 24 |
| Finished | Sep 09 03:17:06 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208730023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4208730023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/31.prim_present_test.4086670878 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8286920000 ps |
| CPU time | 18.02 seconds |
| Started | Sep 09 03:16:38 AM UTC 24 |
| Finished | Sep 09 03:17:31 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086670878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4086670878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/32.prim_present_test.1317049638 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11533860000 ps |
| CPU time | 25.02 seconds |
| Started | Sep 09 03:17:01 AM UTC 24 |
| Finished | Sep 09 03:18:14 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317049638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1317049638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/33.prim_present_test.4237516295 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6675540000 ps |
| CPU time | 14.64 seconds |
| Started | Sep 09 03:17:07 AM UTC 24 |
| Finished | Sep 09 03:17:50 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237516295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.4237516295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/34.prim_present_test.604333323 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9578380000 ps |
| CPU time | 20.9 seconds |
| Started | Sep 09 03:17:20 AM UTC 24 |
| Finished | Sep 09 03:18:21 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604333323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.604333323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/35.prim_present_test.739894366 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9600700000 ps |
| CPU time | 20.84 seconds |
| Started | Sep 09 03:17:30 AM UTC 24 |
| Finished | Sep 09 03:18:32 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739894366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.739894366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/36.prim_present_test.793506407 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11561140000 ps |
| CPU time | 24.99 seconds |
| Started | Sep 09 03:17:31 AM UTC 24 |
| Finished | Sep 09 03:18:45 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793506407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.793506407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/37.prim_present_test.3776436463 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 14390820000 ps |
| CPU time | 31.1 seconds |
| Started | Sep 09 03:17:33 AM UTC 24 |
| Finished | Sep 09 03:19:04 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776436463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3776436463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/38.prim_present_test.3191222521 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13290940000 ps |
| CPU time | 28.5 seconds |
| Started | Sep 09 03:17:34 AM UTC 24 |
| Finished | Sep 09 03:18:58 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191222521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3191222521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/39.prim_present_test.2116047538 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13379600000 ps |
| CPU time | 29.07 seconds |
| Started | Sep 09 03:17:51 AM UTC 24 |
| Finished | Sep 09 03:19:17 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116047538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2116047538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/4.prim_present_test.1832689278 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4803140000 ps |
| CPU time | 10.44 seconds |
| Started | Sep 09 03:12:54 AM UTC 24 |
| Finished | Sep 09 03:13:25 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832689278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1832689278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/40.prim_present_test.4102028027 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10975240000 ps |
| CPU time | 23.9 seconds |
| Started | Sep 09 03:18:15 AM UTC 24 |
| Finished | Sep 09 03:19:26 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102028027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4102028027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/41.prim_present_test.4150381001 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11356540000 ps |
| CPU time | 24.75 seconds |
| Started | Sep 09 03:18:22 AM UTC 24 |
| Finished | Sep 09 03:19:35 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150381001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.4150381001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/42.prim_present_test.395471571 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8130060000 ps |
| CPU time | 17.59 seconds |
| Started | Sep 09 03:18:33 AM UTC 24 |
| Finished | Sep 09 03:19:26 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395471571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.395471571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/43.prim_present_test.1386774314 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12945600000 ps |
| CPU time | 27.94 seconds |
| Started | Sep 09 03:18:46 AM UTC 24 |
| Finished | Sep 09 03:20:10 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386774314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1386774314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/44.prim_present_test.1349843268 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3961180000 ps |
| CPU time | 8.93 seconds |
| Started | Sep 09 03:18:59 AM UTC 24 |
| Finished | Sep 09 03:19:26 AM UTC 24 |
| Peak memory | 152084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349843268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1349843268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/45.prim_present_test.2841266773 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4292260000 ps |
| CPU time | 9.65 seconds |
| Started | Sep 09 03:19:05 AM UTC 24 |
| Finished | Sep 09 03:19:35 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841266773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2841266773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/46.prim_present_test.2352494402 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9676340000 ps |
| CPU time | 21 seconds |
| Started | Sep 09 03:19:17 AM UTC 24 |
| Finished | Sep 09 03:20:21 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352494402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2352494402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/47.prim_present_test.2940122289 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7367460000 ps |
| CPU time | 16.2 seconds |
| Started | Sep 09 03:19:26 AM UTC 24 |
| Finished | Sep 09 03:20:15 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940122289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2940122289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/48.prim_present_test.4286039443 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8759360000 ps |
| CPU time | 19.12 seconds |
| Started | Sep 09 03:19:26 AM UTC 24 |
| Finished | Sep 09 03:20:24 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286039443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4286039443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/49.prim_present_test.1893022840 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14744840000 ps |
| CPU time | 32.53 seconds |
| Started | Sep 09 03:19:26 AM UTC 24 |
| Finished | Sep 09 03:21:06 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893022840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1893022840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/5.prim_present_test.3297031950 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 6897500000 ps |
| CPU time | 14.96 seconds |
| Started | Sep 09 03:12:56 AM UTC 24 |
| Finished | Sep 09 03:13:40 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297031950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3297031950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/6.prim_present_test.1771104682 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11215800000 ps |
| CPU time | 24.6 seconds |
| Started | Sep 09 03:12:57 AM UTC 24 |
| Finished | Sep 09 03:14:08 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771104682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1771104682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/7.prim_present_test.199209687 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13232660000 ps |
| CPU time | 28.94 seconds |
| Started | Sep 09 03:13:20 AM UTC 24 |
| Finished | Sep 09 03:14:43 AM UTC 24 |
| Peak memory | 152168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199209687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.199209687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/8.prim_present_test.3154901717 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4865140000 ps |
| CPU time | 10.86 seconds |
| Started | Sep 09 03:13:26 AM UTC 24 |
| Finished | Sep 09 03:13:57 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154901717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3154901717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default/9.prim_present_test.3273722995 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11826500000 ps |
| CPU time | 25.22 seconds |
| Started | Sep 09 03:13:28 AM UTC 24 |
| Finished | Sep 09 03:14:41 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273722995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3273722995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |