| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/1.prim_present_test.4025722426 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/0.prim_present_test.1912534479 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/10.prim_present_test.1267207440 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/11.prim_present_test.2119787337 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/12.prim_present_test.537928957 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/13.prim_present_test.2083376895 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/14.prim_present_test.2127958742 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/15.prim_present_test.3931600615 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/16.prim_present_test.4096694905 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/17.prim_present_test.329030836 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/18.prim_present_test.2994172432 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/19.prim_present_test.3957719063 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/2.prim_present_test.3654896077 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/20.prim_present_test.3696783603 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/21.prim_present_test.4116073184 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/22.prim_present_test.3094356678 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/23.prim_present_test.2731772005 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/24.prim_present_test.1713921795 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/25.prim_present_test.3855861051 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/26.prim_present_test.1788613466 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/27.prim_present_test.2508418643 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/28.prim_present_test.2118423529 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/29.prim_present_test.2247711925 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/3.prim_present_test.3170117906 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/30.prim_present_test.3060032610 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/31.prim_present_test.4286283048 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/32.prim_present_test.1638672712 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/33.prim_present_test.3064434098 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/34.prim_present_test.3795105462 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/35.prim_present_test.762587699 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/36.prim_present_test.3708324426 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/37.prim_present_test.2020078760 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/38.prim_present_test.653863812 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/39.prim_present_test.3644350516 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/4.prim_present_test.2185309109 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/40.prim_present_test.1487051116 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/41.prim_present_test.1478906213 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/42.prim_present_test.3852821775 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/43.prim_present_test.2810397714 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/44.prim_present_test.2503034998 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/45.prim_present_test.3160804374 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/46.prim_present_test.2973856291 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/47.prim_present_test.429510899 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/48.prim_present_test.1709119778 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/49.prim_present_test.743925336 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/5.prim_present_test.2974482090 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/6.prim_present_test.2288790219 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/7.prim_present_test.1033636435 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/8.prim_present_test.2042815257 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/9.prim_present_test.1661338083 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/17.prim_present_test.329030836 | Sep 11 12:39:08 AM UTC 24 | Sep 11 12:39:40 AM UTC 24 | 3878720000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/20.prim_present_test.3696783603 | Sep 11 12:39:13 AM UTC 24 | Sep 11 12:39:41 AM UTC 24 | 3379000000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/13.prim_present_test.2083376895 | Sep 11 12:39:07 AM UTC 24 | Sep 11 12:39:43 AM UTC 24 | 4380920000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/18.prim_present_test.2994172432 | Sep 11 12:39:08 AM UTC 24 | Sep 11 12:39:53 AM UTC 24 | 5406400000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/8.prim_present_test.2042815257 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:39:59 AM UTC 24 | 6348800000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/1.prim_present_test.4025722426 | Sep 11 12:39:05 AM UTC 24 | Sep 11 12:40:00 AM UTC 24 | 6703440000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/12.prim_present_test.537928957 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:40:02 AM UTC 24 | 6668100000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/23.prim_present_test.2731772005 | Sep 11 12:39:31 AM UTC 24 | Sep 11 12:40:03 AM UTC 24 | 3601580000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/4.prim_present_test.2185309109 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:40:04 AM UTC 24 | 6944000000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/31.prim_present_test.4286283048 | Sep 11 12:39:39 AM UTC 24 | Sep 11 12:40:11 AM UTC 24 | 3736120000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/22.prim_present_test.3094356678 | Sep 11 12:39:31 AM UTC 24 | Sep 11 12:40:16 AM UTC 24 | 5467780000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/6.prim_present_test.2288790219 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:40:16 AM UTC 24 | 8789740000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/37.prim_present_test.2020078760 | Sep 11 12:39:43 AM UTC 24 | Sep 11 12:40:18 AM UTC 24 | 4309000000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/7.prim_present_test.1033636435 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:40:22 AM UTC 24 | 9670140000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/10.prim_present_test.1267207440 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:40:23 AM UTC 24 | 9805300000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/30.prim_present_test.3060032610 | Sep 11 12:39:39 AM UTC 24 | Sep 11 12:40:23 AM UTC 24 | 5589300000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/42.prim_present_test.3852821775 | Sep 11 12:40:00 AM UTC 24 | Sep 11 12:40:24 AM UTC 24 | 3303980000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/34.prim_present_test.3795105462 | Sep 11 12:39:42 AM UTC 24 | Sep 11 12:40:28 AM UTC 24 | 5866440000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/46.prim_present_test.2973856291 | Sep 11 12:40:02 AM UTC 24 | Sep 11 12:40:29 AM UTC 24 | 3917780000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/36.prim_present_test.3708324426 | Sep 11 12:39:42 AM UTC 24 | Sep 11 12:40:32 AM UTC 24 | 6488300000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/16.prim_present_test.4096694905 | Sep 11 12:39:08 AM UTC 24 | Sep 11 12:40:32 AM UTC 24 | 10895880000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/44.prim_present_test.2503034998 | Sep 11 12:40:00 AM UTC 24 | Sep 11 12:40:34 AM UTC 24 | 4787020000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/11.prim_present_test.2119787337 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:40:35 AM UTC 24 | 11533240000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/21.prim_present_test.4116073184 | Sep 11 12:39:30 AM UTC 24 | Sep 11 12:40:37 AM UTC 24 | 8650860000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/2.prim_present_test.3654896077 | Sep 11 12:39:05 AM UTC 24 | Sep 11 12:40:39 AM UTC 24 | 12411160000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/0.prim_present_test.1912534479 | Sep 11 12:39:05 AM UTC 24 | Sep 11 12:40:39 AM UTC 24 | 12455800000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/43.prim_present_test.2810397714 | Sep 11 12:40:00 AM UTC 24 | Sep 11 12:40:40 AM UTC 24 | 5638900000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/29.prim_present_test.2247711925 | Sep 11 12:39:38 AM UTC 24 | Sep 11 12:40:41 AM UTC 24 | 8461760000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/14.prim_present_test.2127958742 | Sep 11 12:39:08 AM UTC 24 | Sep 11 12:40:42 AM UTC 24 | 12276620000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/48.prim_present_test.1709119778 | Sep 11 12:40:02 AM UTC 24 | Sep 11 12:40:45 AM UTC 24 | 6279360000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/3.prim_present_test.3170117906 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:40:47 AM UTC 24 | 13401300000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/27.prim_present_test.2508418643 | Sep 11 12:39:37 AM UTC 24 | Sep 11 12:40:48 AM UTC 24 | 9620540000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/28.prim_present_test.2118423529 | Sep 11 12:39:37 AM UTC 24 | Sep 11 12:40:49 AM UTC 24 | 9650300000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/24.prim_present_test.1713921795 | Sep 11 12:39:32 AM UTC 24 | Sep 11 12:40:49 AM UTC 24 | 10264100000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/32.prim_present_test.1638672712 | Sep 11 12:39:41 AM UTC 24 | Sep 11 12:40:52 AM UTC 24 | 9619920000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/41.prim_present_test.1478906213 | Sep 11 12:39:59 AM UTC 24 | Sep 11 12:40:55 AM UTC 24 | 7979400000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/5.prim_present_test.2974482090 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:40:58 AM UTC 24 | 15132960000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/39.prim_present_test.3644350516 | Sep 11 12:39:51 AM UTC 24 | Sep 11 12:40:59 AM UTC 24 | 9427720000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/49.prim_present_test.743925336 | Sep 11 12:40:02 AM UTC 24 | Sep 11 12:41:00 AM UTC 24 | 8377440000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/19.prim_present_test.3957719063 | Sep 11 12:39:08 AM UTC 24 | Sep 11 12:41:00 AM UTC 24 | 15020740000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/9.prim_present_test.1661338083 | Sep 11 12:39:06 AM UTC 24 | Sep 11 12:41:00 AM UTC 24 | 15260680000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/25.prim_present_test.3855861051 | Sep 11 12:39:33 AM UTC 24 | Sep 11 12:41:03 AM UTC 24 | 12189200000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/33.prim_present_test.3064434098 | Sep 11 12:39:41 AM UTC 24 | Sep 11 12:41:03 AM UTC 24 | 11351580000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/15.prim_present_test.3931600615 | Sep 11 12:39:08 AM UTC 24 | Sep 11 12:41:04 AM UTC 24 | 15495660000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/26.prim_present_test.1788613466 | Sep 11 12:39:37 AM UTC 24 | Sep 11 12:41:14 AM UTC 24 | 13435400000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/35.prim_present_test.762587699 | Sep 11 12:39:42 AM UTC 24 | Sep 11 12:41:14 AM UTC 24 | 12900960000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/47.prim_present_test.429510899 | Sep 11 12:40:02 AM UTC 24 | Sep 11 12:41:32 AM UTC 24 | 13124780000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/45.prim_present_test.3160804374 | Sep 11 12:40:02 AM UTC 24 | Sep 11 12:41:33 AM UTC 24 | 13232660000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/38.prim_present_test.653863812 | Sep 11 12:39:50 AM UTC 24 | Sep 11 12:41:37 AM UTC 24 | 15099480000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/40.prim_present_test.1487051116 | Sep 11 12:39:54 AM UTC 24 | Sep 11 12:41:40 AM UTC 24 | 15029420000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/1.prim_present_test.4025722426 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6703440000 ps |
| CPU time | 13.27 seconds |
| Started | Sep 11 12:39:05 AM UTC 24 |
| Finished | Sep 11 12:40:00 AM UTC 24 |
| Peak memory | 151428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025722426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4025722426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/0.prim_present_test.1912534479 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12455800000 ps |
| CPU time | 25.76 seconds |
| Started | Sep 11 12:39:05 AM UTC 24 |
| Finished | Sep 11 12:40:39 AM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912534479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1912534479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/10.prim_present_test.1267207440 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9805300000 ps |
| CPU time | 20.35 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:40:23 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267207440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1267207440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/11.prim_present_test.2119787337 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11533240000 ps |
| CPU time | 23.92 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:40:35 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119787337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2119787337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/12.prim_present_test.537928957 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6668100000 ps |
| CPU time | 13.34 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:40:02 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537928957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.537928957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/13.prim_present_test.2083376895 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4380920000 ps |
| CPU time | 8.84 seconds |
| Started | Sep 11 12:39:07 AM UTC 24 |
| Finished | Sep 11 12:39:43 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083376895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2083376895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/14.prim_present_test.2127958742 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 12276620000 ps |
| CPU time | 26.09 seconds |
| Started | Sep 11 12:39:08 AM UTC 24 |
| Finished | Sep 11 12:40:42 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127958742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2127958742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/15.prim_present_test.3931600615 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 15495660000 ps |
| CPU time | 32.77 seconds |
| Started | Sep 11 12:39:08 AM UTC 24 |
| Finished | Sep 11 12:41:04 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931600615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3931600615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/16.prim_present_test.4096694905 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10895880000 ps |
| CPU time | 22.98 seconds |
| Started | Sep 11 12:39:08 AM UTC 24 |
| Finished | Sep 11 12:40:32 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096694905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.4096694905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/17.prim_present_test.329030836 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3878720000 ps |
| CPU time | 7.78 seconds |
| Started | Sep 11 12:39:08 AM UTC 24 |
| Finished | Sep 11 12:39:40 AM UTC 24 |
| Peak memory | 151900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329030836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.329030836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/18.prim_present_test.2994172432 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5406400000 ps |
| CPU time | 10.39 seconds |
| Started | Sep 11 12:39:08 AM UTC 24 |
| Finished | Sep 11 12:39:53 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994172432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2994172432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/19.prim_present_test.3957719063 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15020740000 ps |
| CPU time | 32.34 seconds |
| Started | Sep 11 12:39:08 AM UTC 24 |
| Finished | Sep 11 12:41:00 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957719063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3957719063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/2.prim_present_test.3654896077 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12411160000 ps |
| CPU time | 26.08 seconds |
| Started | Sep 11 12:39:05 AM UTC 24 |
| Finished | Sep 11 12:40:39 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654896077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3654896077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/20.prim_present_test.3696783603 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3379000000 ps |
| CPU time | 6.95 seconds |
| Started | Sep 11 12:39:13 AM UTC 24 |
| Finished | Sep 11 12:39:41 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696783603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3696783603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/21.prim_present_test.4116073184 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8650860000 ps |
| CPU time | 18.92 seconds |
| Started | Sep 11 12:39:30 AM UTC 24 |
| Finished | Sep 11 12:40:37 AM UTC 24 |
| Peak memory | 152136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116073184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4116073184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/22.prim_present_test.3094356678 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5467780000 ps |
| CPU time | 11.51 seconds |
| Started | Sep 11 12:39:31 AM UTC 24 |
| Finished | Sep 11 12:40:16 AM UTC 24 |
| Peak memory | 152108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094356678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3094356678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/23.prim_present_test.2731772005 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3601580000 ps |
| CPU time | 7.41 seconds |
| Started | Sep 11 12:39:31 AM UTC 24 |
| Finished | Sep 11 12:40:03 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731772005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2731772005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/24.prim_present_test.1713921795 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10264100000 ps |
| CPU time | 22.52 seconds |
| Started | Sep 11 12:39:32 AM UTC 24 |
| Finished | Sep 11 12:40:49 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713921795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1713921795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/25.prim_present_test.3855861051 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12189200000 ps |
| CPU time | 26.45 seconds |
| Started | Sep 11 12:39:33 AM UTC 24 |
| Finished | Sep 11 12:41:03 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855861051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3855861051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/26.prim_present_test.1788613466 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13435400000 ps |
| CPU time | 29.84 seconds |
| Started | Sep 11 12:39:37 AM UTC 24 |
| Finished | Sep 11 12:41:14 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788613466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1788613466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/27.prim_present_test.2508418643 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9620540000 ps |
| CPU time | 21.46 seconds |
| Started | Sep 11 12:39:37 AM UTC 24 |
| Finished | Sep 11 12:40:48 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508418643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2508418643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/28.prim_present_test.2118423529 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9650300000 ps |
| CPU time | 21.38 seconds |
| Started | Sep 11 12:39:37 AM UTC 24 |
| Finished | Sep 11 12:40:49 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118423529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2118423529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/29.prim_present_test.2247711925 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8461760000 ps |
| CPU time | 18.74 seconds |
| Started | Sep 11 12:39:38 AM UTC 24 |
| Finished | Sep 11 12:40:41 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247711925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2247711925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/3.prim_present_test.3170117906 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13401300000 ps |
| CPU time | 28.47 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:40:47 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170117906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3170117906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/30.prim_present_test.3060032610 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5589300000 ps |
| CPU time | 12.16 seconds |
| Started | Sep 11 12:39:39 AM UTC 24 |
| Finished | Sep 11 12:40:23 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060032610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3060032610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/31.prim_present_test.4286283048 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3736120000 ps |
| CPU time | 8.17 seconds |
| Started | Sep 11 12:39:39 AM UTC 24 |
| Finished | Sep 11 12:40:11 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286283048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4286283048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/32.prim_present_test.1638672712 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9619920000 ps |
| CPU time | 21.52 seconds |
| Started | Sep 11 12:39:41 AM UTC 24 |
| Finished | Sep 11 12:40:52 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638672712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1638672712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/33.prim_present_test.3064434098 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11351580000 ps |
| CPU time | 25.42 seconds |
| Started | Sep 11 12:39:41 AM UTC 24 |
| Finished | Sep 11 12:41:03 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064434098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3064434098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/34.prim_present_test.3795105462 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5866440000 ps |
| CPU time | 12.86 seconds |
| Started | Sep 11 12:39:42 AM UTC 24 |
| Finished | Sep 11 12:40:28 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795105462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3795105462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/35.prim_present_test.762587699 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12900960000 ps |
| CPU time | 28.93 seconds |
| Started | Sep 11 12:39:42 AM UTC 24 |
| Finished | Sep 11 12:41:14 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762587699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.762587699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/36.prim_present_test.3708324426 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6488300000 ps |
| CPU time | 14.37 seconds |
| Started | Sep 11 12:39:42 AM UTC 24 |
| Finished | Sep 11 12:40:32 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708324426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3708324426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/37.prim_present_test.2020078760 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4309000000 ps |
| CPU time | 9.54 seconds |
| Started | Sep 11 12:39:43 AM UTC 24 |
| Finished | Sep 11 12:40:18 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020078760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2020078760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/38.prim_present_test.653863812 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15099480000 ps |
| CPU time | 33.65 seconds |
| Started | Sep 11 12:39:50 AM UTC 24 |
| Finished | Sep 11 12:41:37 AM UTC 24 |
| Peak memory | 154784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653863812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.653863812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/39.prim_present_test.3644350516 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9427720000 ps |
| CPU time | 21.1 seconds |
| Started | Sep 11 12:39:51 AM UTC 24 |
| Finished | Sep 11 12:40:59 AM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644350516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3644350516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/4.prim_present_test.2185309109 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6944000000 ps |
| CPU time | 13.83 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:40:04 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185309109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2185309109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/40.prim_present_test.1487051116 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15029420000 ps |
| CPU time | 33.7 seconds |
| Started | Sep 11 12:39:54 AM UTC 24 |
| Finished | Sep 11 12:41:40 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487051116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1487051116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/41.prim_present_test.1478906213 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7979400000 ps |
| CPU time | 18.15 seconds |
| Started | Sep 11 12:39:59 AM UTC 24 |
| Finished | Sep 11 12:40:55 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478906213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1478906213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/42.prim_present_test.3852821775 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3303980000 ps |
| CPU time | 7.83 seconds |
| Started | Sep 11 12:40:00 AM UTC 24 |
| Finished | Sep 11 12:40:24 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852821775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3852821775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/43.prim_present_test.2810397714 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5638900000 ps |
| CPU time | 12.91 seconds |
| Started | Sep 11 12:40:00 AM UTC 24 |
| Finished | Sep 11 12:40:40 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810397714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2810397714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/44.prim_present_test.2503034998 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4787020000 ps |
| CPU time | 10.98 seconds |
| Started | Sep 11 12:40:00 AM UTC 24 |
| Finished | Sep 11 12:40:34 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503034998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2503034998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/45.prim_present_test.3160804374 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13232660000 ps |
| CPU time | 29.97 seconds |
| Started | Sep 11 12:40:02 AM UTC 24 |
| Finished | Sep 11 12:41:33 AM UTC 24 |
| Peak memory | 151824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160804374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3160804374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/46.prim_present_test.2973856291 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3917780000 ps |
| CPU time | 9.26 seconds |
| Started | Sep 11 12:40:02 AM UTC 24 |
| Finished | Sep 11 12:40:29 AM UTC 24 |
| Peak memory | 151800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973856291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2973856291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/47.prim_present_test.429510899 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13124780000 ps |
| CPU time | 29.54 seconds |
| Started | Sep 11 12:40:02 AM UTC 24 |
| Finished | Sep 11 12:41:32 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429510899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.429510899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/48.prim_present_test.1709119778 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6279360000 ps |
| CPU time | 14.54 seconds |
| Started | Sep 11 12:40:02 AM UTC 24 |
| Finished | Sep 11 12:40:45 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709119778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1709119778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/49.prim_present_test.743925336 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8377440000 ps |
| CPU time | 18.99 seconds |
| Started | Sep 11 12:40:02 AM UTC 24 |
| Finished | Sep 11 12:41:00 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743925336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.743925336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/5.prim_present_test.2974482090 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 15132960000 ps |
| CPU time | 32.32 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:40:58 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974482090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2974482090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/6.prim_present_test.2288790219 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8789740000 ps |
| CPU time | 17.68 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:40:16 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288790219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2288790219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/7.prim_present_test.1033636435 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9670140000 ps |
| CPU time | 19.33 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:40:22 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033636435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1033636435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/8.prim_present_test.2042815257 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 6348800000 ps |
| CPU time | 12.62 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:39:59 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042815257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2042815257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default/9.prim_present_test.1661338083 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 15260680000 ps |
| CPU time | 31.72 seconds |
| Started | Sep 11 12:39:06 AM UTC 24 |
| Finished | Sep 11 12:41:00 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661338083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1661338083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |