| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/0.prim_present_test.3703666320 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/1.prim_present_test.498242397 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/10.prim_present_test.3453425940 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/11.prim_present_test.357447481 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/12.prim_present_test.3561948227 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/13.prim_present_test.1916200181 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/14.prim_present_test.1571094514 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/15.prim_present_test.2603568295 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/16.prim_present_test.1410623680 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/17.prim_present_test.4259720173 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/18.prim_present_test.2616679391 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/19.prim_present_test.708385617 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/2.prim_present_test.4198485021 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/20.prim_present_test.2328252657 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/21.prim_present_test.1673845683 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/22.prim_present_test.836252467 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/23.prim_present_test.754640360 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/24.prim_present_test.1730592772 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/25.prim_present_test.503302455 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/26.prim_present_test.3175663212 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/27.prim_present_test.2910635868 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/28.prim_present_test.4186968721 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/29.prim_present_test.4224743821 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/3.prim_present_test.2396710770 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/30.prim_present_test.1802197321 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/31.prim_present_test.3583040689 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/32.prim_present_test.1693218924 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/33.prim_present_test.1126828185 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/34.prim_present_test.3828187227 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/35.prim_present_test.697496998 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/36.prim_present_test.1332197139 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/37.prim_present_test.963293191 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/38.prim_present_test.1159387025 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/39.prim_present_test.1514651317 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/4.prim_present_test.2660558256 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/40.prim_present_test.1531976636 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/41.prim_present_test.2668553937 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/42.prim_present_test.3012026834 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/43.prim_present_test.953921190 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/44.prim_present_test.631592715 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/45.prim_present_test.3097254528 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/46.prim_present_test.359040224 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/47.prim_present_test.523407043 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/48.prim_present_test.1398325556 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/49.prim_present_test.3093279039 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/5.prim_present_test.1191904107 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/6.prim_present_test.2030987996 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/7.prim_present_test.3902448111 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/8.prim_present_test.2602977019 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/9.prim_present_test.712146306 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/8.prim_present_test.2602977019 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:36:30 AM UTC 24 | 3128520000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/11.prim_present_test.357447481 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:36:31 AM UTC 24 | 3330640000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/0.prim_present_test.3703666320 | Sep 18 03:36:03 AM UTC 24 | Sep 18 03:36:32 AM UTC 24 | 3819200000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/10.prim_present_test.3453425940 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:36:35 AM UTC 24 | 3946920000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/18.prim_present_test.2616679391 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:36:40 AM UTC 24 | 4584900000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/37.prim_present_test.963293191 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:36:41 AM UTC 24 | 4176940000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/31.prim_present_test.3583040689 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:36:43 AM UTC 24 | 4402620000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/30.prim_present_test.1802197321 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:36:46 AM UTC 24 | 4916600000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/42.prim_present_test.3012026834 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:36:48 AM UTC 24 | 5198080000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/1.prim_present_test.498242397 | Sep 18 03:36:04 AM UTC 24 | Sep 18 03:36:49 AM UTC 24 | 6131180000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/5.prim_present_test.1191904107 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:36:53 AM UTC 24 | 6577580000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/12.prim_present_test.3561948227 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:36:56 AM UTC 24 | 7109540000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/35.prim_present_test.697496998 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:36:57 AM UTC 24 | 5405780000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/45.prim_present_test.3097254528 | Sep 18 03:36:10 AM UTC 24 | Sep 18 03:36:59 AM UTC 24 | 5723840000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/33.prim_present_test.1126828185 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:00 AM UTC 24 | 5794520000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/44.prim_present_test.631592715 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:04 AM UTC 24 | 7670020000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/46.prim_present_test.359040224 | Sep 18 03:36:10 AM UTC 24 | Sep 18 03:37:11 AM UTC 24 | 7547880000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/28.prim_present_test.4186968721 | Sep 18 03:36:08 AM UTC 24 | Sep 18 03:37:13 AM UTC 24 | 9019760000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/13.prim_present_test.1916200181 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:13 AM UTC 24 | 9431440000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/48.prim_present_test.1398325556 | Sep 18 03:36:10 AM UTC 24 | Sep 18 03:37:16 AM UTC 24 | 8038300000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/27.prim_present_test.2910635868 | Sep 18 03:36:08 AM UTC 24 | Sep 18 03:37:18 AM UTC 24 | 9840020000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/3.prim_present_test.2396710770 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:19 AM UTC 24 | 10248600000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/20.prim_present_test.2328252657 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:21 AM UTC 24 | 10588980000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/26.prim_present_test.3175663212 | Sep 18 03:36:07 AM UTC 24 | Sep 18 03:37:23 AM UTC 24 | 10983920000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/25.prim_present_test.503302455 | Sep 18 03:36:07 AM UTC 24 | Sep 18 03:37:24 AM UTC 24 | 11031660000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/15.prim_present_test.2603568295 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:26 AM UTC 24 | 11313140000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/16.prim_present_test.1410623680 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:26 AM UTC 24 | 11330500000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/29.prim_present_test.4224743821 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:26 AM UTC 24 | 10760720000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/7.prim_present_test.3902448111 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:27 AM UTC 24 | 11473720000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/49.prim_present_test.3093279039 | Sep 18 03:36:15 AM UTC 24 | Sep 18 03:37:28 AM UTC 24 | 9586440000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/34.prim_present_test.3828187227 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:30 AM UTC 24 | 10267820000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/23.prim_present_test.754640360 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:30 AM UTC 24 | 12197260000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/22.prim_present_test.836252467 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:31 AM UTC 24 | 12231360000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/19.prim_present_test.708385617 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:31 AM UTC 24 | 12012500000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/14.prim_present_test.1571094514 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:31 AM UTC 24 | 12377680000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/40.prim_present_test.1531976636 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:32 AM UTC 24 | 11706220000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/38.prim_present_test.1159387025 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:34 AM UTC 24 | 12047840000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/9.prim_present_test.712146306 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:35 AM UTC 24 | 12663500000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/21.prim_present_test.1673845683 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:35 AM UTC 24 | 12987760000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/39.prim_present_test.1514651317 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:36 AM UTC 24 | 12670320000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/24.prim_present_test.1730592772 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:37 AM UTC 24 | 13250020000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/43.prim_present_test.953921190 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:43 AM UTC 24 | 13615820000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/47.prim_present_test.523407043 | Sep 18 03:36:10 AM UTC 24 | Sep 18 03:37:44 AM UTC 24 | 12571740000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/36.prim_present_test.1332197139 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:44 AM UTC 24 | 13903500000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/2.prim_present_test.4198485021 | Sep 18 03:36:04 AM UTC 24 | Sep 18 03:37:45 AM UTC 24 | 14517300000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/6.prim_present_test.2030987996 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:46 AM UTC 24 | 14441040000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/4.prim_present_test.2660558256 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:48 AM UTC 24 | 14990360000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/17.prim_present_test.4259720173 | Sep 18 03:36:05 AM UTC 24 | Sep 18 03:37:49 AM UTC 24 | 14788860000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/41.prim_present_test.2668553937 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:37:53 AM UTC 24 | 15274320000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/32.prim_present_test.1693218924 | Sep 18 03:36:09 AM UTC 24 | Sep 18 03:38:00 AM UTC 24 | 14676640000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/0.prim_present_test.3703666320 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3819200000 ps |
| CPU time | 8.14 seconds |
| Started | Sep 18 03:36:03 AM UTC 24 |
| Finished | Sep 18 03:36:32 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703666320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3703666320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/1.prim_present_test.498242397 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6131180000 ps |
| CPU time | 13.41 seconds |
| Started | Sep 18 03:36:04 AM UTC 24 |
| Finished | Sep 18 03:36:49 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498242397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.498242397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/10.prim_present_test.3453425940 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3946920000 ps |
| CPU time | 8.65 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:36:35 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453425940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3453425940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/11.prim_present_test.357447481 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3330640000 ps |
| CPU time | 7.3 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:36:31 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357447481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.357447481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/12.prim_present_test.3561948227 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7109540000 ps |
| CPU time | 15.73 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:36:56 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561948227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3561948227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/13.prim_present_test.1916200181 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9431440000 ps |
| CPU time | 20.92 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:13 AM UTC 24 |
| Peak memory | 152124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916200181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1916200181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/14.prim_present_test.1571094514 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12377680000 ps |
| CPU time | 27.38 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:31 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571094514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1571094514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/15.prim_present_test.2603568295 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11313140000 ps |
| CPU time | 24.97 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:26 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603568295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2603568295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/16.prim_present_test.1410623680 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 11330500000 ps |
| CPU time | 25.1 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:26 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410623680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1410623680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/17.prim_present_test.4259720173 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14788860000 ps |
| CPU time | 32.71 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:49 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259720173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4259720173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/18.prim_present_test.2616679391 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4584900000 ps |
| CPU time | 10.1 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:36:40 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616679391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2616679391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/19.prim_present_test.708385617 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12012500000 ps |
| CPU time | 26.62 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:31 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708385617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.708385617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/2.prim_present_test.4198485021 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14517300000 ps |
| CPU time | 31.92 seconds |
| Started | Sep 18 03:36:04 AM UTC 24 |
| Finished | Sep 18 03:37:45 AM UTC 24 |
| Peak memory | 154784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198485021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4198485021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/20.prim_present_test.2328252657 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10588980000 ps |
| CPU time | 23.4 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:21 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328252657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2328252657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/21.prim_present_test.1673845683 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12987760000 ps |
| CPU time | 28.73 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:35 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673845683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1673845683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/22.prim_present_test.836252467 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12231360000 ps |
| CPU time | 27.07 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:31 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836252467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.836252467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/23.prim_present_test.754640360 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12197260000 ps |
| CPU time | 27.07 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:30 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754640360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.754640360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/24.prim_present_test.1730592772 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13250020000 ps |
| CPU time | 29.26 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:37 AM UTC 24 |
| Peak memory | 152028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730592772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1730592772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/25.prim_present_test.503302455 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11031660000 ps |
| CPU time | 24.5 seconds |
| Started | Sep 18 03:36:07 AM UTC 24 |
| Finished | Sep 18 03:37:24 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503302455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.503302455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/26.prim_present_test.3175663212 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10983920000 ps |
| CPU time | 24.45 seconds |
| Started | Sep 18 03:36:07 AM UTC 24 |
| Finished | Sep 18 03:37:23 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175663212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3175663212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/27.prim_present_test.2910635868 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9840020000 ps |
| CPU time | 21.87 seconds |
| Started | Sep 18 03:36:08 AM UTC 24 |
| Finished | Sep 18 03:37:18 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910635868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2910635868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/28.prim_present_test.4186968721 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9019760000 ps |
| CPU time | 20.14 seconds |
| Started | Sep 18 03:36:08 AM UTC 24 |
| Finished | Sep 18 03:37:13 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186968721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.4186968721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/29.prim_present_test.4224743821 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10760720000 ps |
| CPU time | 24.03 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:26 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224743821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4224743821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/3.prim_present_test.2396710770 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10248600000 ps |
| CPU time | 22.7 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:19 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396710770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2396710770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/30.prim_present_test.1802197321 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4916600000 ps |
| CPU time | 11.06 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:36:46 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802197321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1802197321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/31.prim_present_test.3583040689 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4402620000 ps |
| CPU time | 9.86 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:36:43 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583040689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3583040689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/32.prim_present_test.1693218924 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14676640000 ps |
| CPU time | 32.99 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:38:00 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693218924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1693218924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/33.prim_present_test.1126828185 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5794520000 ps |
| CPU time | 13.21 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:00 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126828185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1126828185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/34.prim_present_test.3828187227 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10267820000 ps |
| CPU time | 23.15 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:30 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828187227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3828187227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/35.prim_present_test.697496998 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5405780000 ps |
| CPU time | 12.3 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:36:57 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697496998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.697496998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/36.prim_present_test.1332197139 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13903500000 ps |
| CPU time | 31.02 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:44 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332197139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1332197139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/37.prim_present_test.963293191 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4176940000 ps |
| CPU time | 9.45 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:36:41 AM UTC 24 |
| Peak memory | 152088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963293191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.963293191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/38.prim_present_test.1159387025 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12047840000 ps |
| CPU time | 26.94 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:34 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159387025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1159387025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/39.prim_present_test.1514651317 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12670320000 ps |
| CPU time | 28.17 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:36 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514651317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1514651317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/4.prim_present_test.2660558256 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14990360000 ps |
| CPU time | 33.21 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:48 AM UTC 24 |
| Peak memory | 154784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660558256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2660558256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/40.prim_present_test.1531976636 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11706220000 ps |
| CPU time | 26.15 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:32 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531976636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1531976636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/41.prim_present_test.2668553937 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15274320000 ps |
| CPU time | 34.06 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:53 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668553937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2668553937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/42.prim_present_test.3012026834 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5198080000 ps |
| CPU time | 11.66 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:36:48 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012026834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3012026834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/43.prim_present_test.953921190 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13615820000 ps |
| CPU time | 30.31 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:43 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953921190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.953921190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/44.prim_present_test.631592715 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7670020000 ps |
| CPU time | 17.14 seconds |
| Started | Sep 18 03:36:09 AM UTC 24 |
| Finished | Sep 18 03:37:04 AM UTC 24 |
| Peak memory | 152152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631592715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.631592715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/45.prim_present_test.3097254528 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5723840000 ps |
| CPU time | 12.98 seconds |
| Started | Sep 18 03:36:10 AM UTC 24 |
| Finished | Sep 18 03:36:59 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097254528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3097254528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/46.prim_present_test.359040224 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7547880000 ps |
| CPU time | 17.05 seconds |
| Started | Sep 18 03:36:10 AM UTC 24 |
| Finished | Sep 18 03:37:11 AM UTC 24 |
| Peak memory | 152156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359040224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.359040224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/47.prim_present_test.523407043 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12571740000 ps |
| CPU time | 28.14 seconds |
| Started | Sep 18 03:36:10 AM UTC 24 |
| Finished | Sep 18 03:37:44 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523407043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.523407043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/48.prim_present_test.1398325556 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8038300000 ps |
| CPU time | 18.19 seconds |
| Started | Sep 18 03:36:10 AM UTC 24 |
| Finished | Sep 18 03:37:16 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398325556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1398325556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/49.prim_present_test.3093279039 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9586440000 ps |
| CPU time | 21.59 seconds |
| Started | Sep 18 03:36:15 AM UTC 24 |
| Finished | Sep 18 03:37:28 AM UTC 24 |
| Peak memory | 152128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093279039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3093279039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/5.prim_present_test.1191904107 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6577580000 ps |
| CPU time | 14.54 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:36:53 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191904107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1191904107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/6.prim_present_test.2030987996 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14441040000 ps |
| CPU time | 32.01 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:46 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030987996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2030987996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/7.prim_present_test.3902448111 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11473720000 ps |
| CPU time | 25.37 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:27 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902448111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3902448111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/8.prim_present_test.2602977019 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3128520000 ps |
| CPU time | 6.88 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:36:30 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602977019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2602977019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default/9.prim_present_test.712146306 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12663500000 ps |
| CPU time | 28.05 seconds |
| Started | Sep 18 03:36:05 AM UTC 24 |
| Finished | Sep 18 03:37:35 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712146306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.712146306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |