| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/0.prim_present_test.1287738842 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/1.prim_present_test.878614489 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/10.prim_present_test.3570604398 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/11.prim_present_test.3007732071 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/12.prim_present_test.2192250169 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/13.prim_present_test.3104971173 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/14.prim_present_test.3718649946 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/15.prim_present_test.3509017747 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/16.prim_present_test.2597971705 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/17.prim_present_test.2523288082 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/18.prim_present_test.797452371 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/19.prim_present_test.3214065884 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/2.prim_present_test.431249452 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/20.prim_present_test.1533941591 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/21.prim_present_test.2678764104 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/22.prim_present_test.4239327195 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/23.prim_present_test.2249857034 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/24.prim_present_test.1539215396 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/25.prim_present_test.2436342047 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/26.prim_present_test.1613821548 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/27.prim_present_test.2814918067 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/28.prim_present_test.770659166 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/29.prim_present_test.1379117103 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/3.prim_present_test.316205101 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/30.prim_present_test.814737064 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/31.prim_present_test.2436354338 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/32.prim_present_test.2070680414 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/33.prim_present_test.3484358044 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/34.prim_present_test.1370788464 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/35.prim_present_test.3402485785 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/36.prim_present_test.1257649326 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/37.prim_present_test.3744303672 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/38.prim_present_test.1043498504 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/39.prim_present_test.4171692424 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/4.prim_present_test.3296943994 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/40.prim_present_test.2525931910 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/41.prim_present_test.3879569102 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/42.prim_present_test.3496623193 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/43.prim_present_test.2039787411 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/44.prim_present_test.142054868 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/45.prim_present_test.3534952445 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/46.prim_present_test.2652007474 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/47.prim_present_test.649044924 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/48.prim_present_test.2228885381 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/49.prim_present_test.1728311331 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/5.prim_present_test.1709580640 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/6.prim_present_test.35851598 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/7.prim_present_test.86950852 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/8.prim_present_test.21407280 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/9.prim_present_test.3650494713 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/14.prim_present_test.3718649946 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:49:03 AM UTC 24 | 4347440000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/30.prim_present_test.814737064 | Sep 24 03:48:36 AM UTC 24 | Sep 24 03:49:04 AM UTC 24 | 3190520000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/0.prim_present_test.1287738842 | Sep 24 03:48:24 AM UTC 24 | Sep 24 03:49:04 AM UTC 24 | 4669840000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/38.prim_present_test.1043498504 | Sep 24 03:48:39 AM UTC 24 | Sep 24 03:49:08 AM UTC 24 | 3346760000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/22.prim_present_test.4239327195 | Sep 24 03:48:33 AM UTC 24 | Sep 24 03:49:11 AM UTC 24 | 4322640000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/5.prim_present_test.1709580640 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:49:11 AM UTC 24 | 5418180000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/41.prim_present_test.3879569102 | Sep 24 03:48:40 AM UTC 24 | Sep 24 03:49:12 AM UTC 24 | 3812380000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/25.prim_present_test.2436342047 | Sep 24 03:48:34 AM UTC 24 | Sep 24 03:49:12 AM UTC 24 | 4419360000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/3.prim_present_test.316205101 | Sep 24 03:48:24 AM UTC 24 | Sep 24 03:49:14 AM UTC 24 | 5907360000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/20.prim_present_test.1533941591 | Sep 24 03:48:29 AM UTC 24 | Sep 24 03:49:15 AM UTC 24 | 5511800000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/35.prim_present_test.3402485785 | Sep 24 03:48:37 AM UTC 24 | Sep 24 03:49:19 AM UTC 24 | 5182580000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/47.prim_present_test.649044924 | Sep 24 03:48:54 AM UTC 24 | Sep 24 03:49:21 AM UTC 24 | 3453400000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/10.prim_present_test.3570604398 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:49:21 AM UTC 24 | 6874560000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/9.prim_present_test.3650494713 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:49:22 AM UTC 24 | 6967560000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/43.prim_present_test.2039787411 | Sep 24 03:48:40 AM UTC 24 | Sep 24 03:49:22 AM UTC 24 | 5253880000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/19.prim_present_test.3214065884 | Sep 24 03:48:28 AM UTC 24 | Sep 24 03:49:25 AM UTC 24 | 7063660000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/11.prim_present_test.3007732071 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:49:25 AM UTC 24 | 7447440000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/17.prim_present_test.2523288082 | Sep 24 03:48:28 AM UTC 24 | Sep 24 03:49:28 AM UTC 24 | 7575780000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/27.prim_present_test.2814918067 | Sep 24 03:48:35 AM UTC 24 | Sep 24 03:49:29 AM UTC 24 | 6903700000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/23.prim_present_test.2249857034 | Sep 24 03:48:33 AM UTC 24 | Sep 24 03:49:30 AM UTC 24 | 7073580000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/39.prim_present_test.4171692424 | Sep 24 03:48:39 AM UTC 24 | Sep 24 03:49:35 AM UTC 24 | 7348860000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/31.prim_present_test.2436354338 | Sep 24 03:48:36 AM UTC 24 | Sep 24 03:49:36 AM UTC 24 | 7763640000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/7.prim_present_test.86950852 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:49:37 AM UTC 24 | 9151820000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/6.prim_present_test.35851598 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:49:41 AM UTC 24 | 9757560000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/33.prim_present_test.3484358044 | Sep 24 03:48:36 AM UTC 24 | Sep 24 03:49:42 AM UTC 24 | 8694260000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/1.prim_present_test.878614489 | Sep 24 03:48:24 AM UTC 24 | Sep 24 03:49:42 AM UTC 24 | 10165520000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/34.prim_present_test.1370788464 | Sep 24 03:48:36 AM UTC 24 | Sep 24 03:49:42 AM UTC 24 | 8757500000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/40.prim_present_test.2525931910 | Sep 24 03:48:39 AM UTC 24 | Sep 24 03:49:54 AM UTC 24 | 10006180000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/26.prim_present_test.1613821548 | Sep 24 03:48:34 AM UTC 24 | Sep 24 03:49:54 AM UTC 24 | 10618740000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/18.prim_present_test.797452371 | Sep 24 03:48:28 AM UTC 24 | Sep 24 03:49:55 AM UTC 24 | 11438380000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/2.prim_present_test.431249452 | Sep 24 03:48:24 AM UTC 24 | Sep 24 03:49:55 AM UTC 24 | 12028000000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/29.prim_present_test.1379117103 | Sep 24 03:48:35 AM UTC 24 | Sep 24 03:49:57 AM UTC 24 | 10889680000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/16.prim_present_test.2597971705 | Sep 24 03:48:28 AM UTC 24 | Sep 24 03:49:57 AM UTC 24 | 11789920000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/37.prim_present_test.3744303672 | Sep 24 03:48:39 AM UTC 24 | Sep 24 03:50:04 AM UTC 24 | 11540060000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/45.prim_present_test.3534952445 | Sep 24 03:48:43 AM UTC 24 | Sep 24 03:50:05 AM UTC 24 | 11424120000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/8.prim_present_test.21407280 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:50:05 AM UTC 24 | 13291560000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/13.prim_present_test.3104971173 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:50:08 AM UTC 24 | 13844600000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/4.prim_present_test.3296943994 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:50:14 AM UTC 24 | 14563180000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/15.prim_present_test.3509017747 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:50:15 AM UTC 24 | 14740500000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/12.prim_present_test.2192250169 | Sep 24 03:48:25 AM UTC 24 | Sep 24 03:50:15 AM UTC 24 | 14873180000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/42.prim_present_test.3496623193 | Sep 24 03:48:40 AM UTC 24 | Sep 24 03:50:19 AM UTC 24 | 13592880000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/32.prim_present_test.2070680414 | Sep 24 03:48:36 AM UTC 24 | Sep 24 03:50:20 AM UTC 24 | 14335020000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/21.prim_present_test.2678764104 | Sep 24 03:48:31 AM UTC 24 | Sep 24 03:50:20 AM UTC 24 | 14916580000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/49.prim_present_test.1728311331 | Sep 24 03:49:05 AM UTC 24 | Sep 24 03:50:23 AM UTC 24 | 11154420000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/24.prim_present_test.1539215396 | Sep 24 03:48:34 AM UTC 24 | Sep 24 03:50:23 AM UTC 24 | 14748560000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/44.prim_present_test.142054868 | Sep 24 03:48:40 AM UTC 24 | Sep 24 03:50:23 AM UTC 24 | 14408180000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/28.prim_present_test.770659166 | Sep 24 03:48:35 AM UTC 24 | Sep 24 03:50:25 AM UTC 24 | 15170160000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/36.prim_present_test.1257649326 | Sep 24 03:48:38 AM UTC 24 | Sep 24 03:50:28 AM UTC 24 | 15106300000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/46.prim_present_test.2652007474 | Sep 24 03:48:44 AM UTC 24 | Sep 24 03:50:34 AM UTC 24 | 15419400000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/48.prim_present_test.2228885381 | Sep 24 03:49:05 AM UTC 24 | Sep 24 03:50:49 AM UTC 24 | 14937040000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/0.prim_present_test.1287738842 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4669840000 ps |
| CPU time | 11.38 seconds |
| Started | Sep 24 03:48:24 AM UTC 24 |
| Finished | Sep 24 03:49:04 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287738842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1287738842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/1.prim_present_test.878614489 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10165520000 ps |
| CPU time | 24.16 seconds |
| Started | Sep 24 03:48:24 AM UTC 24 |
| Finished | Sep 24 03:49:42 AM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878614489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.878614489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/10.prim_present_test.3570604398 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6874560000 ps |
| CPU time | 16.15 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:49:21 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570604398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3570604398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/11.prim_present_test.3007732071 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7447440000 ps |
| CPU time | 17.86 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:49:25 AM UTC 24 |
| Peak memory | 151872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007732071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3007732071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/12.prim_present_test.2192250169 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14873180000 ps |
| CPU time | 35.42 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:50:15 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192250169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2192250169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/13.prim_present_test.3104971173 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13844600000 ps |
| CPU time | 32.92 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:50:08 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104971173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3104971173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/14.prim_present_test.3718649946 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4347440000 ps |
| CPU time | 10.58 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:49:03 AM UTC 24 |
| Peak memory | 151904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718649946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3718649946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/15.prim_present_test.3509017747 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 14740500000 ps |
| CPU time | 34.51 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:50:15 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509017747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3509017747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/16.prim_present_test.2597971705 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11789920000 ps |
| CPU time | 27.64 seconds |
| Started | Sep 24 03:48:28 AM UTC 24 |
| Finished | Sep 24 03:49:57 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597971705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2597971705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/17.prim_present_test.2523288082 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7575780000 ps |
| CPU time | 18.04 seconds |
| Started | Sep 24 03:48:28 AM UTC 24 |
| Finished | Sep 24 03:49:28 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523288082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2523288082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/18.prim_present_test.797452371 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11438380000 ps |
| CPU time | 26.88 seconds |
| Started | Sep 24 03:48:28 AM UTC 24 |
| Finished | Sep 24 03:49:55 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797452371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.797452371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/19.prim_present_test.3214065884 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7063660000 ps |
| CPU time | 16.87 seconds |
| Started | Sep 24 03:48:28 AM UTC 24 |
| Finished | Sep 24 03:49:25 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214065884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3214065884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/2.prim_present_test.431249452 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12028000000 ps |
| CPU time | 27.94 seconds |
| Started | Sep 24 03:48:24 AM UTC 24 |
| Finished | Sep 24 03:49:55 AM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431249452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.431249452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/20.prim_present_test.1533941591 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5511800000 ps |
| CPU time | 13.48 seconds |
| Started | Sep 24 03:48:29 AM UTC 24 |
| Finished | Sep 24 03:49:15 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533941591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1533941591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/21.prim_present_test.2678764104 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14916580000 ps |
| CPU time | 35.44 seconds |
| Started | Sep 24 03:48:31 AM UTC 24 |
| Finished | Sep 24 03:50:20 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678764104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2678764104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/22.prim_present_test.4239327195 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4322640000 ps |
| CPU time | 10.53 seconds |
| Started | Sep 24 03:48:33 AM UTC 24 |
| Finished | Sep 24 03:49:11 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239327195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.4239327195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/23.prim_present_test.2249857034 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7073580000 ps |
| CPU time | 16.88 seconds |
| Started | Sep 24 03:48:33 AM UTC 24 |
| Finished | Sep 24 03:49:30 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249857034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2249857034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/24.prim_present_test.1539215396 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14748560000 ps |
| CPU time | 34.6 seconds |
| Started | Sep 24 03:48:34 AM UTC 24 |
| Finished | Sep 24 03:50:23 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539215396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1539215396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/25.prim_present_test.2436342047 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4419360000 ps |
| CPU time | 10.72 seconds |
| Started | Sep 24 03:48:34 AM UTC 24 |
| Finished | Sep 24 03:49:12 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436342047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2436342047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/26.prim_present_test.1613821548 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10618740000 ps |
| CPU time | 25.4 seconds |
| Started | Sep 24 03:48:34 AM UTC 24 |
| Finished | Sep 24 03:49:54 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613821548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1613821548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/27.prim_present_test.2814918067 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6903700000 ps |
| CPU time | 16.88 seconds |
| Started | Sep 24 03:48:35 AM UTC 24 |
| Finished | Sep 24 03:49:29 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814918067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2814918067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/28.prim_present_test.770659166 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 15170160000 ps |
| CPU time | 36.05 seconds |
| Started | Sep 24 03:48:35 AM UTC 24 |
| Finished | Sep 24 03:50:25 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770659166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.770659166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/29.prim_present_test.1379117103 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10889680000 ps |
| CPU time | 25.81 seconds |
| Started | Sep 24 03:48:35 AM UTC 24 |
| Finished | Sep 24 03:49:57 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379117103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1379117103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/3.prim_present_test.316205101 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5907360000 ps |
| CPU time | 13.99 seconds |
| Started | Sep 24 03:48:24 AM UTC 24 |
| Finished | Sep 24 03:49:14 AM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316205101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.316205101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/30.prim_present_test.814737064 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3190520000 ps |
| CPU time | 8.11 seconds |
| Started | Sep 24 03:48:36 AM UTC 24 |
| Finished | Sep 24 03:49:04 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814737064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.814737064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/31.prim_present_test.2436354338 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7763640000 ps |
| CPU time | 18.56 seconds |
| Started | Sep 24 03:48:36 AM UTC 24 |
| Finished | Sep 24 03:49:36 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436354338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2436354338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/32.prim_present_test.2070680414 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14335020000 ps |
| CPU time | 34.11 seconds |
| Started | Sep 24 03:48:36 AM UTC 24 |
| Finished | Sep 24 03:50:20 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070680414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2070680414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/33.prim_present_test.3484358044 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8694260000 ps |
| CPU time | 21.02 seconds |
| Started | Sep 24 03:48:36 AM UTC 24 |
| Finished | Sep 24 03:49:42 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484358044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3484358044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/34.prim_present_test.1370788464 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8757500000 ps |
| CPU time | 21.15 seconds |
| Started | Sep 24 03:48:36 AM UTC 24 |
| Finished | Sep 24 03:49:42 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370788464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1370788464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/35.prim_present_test.3402485785 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5182580000 ps |
| CPU time | 12.85 seconds |
| Started | Sep 24 03:48:37 AM UTC 24 |
| Finished | Sep 24 03:49:19 AM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402485785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3402485785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/36.prim_present_test.1257649326 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 15106300000 ps |
| CPU time | 35.5 seconds |
| Started | Sep 24 03:48:38 AM UTC 24 |
| Finished | Sep 24 03:50:28 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257649326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1257649326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/37.prim_present_test.3744303672 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11540060000 ps |
| CPU time | 27.27 seconds |
| Started | Sep 24 03:48:39 AM UTC 24 |
| Finished | Sep 24 03:50:04 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744303672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3744303672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/38.prim_present_test.1043498504 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3346760000 ps |
| CPU time | 8.43 seconds |
| Started | Sep 24 03:48:39 AM UTC 24 |
| Finished | Sep 24 03:49:08 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043498504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1043498504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/39.prim_present_test.4171692424 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7348860000 ps |
| CPU time | 17.69 seconds |
| Started | Sep 24 03:48:39 AM UTC 24 |
| Finished | Sep 24 03:49:35 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171692424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.4171692424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/4.prim_present_test.3296943994 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14563180000 ps |
| CPU time | 34.45 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:50:14 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296943994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3296943994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/40.prim_present_test.2525931910 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10006180000 ps |
| CPU time | 23.83 seconds |
| Started | Sep 24 03:48:39 AM UTC 24 |
| Finished | Sep 24 03:49:54 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525931910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2525931910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/41.prim_present_test.3879569102 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3812380000 ps |
| CPU time | 9.51 seconds |
| Started | Sep 24 03:48:40 AM UTC 24 |
| Finished | Sep 24 03:49:12 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879569102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3879569102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/42.prim_present_test.3496623193 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13592880000 ps |
| CPU time | 31.94 seconds |
| Started | Sep 24 03:48:40 AM UTC 24 |
| Finished | Sep 24 03:50:19 AM UTC 24 |
| Peak memory | 152112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496623193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3496623193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/43.prim_present_test.2039787411 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5253880000 ps |
| CPU time | 12.9 seconds |
| Started | Sep 24 03:48:40 AM UTC 24 |
| Finished | Sep 24 03:49:22 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039787411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2039787411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/44.prim_present_test.142054868 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14408180000 ps |
| CPU time | 34.31 seconds |
| Started | Sep 24 03:48:40 AM UTC 24 |
| Finished | Sep 24 03:50:23 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142054868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.142054868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/45.prim_present_test.3534952445 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11424120000 ps |
| CPU time | 27.28 seconds |
| Started | Sep 24 03:48:43 AM UTC 24 |
| Finished | Sep 24 03:50:05 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534952445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3534952445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/46.prim_present_test.2652007474 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15419400000 ps |
| CPU time | 36.13 seconds |
| Started | Sep 24 03:48:44 AM UTC 24 |
| Finished | Sep 24 03:50:34 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652007474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2652007474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/47.prim_present_test.649044924 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3453400000 ps |
| CPU time | 8.66 seconds |
| Started | Sep 24 03:48:54 AM UTC 24 |
| Finished | Sep 24 03:49:21 AM UTC 24 |
| Peak memory | 152072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649044924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.649044924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/48.prim_present_test.2228885381 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14937040000 ps |
| CPU time | 35.04 seconds |
| Started | Sep 24 03:49:05 AM UTC 24 |
| Finished | Sep 24 03:50:49 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228885381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2228885381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/49.prim_present_test.1728311331 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11154420000 ps |
| CPU time | 26.37 seconds |
| Started | Sep 24 03:49:05 AM UTC 24 |
| Finished | Sep 24 03:50:23 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728311331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1728311331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/5.prim_present_test.1709580640 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5418180000 ps |
| CPU time | 12.99 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:49:11 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709580640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1709580640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/6.prim_present_test.35851598 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9757560000 ps |
| CPU time | 22.78 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:49:41 AM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35851598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 6.prim_present_test.35851598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/7.prim_present_test.86950852 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9151820000 ps |
| CPU time | 21.75 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:49:37 AM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86950852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 7.prim_present_test.86950852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/8.prim_present_test.21407280 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13291560000 ps |
| CPU time | 31.13 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:50:05 AM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21407280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 8.prim_present_test.21407280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default/9.prim_present_test.3650494713 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6967560000 ps |
| CPU time | 16.66 seconds |
| Started | Sep 24 03:48:25 AM UTC 24 |
| Finished | Sep 24 03:49:22 AM UTC 24 |
| Peak memory | 152136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650494713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3650494713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |