| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/11.prim_present_test.3001440303 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/0.prim_present_test.4227312488 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/1.prim_present_test.2920996082 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/10.prim_present_test.1368864223 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/12.prim_present_test.1422076764 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/13.prim_present_test.1742959092 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/14.prim_present_test.2266039732 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/15.prim_present_test.4219553703 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/16.prim_present_test.411868106 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/17.prim_present_test.130603191 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/18.prim_present_test.831830240 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/19.prim_present_test.2646966200 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/2.prim_present_test.2601461732 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/20.prim_present_test.2857488467 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/21.prim_present_test.1845899797 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/22.prim_present_test.3991315241 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/23.prim_present_test.3969054725 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/24.prim_present_test.112801530 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/25.prim_present_test.2112415412 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/26.prim_present_test.3463435796 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/27.prim_present_test.645476928 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/28.prim_present_test.200667724 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/29.prim_present_test.3442492907 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/3.prim_present_test.2162890167 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/30.prim_present_test.4062417923 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/31.prim_present_test.2045286814 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/32.prim_present_test.3544153790 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/33.prim_present_test.2779440149 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/34.prim_present_test.2612782130 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/35.prim_present_test.3233324518 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/36.prim_present_test.1219446166 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/37.prim_present_test.1992154098 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/38.prim_present_test.3401028666 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/39.prim_present_test.261725878 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/4.prim_present_test.2518127732 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/40.prim_present_test.693494141 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/41.prim_present_test.4254563336 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/42.prim_present_test.2156641212 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/43.prim_present_test.2287140966 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/44.prim_present_test.175697969 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/45.prim_present_test.3757998912 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/46.prim_present_test.2540876012 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/47.prim_present_test.1695201534 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/48.prim_present_test.3542419503 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/49.prim_present_test.2842953014 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/5.prim_present_test.3041780093 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/6.prim_present_test.1466302840 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/7.prim_present_test.1604203664 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/8.prim_present_test.326664577 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/9.prim_present_test.3281921949 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/5.prim_present_test.3041780093 | Oct 02 04:20:49 PM UTC 24 | Oct 02 04:21:16 PM UTC 24 | 3372800000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/13.prim_present_test.1742959092 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:21:23 PM UTC 24 | 3806180000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/11.prim_present_test.3001440303 | Oct 02 04:20:51 PM UTC 24 | Oct 02 04:21:23 PM UTC 24 | 3891740000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/44.prim_present_test.175697969 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:21:26 PM UTC 24 | 4013880000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/34.prim_present_test.2612782130 | Oct 02 04:20:53 PM UTC 24 | Oct 02 04:21:29 PM UTC 24 | 4395800000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/46.prim_present_test.2540876012 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:21:34 PM UTC 24 | 5095160000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/22.prim_present_test.3991315241 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:21:35 PM UTC 24 | 5423760000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/27.prim_present_test.645476928 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:21:39 PM UTC 24 | 5999740000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/33.prim_present_test.2779440149 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:21:41 PM UTC 24 | 6265100000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/8.prim_present_test.326664577 | Oct 02 04:20:50 PM UTC 24 | Oct 02 04:21:43 PM UTC 24 | 6691660000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/47.prim_present_test.1695201534 | Oct 02 04:20:56 PM UTC 24 | Oct 02 04:21:50 PM UTC 24 | 6862160000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/28.prim_present_test.200667724 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:21:51 PM UTC 24 | 7486500000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/39.prim_present_test.261725878 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:21:51 PM UTC 24 | 7400940000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/2.prim_present_test.2601461732 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:21:54 PM UTC 24 | 8403480000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/45.prim_present_test.3757998912 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:21:55 PM UTC 24 | 7743180000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/9.prim_present_test.3281921949 | Oct 02 04:20:50 PM UTC 24 | Oct 02 04:21:58 PM UTC 24 | 8645280000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/18.prim_present_test.831830240 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:21:58 PM UTC 24 | 8443160000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/25.prim_present_test.2112415412 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:00 PM UTC 24 | 8613660000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/42.prim_present_test.2156641212 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:22:00 PM UTC 24 | 8445020000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/6.prim_present_test.1466302840 | Oct 02 04:20:49 PM UTC 24 | Oct 02 04:22:01 PM UTC 24 | 9377500000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/29.prim_present_test.3442492907 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:02 PM UTC 24 | 8929240000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/20.prim_present_test.2857488467 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:03 PM UTC 24 | 9031540000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/7.prim_present_test.1604203664 | Oct 02 04:20:49 PM UTC 24 | Oct 02 04:22:03 PM UTC 24 | 9546140000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/23.prim_present_test.3969054725 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:03 PM UTC 24 | 9162360000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/31.prim_present_test.2045286814 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:06 PM UTC 24 | 9412840000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/15.prim_present_test.4219553703 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:08 PM UTC 24 | 9840640000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/12.prim_present_test.1422076764 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:10 PM UTC 24 | 10092360000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/30.prim_present_test.4062417923 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:14 PM UTC 24 | 10494120000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/0.prim_present_test.4227312488 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:22:16 PM UTC 24 | 11191000000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/4.prim_present_test.2518127732 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:22:16 PM UTC 24 | 11182320000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/3.prim_present_test.2162890167 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:22:16 PM UTC 24 | 11232540000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/37.prim_present_test.1992154098 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:22:17 PM UTC 24 | 10656560000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/48.prim_present_test.3542419503 | Oct 02 04:20:58 PM UTC 24 | Oct 02 04:22:19 PM UTC 24 | 10326100000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/21.prim_present_test.1845899797 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:21 PM UTC 24 | 11375760000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/43.prim_present_test.2287140966 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:22:22 PM UTC 24 | 11246800000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/19.prim_present_test.2646966200 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:23 PM UTC 24 | 11561760000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/16.prim_present_test.411868106 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:23 PM UTC 24 | 11653520000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/26.prim_present_test.3463435796 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:24 PM UTC 24 | 11670260000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/38.prim_present_test.3401028666 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:22:26 PM UTC 24 | 11739700000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/49.prim_present_test.2842953014 | Oct 02 04:21:01 PM UTC 24 | Oct 02 04:22:26 PM UTC 24 | 10823960000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/1.prim_present_test.2920996082 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:22:28 PM UTC 24 | 12789360000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/24.prim_present_test.112801530 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:30 PM UTC 24 | 12403100000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/10.prim_present_test.1368864223 | Oct 02 04:20:51 PM UTC 24 | Oct 02 04:22:40 PM UTC 24 | 13685880000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/35.prim_present_test.3233324518 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:22:46 PM UTC 24 | 14136000000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/14.prim_present_test.2266039732 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:46 PM UTC 24 | 14512960000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/17.prim_present_test.130603191 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:48 PM UTC 24 | 14629520000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/36.prim_present_test.1219446166 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:22:48 PM UTC 24 | 14518540000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/32.prim_present_test.3544153790 | Oct 02 04:20:52 PM UTC 24 | Oct 02 04:22:51 PM UTC 24 | 14990360000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/40.prim_present_test.693494141 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:22:56 PM UTC 24 | 15287960000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/41.prim_present_test.4254563336 | Oct 02 04:20:54 PM UTC 24 | Oct 02 04:22:56 PM UTC 24 | 15340040000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/11.prim_present_test.3001440303 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3891740000 ps |
| CPU time | 10.13 seconds |
| Started | Oct 02 04:20:51 PM UTC 24 |
| Finished | Oct 02 04:21:23 PM UTC 24 |
| Peak memory | 152084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001440303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3001440303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/0.prim_present_test.4227312488 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11191000000 ps |
| CPU time | 26.81 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:22:16 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227312488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.4227312488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/1.prim_present_test.2920996082 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12789360000 ps |
| CPU time | 30.63 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:22:28 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920996082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2920996082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/10.prim_present_test.1368864223 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13685880000 ps |
| CPU time | 35.1 seconds |
| Started | Oct 02 04:20:51 PM UTC 24 |
| Finished | Oct 02 04:22:40 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368864223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1368864223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/12.prim_present_test.1422076764 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10092360000 ps |
| CPU time | 24.41 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:10 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422076764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1422076764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/13.prim_present_test.1742959092 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3806180000 ps |
| CPU time | 9.96 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:21:23 PM UTC 24 |
| Peak memory | 152084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742959092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1742959092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/14.prim_present_test.2266039732 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14512960000 ps |
| CPU time | 34.86 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:46 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266039732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2266039732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/15.prim_present_test.4219553703 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9840640000 ps |
| CPU time | 24.64 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:08 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219553703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.4219553703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/16.prim_present_test.411868106 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11653520000 ps |
| CPU time | 28.18 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:23 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411868106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.411868106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/17.prim_present_test.130603191 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14629520000 ps |
| CPU time | 37.92 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:48 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130603191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.130603191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/18.prim_present_test.831830240 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8443160000 ps |
| CPU time | 21.76 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:21:58 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831830240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.831830240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/19.prim_present_test.2646966200 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11561760000 ps |
| CPU time | 28.03 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:23 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646966200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2646966200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/2.prim_present_test.2601461732 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8403480000 ps |
| CPU time | 20.61 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:21:54 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601461732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2601461732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/20.prim_present_test.2857488467 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9031540000 ps |
| CPU time | 23.05 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:03 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857488467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2857488467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/21.prim_present_test.1845899797 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11375760000 ps |
| CPU time | 28.56 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:21 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845899797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1845899797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/22.prim_present_test.3991315241 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5423760000 ps |
| CPU time | 13.99 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:21:35 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991315241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3991315241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/23.prim_present_test.3969054725 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9162360000 ps |
| CPU time | 22.41 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:03 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969054725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3969054725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/24.prim_present_test.112801530 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12403100000 ps |
| CPU time | 31.12 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:30 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112801530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.112801530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/25.prim_present_test.2112415412 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8613660000 ps |
| CPU time | 21.99 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:00 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112415412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2112415412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/26.prim_present_test.3463435796 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11670260000 ps |
| CPU time | 29.37 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:24 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463435796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3463435796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/27.prim_present_test.645476928 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5999740000 ps |
| CPU time | 14.85 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:21:39 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645476928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.645476928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/28.prim_present_test.200667724 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7486500000 ps |
| CPU time | 18.67 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:21:51 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200667724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.200667724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/29.prim_present_test.3442492907 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8929240000 ps |
| CPU time | 21.72 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:02 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442492907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3442492907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/3.prim_present_test.2162890167 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11232540000 ps |
| CPU time | 26.95 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:22:16 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162890167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2162890167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/30.prim_present_test.4062417923 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10494120000 ps |
| CPU time | 25.34 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:14 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062417923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4062417923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/31.prim_present_test.2045286814 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9412840000 ps |
| CPU time | 23.03 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:06 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045286814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2045286814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/32.prim_present_test.3544153790 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14990360000 ps |
| CPU time | 36.45 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:22:51 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544153790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3544153790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/33.prim_present_test.2779440149 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6265100000 ps |
| CPU time | 15.34 seconds |
| Started | Oct 02 04:20:52 PM UTC 24 |
| Finished | Oct 02 04:21:41 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779440149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2779440149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/34.prim_present_test.2612782130 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4395800000 ps |
| CPU time | 11.55 seconds |
| Started | Oct 02 04:20:53 PM UTC 24 |
| Finished | Oct 02 04:21:29 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612782130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2612782130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/35.prim_present_test.3233324518 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14136000000 ps |
| CPU time | 36.95 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:22:46 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233324518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3233324518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/36.prim_present_test.1219446166 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14518540000 ps |
| CPU time | 34.67 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:22:48 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219446166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1219446166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/37.prim_present_test.1992154098 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10656560000 ps |
| CPU time | 26.39 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:22:17 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992154098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1992154098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/38.prim_present_test.3401028666 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11739700000 ps |
| CPU time | 28.65 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:22:26 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401028666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3401028666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/39.prim_present_test.261725878 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7400940000 ps |
| CPU time | 18.3 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:21:51 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261725878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.261725878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/4.prim_present_test.2518127732 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11182320000 ps |
| CPU time | 28.06 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:22:16 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518127732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2518127732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/40.prim_present_test.693494141 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15287960000 ps |
| CPU time | 37.54 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:22:56 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693494141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.693494141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/41.prim_present_test.4254563336 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15340040000 ps |
| CPU time | 37.27 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:22:56 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254563336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.4254563336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/42.prim_present_test.2156641212 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8445020000 ps |
| CPU time | 21.76 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:22:00 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156641212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2156641212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/43.prim_present_test.2287140966 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11246800000 ps |
| CPU time | 28.37 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:22:22 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287140966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2287140966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/44.prim_present_test.175697969 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4013880000 ps |
| CPU time | 10.58 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:21:26 PM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175697969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.175697969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/45.prim_present_test.3757998912 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7743180000 ps |
| CPU time | 20.05 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:21:55 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757998912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3757998912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/46.prim_present_test.2540876012 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5095160000 ps |
| CPU time | 13.32 seconds |
| Started | Oct 02 04:20:54 PM UTC 24 |
| Finished | Oct 02 04:21:34 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540876012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2540876012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/47.prim_present_test.1695201534 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6862160000 ps |
| CPU time | 17.82 seconds |
| Started | Oct 02 04:20:56 PM UTC 24 |
| Finished | Oct 02 04:21:50 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695201534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1695201534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/48.prim_present_test.3542419503 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10326100000 ps |
| CPU time | 25.38 seconds |
| Started | Oct 02 04:20:58 PM UTC 24 |
| Finished | Oct 02 04:22:19 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542419503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3542419503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/49.prim_present_test.2842953014 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10823960000 ps |
| CPU time | 26.27 seconds |
| Started | Oct 02 04:21:01 PM UTC 24 |
| Finished | Oct 02 04:22:26 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842953014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2842953014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/5.prim_present_test.3041780093 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3372800000 ps |
| CPU time | 8.22 seconds |
| Started | Oct 02 04:20:49 PM UTC 24 |
| Finished | Oct 02 04:21:16 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041780093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3041780093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/6.prim_present_test.1466302840 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9377500000 ps |
| CPU time | 22.5 seconds |
| Started | Oct 02 04:20:49 PM UTC 24 |
| Finished | Oct 02 04:22:01 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466302840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1466302840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/7.prim_present_test.1604203664 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9546140000 ps |
| CPU time | 24.17 seconds |
| Started | Oct 02 04:20:49 PM UTC 24 |
| Finished | Oct 02 04:22:03 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604203664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1604203664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/8.prim_present_test.326664577 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6691660000 ps |
| CPU time | 16.39 seconds |
| Started | Oct 02 04:20:50 PM UTC 24 |
| Finished | Oct 02 04:21:43 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326664577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.326664577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default/9.prim_present_test.3281921949 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8645280000 ps |
| CPU time | 22.18 seconds |
| Started | Oct 02 04:20:50 PM UTC 24 |
| Finished | Oct 02 04:21:58 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281921949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3281921949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |