| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/1.prim_present_test.730983990 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/0.prim_present_test.3352309686 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/10.prim_present_test.1612678301 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/11.prim_present_test.2128987538 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/12.prim_present_test.1564646341 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/13.prim_present_test.3083590900 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/14.prim_present_test.2223982627 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/15.prim_present_test.2687380896 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/16.prim_present_test.843604644 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/17.prim_present_test.2915476042 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/18.prim_present_test.1619432131 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/19.prim_present_test.2697705592 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/2.prim_present_test.1255878873 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/20.prim_present_test.3550683301 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/21.prim_present_test.1208960588 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/22.prim_present_test.776395654 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/23.prim_present_test.3096102899 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/24.prim_present_test.178853651 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/25.prim_present_test.1840564291 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/26.prim_present_test.3293619270 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/27.prim_present_test.4007398740 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/28.prim_present_test.588569204 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/29.prim_present_test.1591712096 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/3.prim_present_test.1712460999 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/30.prim_present_test.1606018207 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/31.prim_present_test.1645861364 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/32.prim_present_test.1731497130 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/33.prim_present_test.1139294091 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/34.prim_present_test.3885505011 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/35.prim_present_test.2902209441 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/36.prim_present_test.3045922959 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/37.prim_present_test.3296362955 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/38.prim_present_test.3516091361 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/39.prim_present_test.1547186676 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/4.prim_present_test.4129141616 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/40.prim_present_test.118833795 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/41.prim_present_test.1895941884 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/42.prim_present_test.3566843940 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/43.prim_present_test.2417256439 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/44.prim_present_test.2175329746 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/45.prim_present_test.3931665009 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/46.prim_present_test.3231280957 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/47.prim_present_test.3179819232 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/48.prim_present_test.4207689426 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/49.prim_present_test.3846869575 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/5.prim_present_test.3722035177 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/6.prim_present_test.2818351111 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/7.prim_present_test.2987854342 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/8.prim_present_test.1061838331 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/9.prim_present_test.3826176762 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/2.prim_present_test.1255878873 | Oct 09 08:59:53 PM UTC 24 | Oct 09 09:00:31 PM UTC 24 | 4348680000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/16.prim_present_test.843604644 | Oct 09 08:59:58 PM UTC 24 | Oct 09 09:00:31 PM UTC 24 | 3801220000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/10.prim_present_test.1612678301 | Oct 09 08:59:55 PM UTC 24 | Oct 09 09:00:39 PM UTC 24 | 5038740000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/35.prim_present_test.2902209441 | Oct 09 09:00:07 PM UTC 24 | Oct 09 09:00:41 PM UTC 24 | 3176880000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/44.prim_present_test.2175329746 | Oct 09 09:00:14 PM UTC 24 | Oct 09 09:00:45 PM UTC 24 | 3326300000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/19.prim_present_test.2697705592 | Oct 09 08:59:58 PM UTC 24 | Oct 09 09:00:49 PM UTC 24 | 5837920000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/48.prim_present_test.4207689426 | Oct 09 09:00:16 PM UTC 24 | Oct 09 09:00:49 PM UTC 24 | 3682180000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/1.prim_present_test.730983990 | Oct 09 08:59:53 PM UTC 24 | Oct 09 09:00:51 PM UTC 24 | 6634620000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/34.prim_present_test.3885505011 | Oct 09 09:00:07 PM UTC 24 | Oct 09 09:00:51 PM UTC 24 | 4441680000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/46.prim_present_test.3231280957 | Oct 09 09:00:14 PM UTC 24 | Oct 09 09:00:53 PM UTC 24 | 4316440000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/27.prim_present_test.4007398740 | Oct 09 09:00:02 PM UTC 24 | Oct 09 09:00:55 PM UTC 24 | 4833520000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/40.prim_present_test.118833795 | Oct 09 09:00:08 PM UTC 24 | Oct 09 09:00:56 PM UTC 24 | 4915980000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/45.prim_present_test.3931665009 | Oct 09 09:00:14 PM UTC 24 | Oct 09 09:00:58 PM UTC 24 | 4971160000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/8.prim_present_test.1061838331 | Oct 09 08:59:55 PM UTC 24 | Oct 09 09:00:59 PM UTC 24 | 7371800000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/41.prim_present_test.1895941884 | Oct 09 09:00:09 PM UTC 24 | Oct 09 09:01:04 PM UTC 24 | 5886900000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/12.prim_present_test.1564646341 | Oct 09 08:59:56 PM UTC 24 | Oct 09 09:01:05 PM UTC 24 | 7965760000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/37.prim_present_test.3296362955 | Oct 09 09:00:08 PM UTC 24 | Oct 09 09:01:06 PM UTC 24 | 6180160000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/14.prim_present_test.2223982627 | Oct 09 08:59:57 PM UTC 24 | Oct 09 09:01:07 PM UTC 24 | 8007300000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/38.prim_present_test.3516091361 | Oct 09 09:00:08 PM UTC 24 | Oct 09 09:01:10 PM UTC 24 | 6640200000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/20.prim_present_test.3550683301 | Oct 09 09:00:01 PM UTC 24 | Oct 09 09:01:13 PM UTC 24 | 6988640000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/3.prim_present_test.1712460999 | Oct 09 08:59:55 PM UTC 24 | Oct 09 09:01:18 PM UTC 24 | 9679440000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/28.prim_present_test.588569204 | Oct 09 09:00:02 PM UTC 24 | Oct 09 09:01:20 PM UTC 24 | 7851680000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/26.prim_present_test.3293619270 | Oct 09 09:00:01 PM UTC 24 | Oct 09 09:01:20 PM UTC 24 | 7914920000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/32.prim_present_test.1731497130 | Oct 09 09:00:07 PM UTC 24 | Oct 09 09:01:22 PM UTC 24 | 8050080000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/30.prim_present_test.1606018207 | Oct 09 09:00:07 PM UTC 24 | Oct 09 09:01:23 PM UTC 24 | 8298700000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/13.prim_present_test.3083590900 | Oct 09 08:59:57 PM UTC 24 | Oct 09 09:01:24 PM UTC 24 | 10071900000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/0.prim_present_test.3352309686 | Oct 09 08:59:53 PM UTC 24 | Oct 09 09:01:24 PM UTC 24 | 10679500000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/49.prim_present_test.3846869575 | Oct 09 09:00:16 PM UTC 24 | Oct 09 09:01:29 PM UTC 24 | 8547940000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/5.prim_present_test.3722035177 | Oct 09 08:59:55 PM UTC 24 | Oct 09 09:01:29 PM UTC 24 | 11068240000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/7.prim_present_test.2987854342 | Oct 09 08:59:55 PM UTC 24 | Oct 09 09:01:30 PM UTC 24 | 11104200000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/29.prim_present_test.1591712096 | Oct 09 09:00:07 PM UTC 24 | Oct 09 09:01:31 PM UTC 24 | 9191500000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/17.prim_present_test.2915476042 | Oct 09 08:59:58 PM UTC 24 | Oct 09 09:01:36 PM UTC 24 | 11533240000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/23.prim_present_test.3096102899 | Oct 09 09:00:01 PM UTC 24 | Oct 09 09:01:41 PM UTC 24 | 10367640000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/4.prim_present_test.4129141616 | Oct 09 08:59:55 PM UTC 24 | Oct 09 09:01:43 PM UTC 24 | 12600260000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/42.prim_present_test.3566843940 | Oct 09 09:00:09 PM UTC 24 | Oct 09 09:01:44 PM UTC 24 | 10708640000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/31.prim_present_test.1645861364 | Oct 09 09:00:07 PM UTC 24 | Oct 09 09:01:45 PM UTC 24 | 10807840000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/25.prim_present_test.1840564291 | Oct 09 09:00:01 PM UTC 24 | Oct 09 09:01:46 PM UTC 24 | 10897740000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/39.prim_present_test.1547186676 | Oct 09 09:00:08 PM UTC 24 | Oct 09 09:01:48 PM UTC 24 | 11177360000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/15.prim_present_test.2687380896 | Oct 09 08:59:57 PM UTC 24 | Oct 09 09:01:49 PM UTC 24 | 13002640000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/21.prim_present_test.1208960588 | Oct 09 09:00:01 PM UTC 24 | Oct 09 09:01:49 PM UTC 24 | 11378240000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/43.prim_present_test.2417256439 | Oct 09 09:00:10 PM UTC 24 | Oct 09 09:01:50 PM UTC 24 | 11363980000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/11.prim_present_test.2128987538 | Oct 09 08:59:55 PM UTC 24 | Oct 09 09:01:52 PM UTC 24 | 13672860000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/18.prim_present_test.1619432131 | Oct 09 08:59:58 PM UTC 24 | Oct 09 09:01:53 PM UTC 24 | 13470740000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/9.prim_present_test.3826176762 | Oct 09 08:59:55 PM UTC 24 | Oct 09 09:01:55 PM UTC 24 | 14080820000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/6.prim_present_test.2818351111 | Oct 09 08:59:55 PM UTC 24 | Oct 09 09:01:58 PM UTC 24 | 14449100000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/22.prim_present_test.776395654 | Oct 09 09:00:01 PM UTC 24 | Oct 09 09:02:12 PM UTC 24 | 14065940000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/36.prim_present_test.3045922959 | Oct 09 09:00:07 PM UTC 24 | Oct 09 09:02:17 PM UTC 24 | 14610920000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/47.prim_present_test.3179819232 | Oct 09 09:00:16 PM UTC 24 | Oct 09 09:02:18 PM UTC 24 | 14299060000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/24.prim_present_test.178853651 | Oct 09 09:00:01 PM UTC 24 | Oct 09 09:02:19 PM UTC 24 | 14853960000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/33.prim_present_test.1139294091 | Oct 09 09:00:07 PM UTC 24 | Oct 09 09:02:22 PM UTC 24 | 15247660000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/1.prim_present_test.730983990 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6634620000 ps |
| CPU time | 14.87 seconds |
| Started | Oct 09 08:59:53 PM UTC 24 |
| Finished | Oct 09 09:00:51 PM UTC 24 |
| Peak memory | 151876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730983990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.730983990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/0.prim_present_test.3352309686 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10679500000 ps |
| CPU time | 24.81 seconds |
| Started | Oct 09 08:59:53 PM UTC 24 |
| Finished | Oct 09 09:01:24 PM UTC 24 |
| Peak memory | 151832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352309686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3352309686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/10.prim_present_test.1612678301 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5038740000 ps |
| CPU time | 11.78 seconds |
| Started | Oct 09 08:59:55 PM UTC 24 |
| Finished | Oct 09 09:00:39 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612678301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1612678301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/11.prim_present_test.2128987538 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13672860000 ps |
| CPU time | 32.35 seconds |
| Started | Oct 09 08:59:55 PM UTC 24 |
| Finished | Oct 09 09:01:52 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128987538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2128987538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/12.prim_present_test.1564646341 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7965760000 ps |
| CPU time | 18.3 seconds |
| Started | Oct 09 08:59:56 PM UTC 24 |
| Finished | Oct 09 09:01:05 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564646341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1564646341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/13.prim_present_test.3083590900 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10071900000 ps |
| CPU time | 23.24 seconds |
| Started | Oct 09 08:59:57 PM UTC 24 |
| Finished | Oct 09 09:01:24 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083590900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3083590900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/14.prim_present_test.2223982627 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8007300000 ps |
| CPU time | 18.47 seconds |
| Started | Oct 09 08:59:57 PM UTC 24 |
| Finished | Oct 09 09:01:07 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223982627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2223982627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/15.prim_present_test.2687380896 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13002640000 ps |
| CPU time | 29.97 seconds |
| Started | Oct 09 08:59:57 PM UTC 24 |
| Finished | Oct 09 09:01:49 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687380896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2687380896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/16.prim_present_test.843604644 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3801220000 ps |
| CPU time | 9.22 seconds |
| Started | Oct 09 08:59:58 PM UTC 24 |
| Finished | Oct 09 09:00:31 PM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843604644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.843604644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/17.prim_present_test.2915476042 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 11533240000 ps |
| CPU time | 26.58 seconds |
| Started | Oct 09 08:59:58 PM UTC 24 |
| Finished | Oct 09 09:01:36 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915476042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2915476042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/18.prim_present_test.1619432131 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13470740000 ps |
| CPU time | 31.25 seconds |
| Started | Oct 09 08:59:58 PM UTC 24 |
| Finished | Oct 09 09:01:53 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619432131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1619432131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/19.prim_present_test.2697705592 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5837920000 ps |
| CPU time | 13.5 seconds |
| Started | Oct 09 08:59:58 PM UTC 24 |
| Finished | Oct 09 09:00:49 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697705592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2697705592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/2.prim_present_test.1255878873 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4348680000 ps |
| CPU time | 10 seconds |
| Started | Oct 09 08:59:53 PM UTC 24 |
| Finished | Oct 09 09:00:31 PM UTC 24 |
| Peak memory | 152208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255878873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1255878873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/20.prim_present_test.3550683301 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6988640000 ps |
| CPU time | 16.95 seconds |
| Started | Oct 09 09:00:01 PM UTC 24 |
| Finished | Oct 09 09:01:13 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550683301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3550683301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/21.prim_present_test.1208960588 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11378240000 ps |
| CPU time | 27.16 seconds |
| Started | Oct 09 09:00:01 PM UTC 24 |
| Finished | Oct 09 09:01:49 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208960588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1208960588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/22.prim_present_test.776395654 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14065940000 ps |
| CPU time | 34.11 seconds |
| Started | Oct 09 09:00:01 PM UTC 24 |
| Finished | Oct 09 09:02:12 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776395654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.776395654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/23.prim_present_test.3096102899 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10367640000 ps |
| CPU time | 25 seconds |
| Started | Oct 09 09:00:01 PM UTC 24 |
| Finished | Oct 09 09:01:41 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096102899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3096102899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/24.prim_present_test.178853651 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14853960000 ps |
| CPU time | 36.13 seconds |
| Started | Oct 09 09:00:01 PM UTC 24 |
| Finished | Oct 09 09:02:19 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178853651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.178853651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/25.prim_present_test.1840564291 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10897740000 ps |
| CPU time | 26.55 seconds |
| Started | Oct 09 09:00:01 PM UTC 24 |
| Finished | Oct 09 09:01:46 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840564291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1840564291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/26.prim_present_test.3293619270 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7914920000 ps |
| CPU time | 19.16 seconds |
| Started | Oct 09 09:00:01 PM UTC 24 |
| Finished | Oct 09 09:01:20 PM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293619270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3293619270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/27.prim_present_test.4007398740 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4833520000 ps |
| CPU time | 11.65 seconds |
| Started | Oct 09 09:00:02 PM UTC 24 |
| Finished | Oct 09 09:00:55 PM UTC 24 |
| Peak memory | 152108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007398740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.4007398740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/28.prim_present_test.588569204 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7851680000 ps |
| CPU time | 19.19 seconds |
| Started | Oct 09 09:00:02 PM UTC 24 |
| Finished | Oct 09 09:01:20 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588569204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.588569204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/29.prim_present_test.1591712096 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9191500000 ps |
| CPU time | 22.45 seconds |
| Started | Oct 09 09:00:07 PM UTC 24 |
| Finished | Oct 09 09:01:31 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591712096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1591712096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/3.prim_present_test.1712460999 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9679440000 ps |
| CPU time | 22.04 seconds |
| Started | Oct 09 08:59:55 PM UTC 24 |
| Finished | Oct 09 09:01:18 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712460999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1712460999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/30.prim_present_test.1606018207 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8298700000 ps |
| CPU time | 19.63 seconds |
| Started | Oct 09 09:00:07 PM UTC 24 |
| Finished | Oct 09 09:01:23 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606018207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1606018207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/31.prim_present_test.1645861364 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10807840000 ps |
| CPU time | 26.36 seconds |
| Started | Oct 09 09:00:07 PM UTC 24 |
| Finished | Oct 09 09:01:45 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645861364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1645861364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/32.prim_present_test.1731497130 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8050080000 ps |
| CPU time | 19.1 seconds |
| Started | Oct 09 09:00:07 PM UTC 24 |
| Finished | Oct 09 09:01:22 PM UTC 24 |
| Peak memory | 151972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731497130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1731497130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/33.prim_present_test.1139294091 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15247660000 ps |
| CPU time | 36.58 seconds |
| Started | Oct 09 09:00:07 PM UTC 24 |
| Finished | Oct 09 09:02:22 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139294091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1139294091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/34.prim_present_test.3885505011 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4441680000 ps |
| CPU time | 10.89 seconds |
| Started | Oct 09 09:00:07 PM UTC 24 |
| Finished | Oct 09 09:00:51 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885505011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3885505011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/35.prim_present_test.2902209441 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3176880000 ps |
| CPU time | 7.97 seconds |
| Started | Oct 09 09:00:07 PM UTC 24 |
| Finished | Oct 09 09:00:41 PM UTC 24 |
| Peak memory | 151916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902209441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2902209441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/36.prim_present_test.3045922959 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14610920000 ps |
| CPU time | 35.28 seconds |
| Started | Oct 09 09:00:07 PM UTC 24 |
| Finished | Oct 09 09:02:17 PM UTC 24 |
| Peak memory | 151880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045922959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3045922959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/37.prim_present_test.3296362955 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6180160000 ps |
| CPU time | 15.09 seconds |
| Started | Oct 09 09:00:08 PM UTC 24 |
| Finished | Oct 09 09:01:06 PM UTC 24 |
| Peak memory | 152128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296362955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3296362955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/38.prim_present_test.3516091361 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6640200000 ps |
| CPU time | 16.26 seconds |
| Started | Oct 09 09:00:08 PM UTC 24 |
| Finished | Oct 09 09:01:10 PM UTC 24 |
| Peak memory | 152000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516091361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3516091361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/39.prim_present_test.1547186676 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11177360000 ps |
| CPU time | 27.01 seconds |
| Started | Oct 09 09:00:08 PM UTC 24 |
| Finished | Oct 09 09:01:48 PM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547186676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1547186676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/4.prim_present_test.4129141616 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12600260000 ps |
| CPU time | 28.79 seconds |
| Started | Oct 09 08:59:55 PM UTC 24 |
| Finished | Oct 09 09:01:43 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129141616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4129141616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/40.prim_present_test.118833795 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4915980000 ps |
| CPU time | 11.84 seconds |
| Started | Oct 09 09:00:08 PM UTC 24 |
| Finished | Oct 09 09:00:56 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118833795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.118833795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/41.prim_present_test.1895941884 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5886900000 ps |
| CPU time | 14.07 seconds |
| Started | Oct 09 09:00:09 PM UTC 24 |
| Finished | Oct 09 09:01:04 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895941884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1895941884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/42.prim_present_test.3566843940 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10708640000 ps |
| CPU time | 25.87 seconds |
| Started | Oct 09 09:00:09 PM UTC 24 |
| Finished | Oct 09 09:01:44 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566843940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3566843940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/43.prim_present_test.2417256439 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11363980000 ps |
| CPU time | 27.18 seconds |
| Started | Oct 09 09:00:10 PM UTC 24 |
| Finished | Oct 09 09:01:50 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417256439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2417256439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/44.prim_present_test.2175329746 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3326300000 ps |
| CPU time | 8.39 seconds |
| Started | Oct 09 09:00:14 PM UTC 24 |
| Finished | Oct 09 09:00:45 PM UTC 24 |
| Peak memory | 152084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175329746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2175329746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/45.prim_present_test.3931665009 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4971160000 ps |
| CPU time | 11.94 seconds |
| Started | Oct 09 09:00:14 PM UTC 24 |
| Finished | Oct 09 09:00:58 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931665009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3931665009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/46.prim_present_test.3231280957 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4316440000 ps |
| CPU time | 10.72 seconds |
| Started | Oct 09 09:00:14 PM UTC 24 |
| Finished | Oct 09 09:00:53 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231280957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3231280957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/47.prim_present_test.3179819232 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14299060000 ps |
| CPU time | 34.8 seconds |
| Started | Oct 09 09:00:16 PM UTC 24 |
| Finished | Oct 09 09:02:18 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179819232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3179819232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/48.prim_present_test.4207689426 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3682180000 ps |
| CPU time | 9.04 seconds |
| Started | Oct 09 09:00:16 PM UTC 24 |
| Finished | Oct 09 09:00:49 PM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207689426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4207689426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/49.prim_present_test.3846869575 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8547940000 ps |
| CPU time | 20.83 seconds |
| Started | Oct 09 09:00:16 PM UTC 24 |
| Finished | Oct 09 09:01:29 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846869575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3846869575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/5.prim_present_test.3722035177 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11068240000 ps |
| CPU time | 25.37 seconds |
| Started | Oct 09 08:59:55 PM UTC 24 |
| Finished | Oct 09 09:01:29 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722035177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3722035177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/6.prim_present_test.2818351111 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14449100000 ps |
| CPU time | 33.12 seconds |
| Started | Oct 09 08:59:55 PM UTC 24 |
| Finished | Oct 09 09:01:58 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818351111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2818351111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/7.prim_present_test.2987854342 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11104200000 ps |
| CPU time | 26.22 seconds |
| Started | Oct 09 08:59:55 PM UTC 24 |
| Finished | Oct 09 09:01:30 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987854342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2987854342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/8.prim_present_test.1061838331 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7371800000 ps |
| CPU time | 17.17 seconds |
| Started | Oct 09 08:59:55 PM UTC 24 |
| Finished | Oct 09 09:00:59 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061838331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1061838331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default/9.prim_present_test.3826176762 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14080820000 ps |
| CPU time | 32.4 seconds |
| Started | Oct 09 08:59:55 PM UTC 24 |
| Finished | Oct 09 09:01:55 PM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826176762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3826176762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |