| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/0.prim_present_test.3894625738 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/1.prim_present_test.1540597631 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/10.prim_present_test.645464672 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/11.prim_present_test.2212492790 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/12.prim_present_test.2207763922 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/13.prim_present_test.1249197783 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/14.prim_present_test.1766486532 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/15.prim_present_test.3206996054 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/16.prim_present_test.1313159045 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/17.prim_present_test.1748146053 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/18.prim_present_test.2885659880 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/19.prim_present_test.3025271869 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/2.prim_present_test.2318143176 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/20.prim_present_test.3004961643 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/21.prim_present_test.935109084 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/22.prim_present_test.560774899 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/23.prim_present_test.2147571337 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/24.prim_present_test.3298338708 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/25.prim_present_test.714642016 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/26.prim_present_test.1804968334 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/27.prim_present_test.859368006 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/28.prim_present_test.2433638339 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/29.prim_present_test.564425075 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/3.prim_present_test.1705968844 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/30.prim_present_test.3425070121 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/31.prim_present_test.1891840038 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/32.prim_present_test.1926530182 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/33.prim_present_test.3183472490 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/34.prim_present_test.4088975082 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/35.prim_present_test.3560101096 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/36.prim_present_test.1494926512 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/37.prim_present_test.3335527507 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/38.prim_present_test.1804505510 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/39.prim_present_test.1559048360 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/4.prim_present_test.526634110 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/40.prim_present_test.927709581 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/41.prim_present_test.1602903893 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/42.prim_present_test.1871024649 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/43.prim_present_test.3411856755 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/44.prim_present_test.369264957 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/45.prim_present_test.1247766519 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/46.prim_present_test.585685535 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/47.prim_present_test.3842392282 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/48.prim_present_test.2774979184 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/49.prim_present_test.734780552 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/5.prim_present_test.3671304648 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/6.prim_present_test.301875110 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/7.prim_present_test.2832953732 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/8.prim_present_test.3157569351 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/9.prim_present_test.3610769409 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/1.prim_present_test.1540597631 | Oct 12 11:23:41 AM UTC 24 | Oct 12 11:24:11 AM UTC 24 | 3892360000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/4.prim_present_test.526634110 | Oct 12 11:23:42 AM UTC 24 | Oct 12 11:24:11 AM UTC 24 | 3751620000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/10.prim_present_test.645464672 | Oct 12 11:23:49 AM UTC 24 | Oct 12 11:24:13 AM UTC 24 | 3241360000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/15.prim_present_test.3206996054 | Oct 12 11:23:51 AM UTC 24 | Oct 12 11:24:15 AM UTC 24 | 3268640000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/16.prim_present_test.1313159045 | Oct 12 11:23:52 AM UTC 24 | Oct 12 11:24:26 AM UTC 24 | 4514220000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/0.prim_present_test.3894625738 | Oct 12 11:23:41 AM UTC 24 | Oct 12 11:24:33 AM UTC 24 | 7069860000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/7.prim_present_test.2832953732 | Oct 12 11:23:46 AM UTC 24 | Oct 12 11:24:39 AM UTC 24 | 7126280000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/8.prim_present_test.3157569351 | Oct 12 11:23:46 AM UTC 24 | Oct 12 11:24:39 AM UTC 24 | 7239740000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/5.prim_present_test.3671304648 | Oct 12 11:23:44 AM UTC 24 | Oct 12 11:24:45 AM UTC 24 | 8356980000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/17.prim_present_test.1748146053 | Oct 12 11:23:53 AM UTC 24 | Oct 12 11:24:46 AM UTC 24 | 7289960000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/12.prim_present_test.2207763922 | Oct 12 11:23:49 AM UTC 24 | Oct 12 11:24:46 AM UTC 24 | 7861600000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/14.prim_present_test.1766486532 | Oct 12 11:23:50 AM UTC 24 | Oct 12 11:24:46 AM UTC 24 | 7844240000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/22.prim_present_test.560774899 | Oct 12 11:24:14 AM UTC 24 | Oct 12 11:24:47 AM UTC 24 | 4516700000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/2.prim_present_test.2318143176 | Oct 12 11:23:41 AM UTC 24 | Oct 12 11:24:57 AM UTC 24 | 10474900000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/24.prim_present_test.3298338708 | Oct 12 11:24:22 AM UTC 24 | Oct 12 11:24:57 AM UTC 24 | 4647520000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/6.prim_present_test.301875110 | Oct 12 11:23:45 AM UTC 24 | Oct 12 11:25:02 AM UTC 24 | 10586500000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/26.prim_present_test.1804968334 | Oct 12 11:24:33 AM UTC 24 | Oct 12 11:25:05 AM UTC 24 | 4239560000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/28.prim_present_test.2433638339 | Oct 12 11:24:40 AM UTC 24 | Oct 12 11:25:09 AM UTC 24 | 3807420000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/30.prim_present_test.3425070121 | Oct 12 11:24:46 AM UTC 24 | Oct 12 11:25:10 AM UTC 24 | 3155800000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/33.prim_present_test.3183472490 | Oct 12 11:24:48 AM UTC 24 | Oct 12 11:25:14 AM UTC 24 | 3509200000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/9.prim_present_test.3610769409 | Oct 12 11:23:48 AM UTC 24 | Oct 12 11:25:15 AM UTC 24 | 12073880000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/20.prim_present_test.3004961643 | Oct 12 11:24:12 AM UTC 24 | Oct 12 11:25:17 AM UTC 24 | 8969540000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/3.prim_present_test.1705968844 | Oct 12 11:23:42 AM UTC 24 | Oct 12 11:25:17 AM UTC 24 | 13241960000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/27.prim_present_test.859368006 | Oct 12 11:24:39 AM UTC 24 | Oct 12 11:25:20 AM UTC 24 | 5512420000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/36.prim_present_test.1494926512 | Oct 12 11:24:58 AM UTC 24 | Oct 12 11:25:24 AM UTC 24 | 3550740000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/19.prim_present_test.3025271869 | Oct 12 11:24:00 AM UTC 24 | Oct 12 11:25:26 AM UTC 24 | 11910200000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/13.prim_present_test.1249197783 | Oct 12 11:23:50 AM UTC 24 | Oct 12 11:25:27 AM UTC 24 | 13499260000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/21.prim_present_test.935109084 | Oct 12 11:24:12 AM UTC 24 | Oct 12 11:25:30 AM UTC 24 | 10732200000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/37.prim_present_test.3335527507 | Oct 12 11:25:03 AM UTC 24 | Oct 12 11:25:30 AM UTC 24 | 3603440000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/11.prim_present_test.2212492790 | Oct 12 11:23:49 AM UTC 24 | Oct 12 11:25:31 AM UTC 24 | 14405700000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/40.prim_present_test.927709581 | Oct 12 11:25:11 AM UTC 24 | Oct 12 11:25:35 AM UTC 24 | 3176260000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/18.prim_present_test.2885659880 | Oct 12 11:23:58 AM UTC 24 | Oct 12 11:25:37 AM UTC 24 | 14061600000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/39.prim_present_test.1559048360 | Oct 12 11:25:10 AM UTC 24 | Oct 12 11:25:42 AM UTC 24 | 4413160000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/23.prim_present_test.2147571337 | Oct 12 11:24:16 AM UTC 24 | Oct 12 11:25:47 AM UTC 24 | 12911500000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/41.prim_present_test.1602903893 | Oct 12 11:25:15 AM UTC 24 | Oct 12 11:25:49 AM UTC 24 | 4691540000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/31.prim_present_test.1891840038 | Oct 12 11:24:46 AM UTC 24 | Oct 12 11:25:52 AM UTC 24 | 9216300000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/29.prim_present_test.564425075 | Oct 12 11:24:40 AM UTC 24 | Oct 12 11:25:57 AM UTC 24 | 10611300000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/35.prim_present_test.3560101096 | Oct 12 11:24:58 AM UTC 24 | Oct 12 11:26:06 AM UTC 24 | 9601940000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/47.prim_present_test.3842392282 | Oct 12 11:25:21 AM UTC 24 | Oct 12 11:26:07 AM UTC 24 | 6156600000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/25.prim_present_test.714642016 | Oct 12 11:24:27 AM UTC 24 | Oct 12 11:26:08 AM UTC 24 | 14151500000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/32.prim_present_test.1926530182 | Oct 12 11:24:47 AM UTC 24 | Oct 12 11:26:18 AM UTC 24 | 12528340000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/34.prim_present_test.4088975082 | Oct 12 11:24:49 AM UTC 24 | Oct 12 11:26:29 AM UTC 24 | 14102520000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/44.prim_present_test.369264957 | Oct 12 11:25:18 AM UTC 24 | Oct 12 11:26:31 AM UTC 24 | 10204580000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/43.prim_present_test.3411856755 | Oct 12 11:25:18 AM UTC 24 | Oct 12 11:26:37 AM UTC 24 | 10773120000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/45.prim_present_test.1247766519 | Oct 12 11:25:18 AM UTC 24 | Oct 12 11:26:42 AM UTC 24 | 11493560000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/42.prim_present_test.1871024649 | Oct 12 11:25:16 AM UTC 24 | Oct 12 11:26:54 AM UTC 24 | 13383940000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/49.prim_present_test.734780552 | Oct 12 11:25:27 AM UTC 24 | Oct 12 11:26:55 AM UTC 24 | 11988940000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/48.prim_present_test.2774979184 | Oct 12 11:25:26 AM UTC 24 | Oct 12 11:26:56 AM UTC 24 | 12129680000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/38.prim_present_test.1804505510 | Oct 12 11:25:06 AM UTC 24 | Oct 12 11:26:57 AM UTC 24 | 15104440000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/46.prim_present_test.585685535 | Oct 12 11:25:19 AM UTC 24 | Oct 12 11:27:02 AM UTC 24 | 13845220000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/0.prim_present_test.3894625738 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7069860000 ps |
| CPU time | 17.25 seconds |
| Started | Oct 12 11:23:41 AM UTC 24 |
| Finished | Oct 12 11:24:33 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894625738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3894625738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/1.prim_present_test.1540597631 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3892360000 ps |
| CPU time | 9.7 seconds |
| Started | Oct 12 11:23:41 AM UTC 24 |
| Finished | Oct 12 11:24:11 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540597631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1540597631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/10.prim_present_test.645464672 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3241360000 ps |
| CPU time | 8.12 seconds |
| Started | Oct 12 11:23:49 AM UTC 24 |
| Finished | Oct 12 11:24:13 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645464672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.645464672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/11.prim_present_test.2212492790 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14405700000 ps |
| CPU time | 34.45 seconds |
| Started | Oct 12 11:23:49 AM UTC 24 |
| Finished | Oct 12 11:25:31 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212492790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2212492790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/12.prim_present_test.2207763922 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7861600000 ps |
| CPU time | 18.84 seconds |
| Started | Oct 12 11:23:49 AM UTC 24 |
| Finished | Oct 12 11:24:46 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207763922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2207763922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/13.prim_present_test.1249197783 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13499260000 ps |
| CPU time | 31.93 seconds |
| Started | Oct 12 11:23:50 AM UTC 24 |
| Finished | Oct 12 11:25:27 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249197783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1249197783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/14.prim_present_test.1766486532 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7844240000 ps |
| CPU time | 18.95 seconds |
| Started | Oct 12 11:23:50 AM UTC 24 |
| Finished | Oct 12 11:24:46 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766486532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1766486532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/15.prim_present_test.3206996054 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3268640000 ps |
| CPU time | 8.2 seconds |
| Started | Oct 12 11:23:51 AM UTC 24 |
| Finished | Oct 12 11:24:15 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206996054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3206996054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/16.prim_present_test.1313159045 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4514220000 ps |
| CPU time | 11.05 seconds |
| Started | Oct 12 11:23:52 AM UTC 24 |
| Finished | Oct 12 11:24:26 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313159045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1313159045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/17.prim_present_test.1748146053 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7289960000 ps |
| CPU time | 17.69 seconds |
| Started | Oct 12 11:23:53 AM UTC 24 |
| Finished | Oct 12 11:24:46 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748146053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1748146053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/18.prim_present_test.2885659880 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14061600000 ps |
| CPU time | 33.54 seconds |
| Started | Oct 12 11:23:58 AM UTC 24 |
| Finished | Oct 12 11:25:37 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885659880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2885659880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/19.prim_present_test.3025271869 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11910200000 ps |
| CPU time | 28.21 seconds |
| Started | Oct 12 11:24:00 AM UTC 24 |
| Finished | Oct 12 11:25:26 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025271869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3025271869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/2.prim_present_test.2318143176 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10474900000 ps |
| CPU time | 25.3 seconds |
| Started | Oct 12 11:23:41 AM UTC 24 |
| Finished | Oct 12 11:24:57 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318143176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2318143176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/20.prim_present_test.3004961643 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8969540000 ps |
| CPU time | 21.4 seconds |
| Started | Oct 12 11:24:12 AM UTC 24 |
| Finished | Oct 12 11:25:17 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004961643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3004961643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/21.prim_present_test.935109084 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10732200000 ps |
| CPU time | 25.59 seconds |
| Started | Oct 12 11:24:12 AM UTC 24 |
| Finished | Oct 12 11:25:30 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935109084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.935109084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/22.prim_present_test.560774899 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4516700000 ps |
| CPU time | 11.01 seconds |
| Started | Oct 12 11:24:14 AM UTC 24 |
| Finished | Oct 12 11:24:47 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560774899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.560774899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/23.prim_present_test.2147571337 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12911500000 ps |
| CPU time | 30.77 seconds |
| Started | Oct 12 11:24:16 AM UTC 24 |
| Finished | Oct 12 11:25:47 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147571337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2147571337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/24.prim_present_test.3298338708 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4647520000 ps |
| CPU time | 11.44 seconds |
| Started | Oct 12 11:24:22 AM UTC 24 |
| Finished | Oct 12 11:24:57 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298338708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3298338708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/25.prim_present_test.714642016 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14151500000 ps |
| CPU time | 33.71 seconds |
| Started | Oct 12 11:24:27 AM UTC 24 |
| Finished | Oct 12 11:26:08 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714642016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.714642016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/26.prim_present_test.1804968334 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4239560000 ps |
| CPU time | 10.51 seconds |
| Started | Oct 12 11:24:33 AM UTC 24 |
| Finished | Oct 12 11:25:05 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804968334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1804968334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/27.prim_present_test.859368006 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5512420000 ps |
| CPU time | 13.44 seconds |
| Started | Oct 12 11:24:39 AM UTC 24 |
| Finished | Oct 12 11:25:20 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859368006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.859368006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/28.prim_present_test.2433638339 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3807420000 ps |
| CPU time | 9.42 seconds |
| Started | Oct 12 11:24:40 AM UTC 24 |
| Finished | Oct 12 11:25:09 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433638339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2433638339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/29.prim_present_test.564425075 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10611300000 ps |
| CPU time | 25.21 seconds |
| Started | Oct 12 11:24:40 AM UTC 24 |
| Finished | Oct 12 11:25:57 AM UTC 24 |
| Peak memory | 153520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564425075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.564425075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/3.prim_present_test.1705968844 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13241960000 ps |
| CPU time | 31.84 seconds |
| Started | Oct 12 11:23:42 AM UTC 24 |
| Finished | Oct 12 11:25:17 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705968844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1705968844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/30.prim_present_test.3425070121 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3155800000 ps |
| CPU time | 7.88 seconds |
| Started | Oct 12 11:24:46 AM UTC 24 |
| Finished | Oct 12 11:25:10 AM UTC 24 |
| Peak memory | 151996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425070121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3425070121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/31.prim_present_test.1891840038 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9216300000 ps |
| CPU time | 22.19 seconds |
| Started | Oct 12 11:24:46 AM UTC 24 |
| Finished | Oct 12 11:25:52 AM UTC 24 |
| Peak memory | 152056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891840038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1891840038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/32.prim_present_test.1926530182 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12528340000 ps |
| CPU time | 29.91 seconds |
| Started | Oct 12 11:24:47 AM UTC 24 |
| Finished | Oct 12 11:26:18 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926530182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1926530182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/33.prim_present_test.3183472490 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3509200000 ps |
| CPU time | 8.92 seconds |
| Started | Oct 12 11:24:48 AM UTC 24 |
| Finished | Oct 12 11:25:14 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183472490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3183472490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/34.prim_present_test.4088975082 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14102520000 ps |
| CPU time | 33.65 seconds |
| Started | Oct 12 11:24:49 AM UTC 24 |
| Finished | Oct 12 11:26:29 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088975082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.4088975082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/35.prim_present_test.3560101096 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9601940000 ps |
| CPU time | 23.08 seconds |
| Started | Oct 12 11:24:58 AM UTC 24 |
| Finished | Oct 12 11:26:06 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560101096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3560101096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/36.prim_present_test.1494926512 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3550740000 ps |
| CPU time | 8.81 seconds |
| Started | Oct 12 11:24:58 AM UTC 24 |
| Finished | Oct 12 11:25:24 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494926512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1494926512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/37.prim_present_test.3335527507 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3603440000 ps |
| CPU time | 8.92 seconds |
| Started | Oct 12 11:25:03 AM UTC 24 |
| Finished | Oct 12 11:25:30 AM UTC 24 |
| Peak memory | 152072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335527507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3335527507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/38.prim_present_test.1804505510 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15104440000 ps |
| CPU time | 36.09 seconds |
| Started | Oct 12 11:25:06 AM UTC 24 |
| Finished | Oct 12 11:26:57 AM UTC 24 |
| Peak memory | 152140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804505510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1804505510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/39.prim_present_test.1559048360 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4413160000 ps |
| CPU time | 10.77 seconds |
| Started | Oct 12 11:25:10 AM UTC 24 |
| Finished | Oct 12 11:25:42 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559048360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1559048360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/4.prim_present_test.526634110 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3751620000 ps |
| CPU time | 9.3 seconds |
| Started | Oct 12 11:23:42 AM UTC 24 |
| Finished | Oct 12 11:24:11 AM UTC 24 |
| Peak memory | 152096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526634110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.526634110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/40.prim_present_test.927709581 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3176260000 ps |
| CPU time | 8 seconds |
| Started | Oct 12 11:25:11 AM UTC 24 |
| Finished | Oct 12 11:25:35 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927709581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.927709581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/41.prim_present_test.1602903893 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4691540000 ps |
| CPU time | 11.49 seconds |
| Started | Oct 12 11:25:15 AM UTC 24 |
| Finished | Oct 12 11:25:49 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602903893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1602903893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/42.prim_present_test.1871024649 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13383940000 ps |
| CPU time | 32.74 seconds |
| Started | Oct 12 11:25:16 AM UTC 24 |
| Finished | Oct 12 11:26:54 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871024649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1871024649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/43.prim_present_test.3411856755 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10773120000 ps |
| CPU time | 25.99 seconds |
| Started | Oct 12 11:25:18 AM UTC 24 |
| Finished | Oct 12 11:26:37 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411856755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3411856755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/44.prim_present_test.369264957 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10204580000 ps |
| CPU time | 24.71 seconds |
| Started | Oct 12 11:25:18 AM UTC 24 |
| Finished | Oct 12 11:26:31 AM UTC 24 |
| Peak memory | 152136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369264957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.369264957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/45.prim_present_test.1247766519 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11493560000 ps |
| CPU time | 27.7 seconds |
| Started | Oct 12 11:25:18 AM UTC 24 |
| Finished | Oct 12 11:26:42 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247766519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1247766519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/46.prim_present_test.585685535 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13845220000 ps |
| CPU time | 33.26 seconds |
| Started | Oct 12 11:25:19 AM UTC 24 |
| Finished | Oct 12 11:27:02 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585685535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.585685535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/47.prim_present_test.3842392282 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6156600000 ps |
| CPU time | 15.04 seconds |
| Started | Oct 12 11:25:21 AM UTC 24 |
| Finished | Oct 12 11:26:07 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842392282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3842392282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/48.prim_present_test.2774979184 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12129680000 ps |
| CPU time | 29.29 seconds |
| Started | Oct 12 11:25:26 AM UTC 24 |
| Finished | Oct 12 11:26:56 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774979184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2774979184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/49.prim_present_test.734780552 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11988940000 ps |
| CPU time | 29.55 seconds |
| Started | Oct 12 11:25:27 AM UTC 24 |
| Finished | Oct 12 11:26:55 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734780552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.734780552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/5.prim_present_test.3671304648 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8356980000 ps |
| CPU time | 19.97 seconds |
| Started | Oct 12 11:23:44 AM UTC 24 |
| Finished | Oct 12 11:24:45 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671304648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3671304648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/6.prim_present_test.301875110 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10586500000 ps |
| CPU time | 25.57 seconds |
| Started | Oct 12 11:23:45 AM UTC 24 |
| Finished | Oct 12 11:25:02 AM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301875110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.301875110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/7.prim_present_test.2832953732 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7126280000 ps |
| CPU time | 17.16 seconds |
| Started | Oct 12 11:23:46 AM UTC 24 |
| Finished | Oct 12 11:24:39 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832953732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2832953732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/8.prim_present_test.3157569351 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7239740000 ps |
| CPU time | 17.46 seconds |
| Started | Oct 12 11:23:46 AM UTC 24 |
| Finished | Oct 12 11:24:39 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157569351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3157569351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default/9.prim_present_test.3610769409 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12073880000 ps |
| CPU time | 28.65 seconds |
| Started | Oct 12 11:23:48 AM UTC 24 |
| Finished | Oct 12 11:25:15 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610769409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3610769409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_present-sim-vcs/9.prim_present_test/latest |
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