| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/0.prim_present_test.1825081705 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/1.prim_present_test.2942273072 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/10.prim_present_test.1680810324 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/11.prim_present_test.1452139190 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/12.prim_present_test.1250071472 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/13.prim_present_test.707265943 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/14.prim_present_test.1455209045 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/15.prim_present_test.3680429473 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/16.prim_present_test.4005226786 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/17.prim_present_test.2846072763 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/18.prim_present_test.1980925157 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/19.prim_present_test.1642002557 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/2.prim_present_test.861175559 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/20.prim_present_test.3053076327 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/21.prim_present_test.3584342030 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/22.prim_present_test.2654970499 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/23.prim_present_test.2296451933 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/24.prim_present_test.1096590835 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/25.prim_present_test.2878706938 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/26.prim_present_test.3889795475 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/27.prim_present_test.1709048969 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/28.prim_present_test.907626351 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/29.prim_present_test.887314780 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/3.prim_present_test.889126458 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/30.prim_present_test.538509739 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/31.prim_present_test.4069548138 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/32.prim_present_test.2040326781 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/33.prim_present_test.706364802 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/34.prim_present_test.4008718668 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/35.prim_present_test.2093117924 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/36.prim_present_test.3491857042 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/37.prim_present_test.3667897872 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/38.prim_present_test.1068451518 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/39.prim_present_test.1806252298 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/4.prim_present_test.3428529375 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/40.prim_present_test.285110527 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/41.prim_present_test.1546825120 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/42.prim_present_test.3459687988 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/43.prim_present_test.3094679404 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/44.prim_present_test.3286586279 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/45.prim_present_test.1203242170 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/46.prim_present_test.4216489593 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/47.prim_present_test.2426172560 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/48.prim_present_test.3912031529 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/49.prim_present_test.2857084026 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/5.prim_present_test.917409632 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/6.prim_present_test.229952979 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/7.prim_present_test.4207238343 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/8.prim_present_test.2467072439 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/9.prim_present_test.1883030428 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/8.prim_present_test.2467072439 | Oct 15 06:18:41 AM UTC 24 | Oct 15 06:19:16 AM UTC 24 | 3348000000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/0.prim_present_test.1825081705 | Oct 15 06:18:31 AM UTC 24 | Oct 15 06:19:26 AM UTC 24 | 5330140000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/3.prim_present_test.889126458 | Oct 15 06:18:34 AM UTC 24 | Oct 15 06:19:32 AM UTC 24 | 5540940000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/14.prim_present_test.1455209045 | Oct 15 06:18:55 AM UTC 24 | Oct 15 06:19:34 AM UTC 24 | 3618940000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/7.prim_present_test.4207238343 | Oct 15 06:18:40 AM UTC 24 | Oct 15 06:19:44 AM UTC 24 | 6281220000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/13.prim_present_test.707265943 | Oct 15 06:18:54 AM UTC 24 | Oct 15 06:20:05 AM UTC 24 | 7115120000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/22.prim_present_test.2654970499 | Oct 15 06:19:30 AM UTC 24 | Oct 15 06:20:07 AM UTC 24 | 3817960000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/1.prim_present_test.2942273072 | Oct 15 06:18:31 AM UTC 24 | Oct 15 06:20:11 AM UTC 24 | 10017340000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/20.prim_present_test.3053076327 | Oct 15 06:19:27 AM UTC 24 | Oct 15 06:20:13 AM UTC 24 | 4671700000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/24.prim_present_test.1096590835 | Oct 15 06:19:34 AM UTC 24 | Oct 15 06:20:21 AM UTC 24 | 4899860000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/11.prim_present_test.1452139190 | Oct 15 06:18:46 AM UTC 24 | Oct 15 06:20:21 AM UTC 24 | 9671380000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/18.prim_present_test.1980925157 | Oct 15 06:19:17 AM UTC 24 | Oct 15 06:20:23 AM UTC 24 | 6762960000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/4.prim_present_test.3428529375 | Oct 15 06:18:34 AM UTC 24 | Oct 15 06:20:25 AM UTC 24 | 11297020000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/2.prim_present_test.861175559 | Oct 15 06:18:32 AM UTC 24 | Oct 15 06:20:26 AM UTC 24 | 11610740000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/5.prim_present_test.917409632 | Oct 15 06:18:34 AM UTC 24 | Oct 15 06:20:27 AM UTC 24 | 11510300000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/33.prim_present_test.706364802 | Oct 15 06:19:54 AM UTC 24 | Oct 15 06:20:32 AM UTC 24 | 4181280000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/19.prim_present_test.1642002557 | Oct 15 06:19:24 AM UTC 24 | Oct 15 06:20:33 AM UTC 24 | 7334600000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/10.prim_present_test.1680810324 | Oct 15 06:18:43 AM UTC 24 | Oct 15 06:20:39 AM UTC 24 | 12071400000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/6.prim_present_test.229952979 | Oct 15 06:18:34 AM UTC 24 | Oct 15 06:20:40 AM UTC 24 | 13075800000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/37.prim_present_test.3667897872 | Oct 15 06:20:12 AM UTC 24 | Oct 15 06:20:51 AM UTC 24 | 4450980000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/34.prim_present_test.4008718668 | Oct 15 06:20:04 AM UTC 24 | Oct 15 06:20:52 AM UTC 24 | 5436160000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/27.prim_present_test.1709048969 | Oct 15 06:19:42 AM UTC 24 | Oct 15 06:20:53 AM UTC 24 | 7904380000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/28.prim_present_test.907626351 | Oct 15 06:19:43 AM UTC 24 | Oct 15 06:21:02 AM UTC 24 | 8784160000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/29.prim_present_test.887314780 | Oct 15 06:19:43 AM UTC 24 | Oct 15 06:21:02 AM UTC 24 | 8804000000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/26.prim_present_test.3889795475 | Oct 15 06:19:42 AM UTC 24 | Oct 15 06:21:04 AM UTC 24 | 9117100000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/9.prim_present_test.1883030428 | Oct 15 06:18:43 AM UTC 24 | Oct 15 06:21:05 AM UTC 24 | 15254480000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/16.prim_present_test.4005226786 | Oct 15 06:19:02 AM UTC 24 | Oct 15 06:21:12 AM UTC 24 | 14021920000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/12.prim_present_test.1250071472 | Oct 15 06:18:51 AM UTC 24 | Oct 15 06:21:14 AM UTC 24 | 15276180000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/21.prim_present_test.3584342030 | Oct 15 06:19:27 AM UTC 24 | Oct 15 06:21:16 AM UTC 24 | 11987700000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/39.prim_present_test.1806252298 | Oct 15 06:20:20 AM UTC 24 | Oct 15 06:21:16 AM UTC 24 | 6295480000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/15.prim_present_test.3680429473 | Oct 15 06:19:02 AM UTC 24 | Oct 15 06:21:17 AM UTC 24 | 14610300000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/46.prim_present_test.4216489593 | Oct 15 06:20:28 AM UTC 24 | Oct 15 06:21:24 AM UTC 24 | 6276880000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/47.prim_present_test.2426172560 | Oct 15 06:20:29 AM UTC 24 | Oct 15 06:21:27 AM UTC 24 | 6374220000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/43.prim_present_test.3094679404 | Oct 15 06:20:26 AM UTC 24 | Oct 15 06:21:29 AM UTC 24 | 7034520000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/17.prim_present_test.2846072763 | Oct 15 06:19:12 AM UTC 24 | Oct 15 06:21:30 AM UTC 24 | 14979820000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/35.prim_present_test.2093117924 | Oct 15 06:20:06 AM UTC 24 | Oct 15 06:21:31 AM UTC 24 | 9476700000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/31.prim_present_test.4069548138 | Oct 15 06:19:52 AM UTC 24 | Oct 15 06:21:33 AM UTC 24 | 11097380000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/40.prim_present_test.285110527 | Oct 15 06:20:21 AM UTC 24 | Oct 15 06:21:46 AM UTC 24 | 9259700000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/30.prim_present_test.538509739 | Oct 15 06:19:45 AM UTC 24 | Oct 15 06:21:46 AM UTC 24 | 13258080000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/23.prim_present_test.2296451933 | Oct 15 06:19:33 AM UTC 24 | Oct 15 06:21:47 AM UTC 24 | 14686560000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/25.prim_present_test.2878706938 | Oct 15 06:19:40 AM UTC 24 | Oct 15 06:21:48 AM UTC 24 | 13929540000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/38.prim_present_test.1068451518 | Oct 15 06:20:14 AM UTC 24 | Oct 15 06:21:50 AM UTC 24 | 10566040000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/36.prim_present_test.3491857042 | Oct 15 06:20:08 AM UTC 24 | Oct 15 06:21:53 AM UTC 24 | 11603300000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/41.prim_present_test.1546825120 | Oct 15 06:20:21 AM UTC 24 | Oct 15 06:21:57 AM UTC 24 | 10432740000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/32.prim_present_test.2040326781 | Oct 15 06:19:54 AM UTC 24 | Oct 15 06:22:00 AM UTC 24 | 13784460000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/44.prim_present_test.3286586279 | Oct 15 06:20:27 AM UTC 24 | Oct 15 06:22:26 AM UTC 24 | 12635600000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/42.prim_present_test.3459687988 | Oct 15 06:20:24 AM UTC 24 | Oct 15 06:22:38 AM UTC 24 | 14319520000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/49.prim_present_test.2857084026 | Oct 15 06:20:33 AM UTC 24 | Oct 15 06:22:45 AM UTC 24 | 13857620000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/45.prim_present_test.1203242170 | Oct 15 06:20:27 AM UTC 24 | Oct 15 06:22:48 AM UTC 24 | 14874420000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/48.prim_present_test.3912031529 | Oct 15 06:20:31 AM UTC 24 | Oct 15 06:23:01 AM UTC 24 | 15500000000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/0.prim_present_test.1825081705 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5330140000 ps |
| CPU time | 14.85 seconds |
| Started | Oct 15 06:18:31 AM UTC 24 |
| Finished | Oct 15 06:19:26 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825081705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1825081705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/1.prim_present_test.2942273072 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10017340000 ps |
| CPU time | 27.13 seconds |
| Started | Oct 15 06:18:31 AM UTC 24 |
| Finished | Oct 15 06:20:11 AM UTC 24 |
| Peak memory | 152064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942273072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2942273072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/10.prim_present_test.1680810324 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12071400000 ps |
| CPU time | 31.55 seconds |
| Started | Oct 15 06:18:43 AM UTC 24 |
| Finished | Oct 15 06:20:39 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680810324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1680810324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/11.prim_present_test.1452139190 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9671380000 ps |
| CPU time | 25.91 seconds |
| Started | Oct 15 06:18:46 AM UTC 24 |
| Finished | Oct 15 06:20:21 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452139190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1452139190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/12.prim_present_test.1250071472 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 15276180000 ps |
| CPU time | 38.87 seconds |
| Started | Oct 15 06:18:51 AM UTC 24 |
| Finished | Oct 15 06:21:14 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250071472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1250071472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/13.prim_present_test.707265943 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7115120000 ps |
| CPU time | 19.09 seconds |
| Started | Oct 15 06:18:54 AM UTC 24 |
| Finished | Oct 15 06:20:05 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707265943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.707265943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/14.prim_present_test.1455209045 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3618940000 ps |
| CPU time | 10.41 seconds |
| Started | Oct 15 06:18:55 AM UTC 24 |
| Finished | Oct 15 06:19:34 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455209045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1455209045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/15.prim_present_test.3680429473 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14610300000 ps |
| CPU time | 37.29 seconds |
| Started | Oct 15 06:19:02 AM UTC 24 |
| Finished | Oct 15 06:21:17 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680429473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3680429473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/16.prim_present_test.4005226786 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14021920000 ps |
| CPU time | 36.21 seconds |
| Started | Oct 15 06:19:02 AM UTC 24 |
| Finished | Oct 15 06:21:12 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005226786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.4005226786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/17.prim_present_test.2846072763 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14979820000 ps |
| CPU time | 38.43 seconds |
| Started | Oct 15 06:19:12 AM UTC 24 |
| Finished | Oct 15 06:21:30 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846072763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2846072763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/18.prim_present_test.1980925157 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6762960000 ps |
| CPU time | 17.94 seconds |
| Started | Oct 15 06:19:17 AM UTC 24 |
| Finished | Oct 15 06:20:23 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980925157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1980925157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/19.prim_present_test.1642002557 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7334600000 ps |
| CPU time | 19.15 seconds |
| Started | Oct 15 06:19:24 AM UTC 24 |
| Finished | Oct 15 06:20:33 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642002557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1642002557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/2.prim_present_test.861175559 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11610740000 ps |
| CPU time | 31.3 seconds |
| Started | Oct 15 06:18:32 AM UTC 24 |
| Finished | Oct 15 06:20:26 AM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861175559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.861175559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/20.prim_present_test.3053076327 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4671700000 ps |
| CPU time | 12.55 seconds |
| Started | Oct 15 06:19:27 AM UTC 24 |
| Finished | Oct 15 06:20:13 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053076327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3053076327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/21.prim_present_test.3584342030 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11987700000 ps |
| CPU time | 30.8 seconds |
| Started | Oct 15 06:19:27 AM UTC 24 |
| Finished | Oct 15 06:21:16 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584342030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3584342030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/22.prim_present_test.2654970499 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3817960000 ps |
| CPU time | 10.17 seconds |
| Started | Oct 15 06:19:30 AM UTC 24 |
| Finished | Oct 15 06:20:07 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654970499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2654970499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/23.prim_present_test.2296451933 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14686560000 ps |
| CPU time | 37.24 seconds |
| Started | Oct 15 06:19:33 AM UTC 24 |
| Finished | Oct 15 06:21:47 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296451933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2296451933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/24.prim_present_test.1096590835 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4899860000 ps |
| CPU time | 12.9 seconds |
| Started | Oct 15 06:19:34 AM UTC 24 |
| Finished | Oct 15 06:20:21 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096590835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1096590835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/25.prim_present_test.2878706938 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13929540000 ps |
| CPU time | 35.26 seconds |
| Started | Oct 15 06:19:40 AM UTC 24 |
| Finished | Oct 15 06:21:48 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878706938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2878706938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/26.prim_present_test.3889795475 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9117100000 ps |
| CPU time | 23.38 seconds |
| Started | Oct 15 06:19:42 AM UTC 24 |
| Finished | Oct 15 06:21:04 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889795475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3889795475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/27.prim_present_test.1709048969 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7904380000 ps |
| CPU time | 19.93 seconds |
| Started | Oct 15 06:19:42 AM UTC 24 |
| Finished | Oct 15 06:20:53 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709048969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1709048969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/28.prim_present_test.907626351 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8784160000 ps |
| CPU time | 22.08 seconds |
| Started | Oct 15 06:19:43 AM UTC 24 |
| Finished | Oct 15 06:21:02 AM UTC 24 |
| Peak memory | 152136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907626351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.907626351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/29.prim_present_test.887314780 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8804000000 ps |
| CPU time | 22.2 seconds |
| Started | Oct 15 06:19:43 AM UTC 24 |
| Finished | Oct 15 06:21:02 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887314780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.887314780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/3.prim_present_test.889126458 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5540940000 ps |
| CPU time | 15.28 seconds |
| Started | Oct 15 06:18:34 AM UTC 24 |
| Finished | Oct 15 06:19:32 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889126458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.889126458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/30.prim_present_test.538509739 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13258080000 ps |
| CPU time | 34.12 seconds |
| Started | Oct 15 06:19:45 AM UTC 24 |
| Finished | Oct 15 06:21:46 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538509739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.538509739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/31.prim_present_test.4069548138 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11097380000 ps |
| CPU time | 28.55 seconds |
| Started | Oct 15 06:19:52 AM UTC 24 |
| Finished | Oct 15 06:21:33 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069548138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4069548138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/32.prim_present_test.2040326781 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13784460000 ps |
| CPU time | 35.71 seconds |
| Started | Oct 15 06:19:54 AM UTC 24 |
| Finished | Oct 15 06:22:00 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040326781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2040326781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/33.prim_present_test.706364802 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4181280000 ps |
| CPU time | 10.88 seconds |
| Started | Oct 15 06:19:54 AM UTC 24 |
| Finished | Oct 15 06:20:32 AM UTC 24 |
| Peak memory | 152080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706364802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.706364802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/34.prim_present_test.4008718668 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5436160000 ps |
| CPU time | 14 seconds |
| Started | Oct 15 06:20:04 AM UTC 24 |
| Finished | Oct 15 06:20:52 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008718668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.4008718668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/35.prim_present_test.2093117924 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9476700000 ps |
| CPU time | 24.05 seconds |
| Started | Oct 15 06:20:06 AM UTC 24 |
| Finished | Oct 15 06:21:31 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093117924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2093117924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/36.prim_present_test.3491857042 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11603300000 ps |
| CPU time | 30.07 seconds |
| Started | Oct 15 06:20:08 AM UTC 24 |
| Finished | Oct 15 06:21:53 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491857042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3491857042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/37.prim_present_test.3667897872 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4450980000 ps |
| CPU time | 11.48 seconds |
| Started | Oct 15 06:20:12 AM UTC 24 |
| Finished | Oct 15 06:20:51 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667897872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3667897872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/38.prim_present_test.1068451518 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10566040000 ps |
| CPU time | 27.38 seconds |
| Started | Oct 15 06:20:14 AM UTC 24 |
| Finished | Oct 15 06:21:50 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068451518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1068451518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/39.prim_present_test.1806252298 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6295480000 ps |
| CPU time | 15.85 seconds |
| Started | Oct 15 06:20:20 AM UTC 24 |
| Finished | Oct 15 06:21:16 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806252298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1806252298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/4.prim_present_test.3428529375 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11297020000 ps |
| CPU time | 30.59 seconds |
| Started | Oct 15 06:18:34 AM UTC 24 |
| Finished | Oct 15 06:20:25 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428529375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3428529375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/40.prim_present_test.285110527 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9259700000 ps |
| CPU time | 24.09 seconds |
| Started | Oct 15 06:20:21 AM UTC 24 |
| Finished | Oct 15 06:21:46 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285110527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.285110527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/41.prim_present_test.1546825120 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10432740000 ps |
| CPU time | 27.37 seconds |
| Started | Oct 15 06:20:21 AM UTC 24 |
| Finished | Oct 15 06:21:57 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546825120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1546825120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/42.prim_present_test.3459687988 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14319520000 ps |
| CPU time | 37.55 seconds |
| Started | Oct 15 06:20:24 AM UTC 24 |
| Finished | Oct 15 06:22:38 AM UTC 24 |
| Peak memory | 152148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459687988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3459687988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/43.prim_present_test.3094679404 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7034520000 ps |
| CPU time | 17.85 seconds |
| Started | Oct 15 06:20:26 AM UTC 24 |
| Finished | Oct 15 06:21:29 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094679404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3094679404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/44.prim_present_test.3286586279 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12635600000 ps |
| CPU time | 33.03 seconds |
| Started | Oct 15 06:20:27 AM UTC 24 |
| Finished | Oct 15 06:22:26 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286586279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3286586279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/45.prim_present_test.1203242170 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14874420000 ps |
| CPU time | 39.29 seconds |
| Started | Oct 15 06:20:27 AM UTC 24 |
| Finished | Oct 15 06:22:48 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203242170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1203242170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/46.prim_present_test.4216489593 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6276880000 ps |
| CPU time | 16.26 seconds |
| Started | Oct 15 06:20:28 AM UTC 24 |
| Finished | Oct 15 06:21:24 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216489593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4216489593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/47.prim_present_test.2426172560 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6374220000 ps |
| CPU time | 16.69 seconds |
| Started | Oct 15 06:20:29 AM UTC 24 |
| Finished | Oct 15 06:21:27 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426172560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2426172560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/48.prim_present_test.3912031529 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15500000000 ps |
| CPU time | 41.91 seconds |
| Started | Oct 15 06:20:31 AM UTC 24 |
| Finished | Oct 15 06:23:01 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912031529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3912031529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/49.prim_present_test.2857084026 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13857620000 ps |
| CPU time | 36.53 seconds |
| Started | Oct 15 06:20:33 AM UTC 24 |
| Finished | Oct 15 06:22:45 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857084026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2857084026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/5.prim_present_test.917409632 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11510300000 ps |
| CPU time | 31.11 seconds |
| Started | Oct 15 06:18:34 AM UTC 24 |
| Finished | Oct 15 06:20:27 AM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917409632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.917409632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/6.prim_present_test.229952979 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13075800000 ps |
| CPU time | 34.74 seconds |
| Started | Oct 15 06:18:34 AM UTC 24 |
| Finished | Oct 15 06:20:40 AM UTC 24 |
| Peak memory | 152160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229952979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.229952979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/7.prim_present_test.4207238343 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 6281220000 ps |
| CPU time | 17.25 seconds |
| Started | Oct 15 06:18:40 AM UTC 24 |
| Finished | Oct 15 06:19:44 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207238343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.4207238343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/8.prim_present_test.2467072439 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3348000000 ps |
| CPU time | 9.46 seconds |
| Started | Oct 15 06:18:41 AM UTC 24 |
| Finished | Oct 15 06:19:16 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467072439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2467072439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default/9.prim_present_test.1883030428 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 15254480000 ps |
| CPU time | 39.57 seconds |
| Started | Oct 15 06:18:43 AM UTC 24 |
| Finished | Oct 15 06:21:05 AM UTC 24 |
| Peak memory | 152144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883030428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1883030428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |