| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/0.prim_present_test.2303256920 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/1.prim_present_test.4249680129 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/10.prim_present_test.3157923176 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/11.prim_present_test.1471956793 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/12.prim_present_test.1990281514 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/13.prim_present_test.955093076 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/14.prim_present_test.2569758560 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/15.prim_present_test.1414461525 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/16.prim_present_test.3454881417 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/17.prim_present_test.539934387 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/18.prim_present_test.3667911212 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/19.prim_present_test.3326108476 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/2.prim_present_test.334052927 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/20.prim_present_test.824931012 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/21.prim_present_test.833492210 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/22.prim_present_test.939379854 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/23.prim_present_test.1303575757 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/24.prim_present_test.1923136581 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/25.prim_present_test.679262475 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/26.prim_present_test.1502539174 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/27.prim_present_test.867203627 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/28.prim_present_test.3865625369 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/29.prim_present_test.2211220957 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/3.prim_present_test.1475439353 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/30.prim_present_test.155000302 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/31.prim_present_test.1965345371 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/32.prim_present_test.810289856 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/33.prim_present_test.2484133417 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/34.prim_present_test.3272419261 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/35.prim_present_test.1102659277 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/36.prim_present_test.3436377155 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/37.prim_present_test.923722494 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/38.prim_present_test.3323660810 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/39.prim_present_test.1594628637 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/4.prim_present_test.2213043606 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/40.prim_present_test.4022498838 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/41.prim_present_test.2362245813 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/42.prim_present_test.2386144996 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/43.prim_present_test.4135971257 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/44.prim_present_test.3824490405 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/45.prim_present_test.1547969326 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/46.prim_present_test.654202473 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/47.prim_present_test.454893941 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/48.prim_present_test.1550473872 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/49.prim_present_test.3449387333 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/5.prim_present_test.3093753112 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/6.prim_present_test.2784631098 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/7.prim_present_test.370253456 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/8.prim_present_test.3838399493 |
| /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/9.prim_present_test.1910685543 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/3.prim_present_test.1475439353 | Feb 08 07:34:29 AM UTC 25 | Feb 08 07:35:11 AM UTC 25 | 6128700000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/1.prim_present_test.4249680129 | Feb 08 07:34:28 AM UTC 25 | Feb 08 07:35:23 AM UTC 25 | 7991800000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/4.prim_present_test.2213043606 | Feb 08 07:34:30 AM UTC 25 | Feb 08 07:35:49 AM UTC 25 | 11475580000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/0.prim_present_test.2303256920 | Feb 08 07:34:27 AM UTC 25 | Feb 08 07:35:50 AM UTC 25 | 11997620000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/2.prim_present_test.334052927 | Feb 08 07:34:29 AM UTC 25 | Feb 08 07:35:56 AM UTC 25 | 12688300000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/6.prim_present_test.2784631098 | Feb 08 07:35:24 AM UTC 25 | Feb 08 07:35:57 AM UTC 25 | 4615280000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/5.prim_present_test.3093753112 | Feb 08 07:35:12 AM UTC 25 | Feb 08 07:36:14 AM UTC 25 | 8755020000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/7.prim_present_test.370253456 | Feb 08 07:35:30 AM UTC 25 | Feb 08 07:36:24 AM UTC 25 | 7653900000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/8.prim_present_test.3838399493 | Feb 08 07:35:49 AM UTC 25 | Feb 08 07:36:35 AM UTC 25 | 6301680000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/10.prim_present_test.3157923176 | Feb 08 07:35:56 AM UTC 25 | Feb 08 07:36:57 AM UTC 25 | 8706660000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/12.prim_present_test.1990281514 | Feb 08 07:36:08 AM UTC 25 | Feb 08 07:36:57 AM UTC 25 | 7055600000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/11.prim_present_test.1471956793 | Feb 08 07:35:58 AM UTC 25 | Feb 08 07:37:18 AM UTC 25 | 11419780000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/17.prim_present_test.539934387 | Feb 08 07:36:58 AM UTC 25 | Feb 08 07:37:25 AM UTC 25 | 3728060000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/9.prim_present_test.1910685543 | Feb 08 07:35:50 AM UTC 25 | Feb 08 07:37:27 AM UTC 25 | 13798720000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/13.prim_present_test.955093076 | Feb 08 07:36:15 AM UTC 25 | Feb 08 07:37:41 AM UTC 25 | 12527100000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/14.prim_present_test.2569758560 | Feb 08 07:36:26 AM UTC 25 | Feb 08 07:37:44 AM UTC 25 | 11386920000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/21.prim_present_test.833492210 | Feb 08 07:37:42 AM UTC 25 | Feb 08 07:38:07 AM UTC 25 | 3488120000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/16.prim_present_test.3454881417 | Feb 08 07:36:58 AM UTC 25 | Feb 08 07:38:09 AM UTC 25 | 10324860000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/15.prim_present_test.1414461525 | Feb 08 07:36:36 AM UTC 25 | Feb 08 07:38:15 AM UTC 25 | 14501800000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/19.prim_present_test.3326108476 | Feb 08 07:37:26 AM UTC 25 | Feb 08 07:38:30 AM UTC 25 | 9214440000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/18.prim_present_test.3667911212 | Feb 08 07:37:18 AM UTC 25 | Feb 08 07:38:33 AM UTC 25 | 10918820000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/22.prim_present_test.939379854 | Feb 08 07:37:45 AM UTC 25 | Feb 08 07:38:57 AM UTC 25 | 10463740000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/20.prim_present_test.824931012 | Feb 08 07:37:27 AM UTC 25 | Feb 08 07:39:06 AM UTC 25 | 14455920000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/24.prim_present_test.1923136581 | Feb 08 07:38:10 AM UTC 25 | Feb 08 07:39:21 AM UTC 25 | 10312460000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/23.prim_present_test.1303575757 | Feb 08 07:38:08 AM UTC 25 | Feb 08 07:39:30 AM UTC 25 | 11830840000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/30.prim_present_test.155000302 | Feb 08 07:39:07 AM UTC 25 | Feb 08 07:39:34 AM UTC 25 | 3840280000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/27.prim_present_test.867203627 | Feb 08 07:38:33 AM UTC 25 | Feb 08 07:39:40 AM UTC 25 | 9627360000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/31.prim_present_test.1965345371 | Feb 08 07:39:22 AM UTC 25 | Feb 08 07:39:45 AM UTC 25 | 3215940000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/28.prim_present_test.3865625369 | Feb 08 07:38:43 AM UTC 25 | Feb 08 07:39:46 AM UTC 25 | 9087340000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/26.prim_present_test.1502539174 | Feb 08 07:38:31 AM UTC 25 | Feb 08 07:39:49 AM UTC 25 | 11354680000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/25.prim_present_test.679262475 | Feb 08 07:38:16 AM UTC 25 | Feb 08 07:39:52 AM UTC 25 | 14088260000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/29.prim_present_test.2211220957 | Feb 08 07:38:58 AM UTC 25 | Feb 08 07:40:01 AM UTC 25 | 9246060000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/33.prim_present_test.2484133417 | Feb 08 07:39:35 AM UTC 25 | Feb 08 07:40:10 AM UTC 25 | 5018900000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/36.prim_present_test.3436377155 | Feb 08 07:39:47 AM UTC 25 | Feb 08 07:40:13 AM UTC 25 | 3604060000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/34.prim_present_test.3272419261 | Feb 08 07:39:41 AM UTC 25 | Feb 08 07:40:19 AM UTC 25 | 5405780000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/32.prim_present_test.810289856 | Feb 08 07:39:31 AM UTC 25 | Feb 08 07:40:31 AM UTC 25 | 8736420000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/40.prim_present_test.4022498838 | Feb 08 07:40:11 AM UTC 25 | Feb 08 07:40:35 AM UTC 25 | 3215940000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/41.prim_present_test.2362245813 | Feb 08 07:40:14 AM UTC 25 | Feb 08 07:40:51 AM UTC 25 | 5116240000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/35.prim_present_test.1102659277 | Feb 08 07:39:46 AM UTC 25 | Feb 08 07:41:00 AM UTC 25 | 10683220000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/39.prim_present_test.1594628637 | Feb 08 07:40:02 AM UTC 25 | Feb 08 07:41:01 AM UTC 25 | 8503920000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/37.prim_present_test.923722494 | Feb 08 07:39:50 AM UTC 25 | Feb 08 07:41:08 AM UTC 25 | 11279040000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/42.prim_present_test.2386144996 | Feb 08 07:40:20 AM UTC 25 | Feb 08 07:41:18 AM UTC 25 | 8398520000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/43.prim_present_test.4135971257 | Feb 08 07:40:32 AM UTC 25 | Feb 08 07:41:28 AM UTC 25 | 7878960000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/38.prim_present_test.3323660810 | Feb 08 07:39:53 AM UTC 25 | Feb 08 07:41:31 AM UTC 25 | 14206680000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/44.prim_present_test.3824490405 | Feb 08 07:40:35 AM UTC 25 | Feb 08 07:41:41 AM UTC 25 | 9319840000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/45.prim_present_test.1547969326 | Feb 08 07:40:52 AM UTC 25 | Feb 08 07:41:58 AM UTC 25 | 9591400000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/47.prim_present_test.454893941 | Feb 08 07:41:02 AM UTC 25 | Feb 08 07:42:13 AM UTC 25 | 10323000000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/46.prim_present_test.654202473 | Feb 08 07:41:01 AM UTC 25 | Feb 08 07:42:14 AM UTC 25 | 10611920000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/48.prim_present_test.1550473872 | Feb 08 07:41:09 AM UTC 25 | Feb 08 07:42:24 AM UTC 25 | 10864880000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/49.prim_present_test.3449387333 | Feb 08 07:41:19 AM UTC 25 | Feb 08 07:42:28 AM UTC 25 | 10037800000 ps |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/0.prim_present_test.2303256920 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11997620000 ps |
| CPU time | 28.38 seconds |
| Started | Feb 08 07:34:27 AM UTC 25 |
| Finished | Feb 08 07:35:50 AM UTC 25 |
| Peak memory | 152152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303256920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. prim_present_test.2303256920 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/0.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/1.prim_present_test.4249680129 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7991800000 ps |
| CPU time | 19.59 seconds |
| Started | Feb 08 07:34:28 AM UTC 25 |
| Finished | Feb 08 07:35:23 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249680129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. prim_present_test.4249680129 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/1.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/10.prim_present_test.3157923176 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8706660000 ps |
| CPU time | 20.35 seconds |
| Started | Feb 08 07:35:56 AM UTC 25 |
| Finished | Feb 08 07:36:57 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157923176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10 .prim_present_test.3157923176 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/10.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/11.prim_present_test.1471956793 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11419780000 ps |
| CPU time | 26.57 seconds |
| Started | Feb 08 07:35:58 AM UTC 25 |
| Finished | Feb 08 07:37:18 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471956793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11 .prim_present_test.1471956793 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/11.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/12.prim_present_test.1990281514 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7055600000 ps |
| CPU time | 16.65 seconds |
| Started | Feb 08 07:36:08 AM UTC 25 |
| Finished | Feb 08 07:36:57 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990281514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12 .prim_present_test.1990281514 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/12.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/13.prim_present_test.955093076 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12527100000 ps |
| CPU time | 29.04 seconds |
| Started | Feb 08 07:36:15 AM UTC 25 |
| Finished | Feb 08 07:37:41 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955093076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13. prim_present_test.955093076 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/13.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/14.prim_present_test.2569758560 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11386920000 ps |
| CPU time | 26.47 seconds |
| Started | Feb 08 07:36:26 AM UTC 25 |
| Finished | Feb 08 07:37:44 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569758560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14 .prim_present_test.2569758560 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/14.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/15.prim_present_test.1414461525 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14501800000 ps |
| CPU time | 33.41 seconds |
| Started | Feb 08 07:36:36 AM UTC 25 |
| Finished | Feb 08 07:38:15 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414461525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15 .prim_present_test.1414461525 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/15.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/16.prim_present_test.3454881417 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10324860000 ps |
| CPU time | 23.87 seconds |
| Started | Feb 08 07:36:58 AM UTC 25 |
| Finished | Feb 08 07:38:09 AM UTC 25 |
| Peak memory | 152132 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454881417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .prim_present_test.3454881417 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/16.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/17.prim_present_test.539934387 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3728060000 ps |
| CPU time | 9.03 seconds |
| Started | Feb 08 07:36:58 AM UTC 25 |
| Finished | Feb 08 07:37:25 AM UTC 25 |
| Peak memory | 152068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539934387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17. prim_present_test.539934387 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/17.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/18.prim_present_test.3667911212 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10918820000 ps |
| CPU time | 25.38 seconds |
| Started | Feb 08 07:37:18 AM UTC 25 |
| Finished | Feb 08 07:38:33 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667911212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18 .prim_present_test.3667911212 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/18.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/19.prim_present_test.3326108476 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9214440000 ps |
| CPU time | 22.27 seconds |
| Started | Feb 08 07:37:26 AM UTC 25 |
| Finished | Feb 08 07:38:30 AM UTC 25 |
| Peak memory | 152164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326108476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19 .prim_present_test.3326108476 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/19.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/2.prim_present_test.334052927 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12688300000 ps |
| CPU time | 29.97 seconds |
| Started | Feb 08 07:34:29 AM UTC 25 |
| Finished | Feb 08 07:35:56 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334052927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.p rim_present_test.334052927 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/2.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/20.prim_present_test.824931012 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14455920000 ps |
| CPU time | 33.41 seconds |
| Started | Feb 08 07:37:27 AM UTC 25 |
| Finished | Feb 08 07:39:06 AM UTC 25 |
| Peak memory | 152152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824931012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20. prim_present_test.824931012 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/20.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/21.prim_present_test.833492210 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3488120000 ps |
| CPU time | 8.45 seconds |
| Started | Feb 08 07:37:42 AM UTC 25 |
| Finished | Feb 08 07:38:07 AM UTC 25 |
| Peak memory | 152092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833492210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21. prim_present_test.833492210 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/21.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/22.prim_present_test.939379854 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10463740000 ps |
| CPU time | 24.6 seconds |
| Started | Feb 08 07:37:45 AM UTC 25 |
| Finished | Feb 08 07:38:57 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939379854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22. prim_present_test.939379854 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/22.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/23.prim_present_test.1303575757 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11830840000 ps |
| CPU time | 28.01 seconds |
| Started | Feb 08 07:38:08 AM UTC 25 |
| Finished | Feb 08 07:39:30 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303575757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23 .prim_present_test.1303575757 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/23.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/24.prim_present_test.1923136581 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10312460000 ps |
| CPU time | 23.8 seconds |
| Started | Feb 08 07:38:10 AM UTC 25 |
| Finished | Feb 08 07:39:21 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923136581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24 .prim_present_test.1923136581 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/24.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/25.prim_present_test.679262475 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14088260000 ps |
| CPU time | 32.32 seconds |
| Started | Feb 08 07:38:16 AM UTC 25 |
| Finished | Feb 08 07:39:52 AM UTC 25 |
| Peak memory | 152152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679262475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25. prim_present_test.679262475 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/25.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/26.prim_present_test.1502539174 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11354680000 ps |
| CPU time | 26.19 seconds |
| Started | Feb 08 07:38:31 AM UTC 25 |
| Finished | Feb 08 07:39:49 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502539174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26 .prim_present_test.1502539174 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/26.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/27.prim_present_test.867203627 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9627360000 ps |
| CPU time | 22.42 seconds |
| Started | Feb 08 07:38:33 AM UTC 25 |
| Finished | Feb 08 07:39:40 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867203627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27. prim_present_test.867203627 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/27.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/28.prim_present_test.3865625369 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9087340000 ps |
| CPU time | 21.43 seconds |
| Started | Feb 08 07:38:43 AM UTC 25 |
| Finished | Feb 08 07:39:46 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865625369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28 .prim_present_test.3865625369 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/28.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/29.prim_present_test.2211220957 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9246060000 ps |
| CPU time | 21.39 seconds |
| Started | Feb 08 07:38:58 AM UTC 25 |
| Finished | Feb 08 07:40:01 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211220957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29 .prim_present_test.2211220957 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/29.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/3.prim_present_test.1475439353 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6128700000 ps |
| CPU time | 15.17 seconds |
| Started | Feb 08 07:34:29 AM UTC 25 |
| Finished | Feb 08 07:35:11 AM UTC 25 |
| Peak memory | 152220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475439353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3. prim_present_test.1475439353 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/3.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/30.prim_present_test.155000302 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3840280000 ps |
| CPU time | 9.41 seconds |
| Started | Feb 08 07:39:07 AM UTC 25 |
| Finished | Feb 08 07:39:34 AM UTC 25 |
| Peak memory | 152084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155000302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30. prim_present_test.155000302 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/30.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/31.prim_present_test.1965345371 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3215940000 ps |
| CPU time | 7.83 seconds |
| Started | Feb 08 07:39:22 AM UTC 25 |
| Finished | Feb 08 07:39:45 AM UTC 25 |
| Peak memory | 152084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965345371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31 .prim_present_test.1965345371 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/31.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/32.prim_present_test.810289856 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8736420000 ps |
| CPU time | 20.69 seconds |
| Started | Feb 08 07:39:31 AM UTC 25 |
| Finished | Feb 08 07:40:31 AM UTC 25 |
| Peak memory | 152152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810289856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32. prim_present_test.810289856 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/32.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/33.prim_present_test.2484133417 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5018900000 ps |
| CPU time | 11.88 seconds |
| Started | Feb 08 07:39:35 AM UTC 25 |
| Finished | Feb 08 07:40:10 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484133417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33 .prim_present_test.2484133417 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/33.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/34.prim_present_test.3272419261 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5405780000 ps |
| CPU time | 13.05 seconds |
| Started | Feb 08 07:39:41 AM UTC 25 |
| Finished | Feb 08 07:40:19 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272419261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34 .prim_present_test.3272419261 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/34.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/35.prim_present_test.1102659277 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10683220000 ps |
| CPU time | 24.63 seconds |
| Started | Feb 08 07:39:46 AM UTC 25 |
| Finished | Feb 08 07:41:00 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102659277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35 .prim_present_test.1102659277 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/35.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/36.prim_present_test.3436377155 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3604060000 ps |
| CPU time | 8.63 seconds |
| Started | Feb 08 07:39:47 AM UTC 25 |
| Finished | Feb 08 07:40:13 AM UTC 25 |
| Peak memory | 152084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436377155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36 .prim_present_test.3436377155 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/36.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/37.prim_present_test.923722494 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11279040000 ps |
| CPU time | 26.26 seconds |
| Started | Feb 08 07:39:50 AM UTC 25 |
| Finished | Feb 08 07:41:08 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923722494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37. prim_present_test.923722494 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/37.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/38.prim_present_test.3323660810 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14206680000 ps |
| CPU time | 33.24 seconds |
| Started | Feb 08 07:39:53 AM UTC 25 |
| Finished | Feb 08 07:41:31 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323660810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38 .prim_present_test.3323660810 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/38.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/39.prim_present_test.1594628637 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8503920000 ps |
| CPU time | 19.8 seconds |
| Started | Feb 08 07:40:02 AM UTC 25 |
| Finished | Feb 08 07:41:01 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594628637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39 .prim_present_test.1594628637 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/39.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/4.prim_present_test.2213043606 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11475580000 ps |
| CPU time | 27.24 seconds |
| Started | Feb 08 07:34:30 AM UTC 25 |
| Finished | Feb 08 07:35:49 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213043606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4. prim_present_test.2213043606 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/4.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/40.prim_present_test.4022498838 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3215940000 ps |
| CPU time | 7.75 seconds |
| Started | Feb 08 07:40:11 AM UTC 25 |
| Finished | Feb 08 07:40:35 AM UTC 25 |
| Peak memory | 152084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022498838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40 .prim_present_test.4022498838 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/40.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/41.prim_present_test.2362245813 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5116240000 ps |
| CPU time | 12.37 seconds |
| Started | Feb 08 07:40:14 AM UTC 25 |
| Finished | Feb 08 07:40:51 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362245813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41 .prim_present_test.2362245813 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/41.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/42.prim_present_test.2386144996 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8398520000 ps |
| CPU time | 19.45 seconds |
| Started | Feb 08 07:40:20 AM UTC 25 |
| Finished | Feb 08 07:41:18 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386144996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42 .prim_present_test.2386144996 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/42.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/43.prim_present_test.4135971257 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7878960000 ps |
| CPU time | 18.81 seconds |
| Started | Feb 08 07:40:32 AM UTC 25 |
| Finished | Feb 08 07:41:28 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135971257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43 .prim_present_test.4135971257 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/43.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/44.prim_present_test.3824490405 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9319840000 ps |
| CPU time | 22.3 seconds |
| Started | Feb 08 07:40:35 AM UTC 25 |
| Finished | Feb 08 07:41:41 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824490405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44 .prim_present_test.3824490405 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/44.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/45.prim_present_test.1547969326 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9591400000 ps |
| CPU time | 22.2 seconds |
| Started | Feb 08 07:40:52 AM UTC 25 |
| Finished | Feb 08 07:41:58 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547969326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45 .prim_present_test.1547969326 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/45.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/46.prim_present_test.654202473 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10611920000 ps |
| CPU time | 24.47 seconds |
| Started | Feb 08 07:41:01 AM UTC 25 |
| Finished | Feb 08 07:42:14 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654202473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46. prim_present_test.654202473 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/46.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/47.prim_present_test.454893941 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10323000000 ps |
| CPU time | 23.88 seconds |
| Started | Feb 08 07:41:02 AM UTC 25 |
| Finished | Feb 08 07:42:13 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454893941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47. prim_present_test.454893941 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/47.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/48.prim_present_test.1550473872 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10864880000 ps |
| CPU time | 25.49 seconds |
| Started | Feb 08 07:41:09 AM UTC 25 |
| Finished | Feb 08 07:42:24 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550473872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48 .prim_present_test.1550473872 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/48.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/49.prim_present_test.3449387333 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10037800000 ps |
| CPU time | 23.37 seconds |
| Started | Feb 08 07:41:19 AM UTC 25 |
| Finished | Feb 08 07:42:28 AM UTC 25 |
| Peak memory | 152148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449387333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49 .prim_present_test.3449387333 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/49.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/5.prim_present_test.3093753112 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8755020000 ps |
| CPU time | 20.67 seconds |
| Started | Feb 08 07:35:12 AM UTC 25 |
| Finished | Feb 08 07:36:14 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093753112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5. prim_present_test.3093753112 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/5.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/6.prim_present_test.2784631098 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4615280000 ps |
| CPU time | 11.11 seconds |
| Started | Feb 08 07:35:24 AM UTC 25 |
| Finished | Feb 08 07:35:57 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784631098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6. prim_present_test.2784631098 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/6.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/7.prim_present_test.370253456 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7653900000 ps |
| CPU time | 18.58 seconds |
| Started | Feb 08 07:35:30 AM UTC 25 |
| Finished | Feb 08 07:36:24 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370253456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.p rim_present_test.370253456 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/7.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/8.prim_present_test.3838399493 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6301680000 ps |
| CPU time | 15.02 seconds |
| Started | Feb 08 07:35:49 AM UTC 25 |
| Finished | Feb 08 07:36:35 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838399493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8. prim_present_test.3838399493 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/8.prim_present_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default/9.prim_present_test.1910685543 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13798720000 ps |
| CPU time | 33.08 seconds |
| Started | Feb 08 07:35:50 AM UTC 25 |
| Finished | Feb 08 07:37:27 AM UTC 25 |
| Peak memory | 152156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910685543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9. prim_present_test.1910685543 |
| Directory | /workspaces/repo/scratch/os_regression/prim_present-sim-vcs/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |