Unified Coverage Report :: Module Instance :: prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[3].dut

Module Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[3].dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_prince_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[4].dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_prince_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[3].dut

	Line No.	Total	Covered	Percent
TOTAL		73	73	100.00
ALWAYS	56	7	7	100.00
CONT_ASSIGN	70	1	1	100.00
ALWAYS	85	8	8	100.00
ALWAYS	114	3	3	100.00
ALWAYS	124	3	3	100.00
ALWAYS	124	3	3	100.00
ALWAYS	124	3	3	100.00
ALWAYS	124	3	3	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
ALWAYS	154	3	3	100.00
ALWAYS	173	6	6	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
ALWAYS	208	3	3	100.00
ALWAYS	208	3	3	100.00
ALWAYS	208	3	3	100.00
ALWAYS	208	3	3	100.00
ALWAYS	227	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
61	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
70	1	1
85	1	1
86	1	1
87	1	1
88	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
114	1	1
115	1	1
116	1	1
124	1	1
126	1	1
127	1	1
124	1	1
126	1	1
127	1	1
124	1	1
126	1	1
127	1	1
124	1	1
126	1	1
127	1	1
140	4	4
144	2	2
146	2	2
154	1	1
156	1	1
157	1	1
173	1	1
174	1	1
175	1	1
177	1	1
178	1	1
179	1	1
			MISSING_ELSE
183	1	1
190	1	1
197	2	2
199	2	2
202	4	4
208	1	1
210	1	1
211	1	1
208	1	1
210	1	1
211	1	1
208	1	1
210	1	1
211	1	1
208	1	1
210	1	1
211	1	1
227	1	1
229	1	1
230	1	1

---

Cond Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[3].dut

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       57
 SUB-EXPRESSION (k0[(DataWidth - 1)] ^ k0[1])
                 ---------1---------   --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[3].dut

	Total	Covered	Percent
Totals	8	8	100.00
Total Bits	522	522	100.00
Total Bits 0->1	261	261	100.00
Total Bits 1->0	261	261	100.00

Ports	8	8	100.00
Port Bits	522	522	100.00
Port Bits 0->1	261	261	100.00
Port Bits 1->0	261	261	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
valid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
key_i[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
dec_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
valid_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

Branch Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[3].dut

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	61	2	2	100.00
IF	85	3	3	100.00
IF	173	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if (dec_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	if ((!rst_ni))
-2-:	90	if (valid_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	173	if ((!rst_ni))
-2-:	178	if (valid_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[3].dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumRounds_A	500	500	0	0
SupportedWidths_A	500	500	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500	500	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500	500	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[4].dut

	Line No.	Total	Covered	Percent
TOTAL		83	83	100.00
ALWAYS	56	7	7	100.00
CONT_ASSIGN	70	1	1	100.00
ALWAYS	85	8	8	100.00
ALWAYS	114	3	3	100.00
ALWAYS	124	3	3	100.00
ALWAYS	124	3	3	100.00
ALWAYS	124	3	3	100.00
ALWAYS	124	3	3	100.00
ALWAYS	124	3	3	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
ALWAYS	154	3	3	100.00
ALWAYS	173	6	6	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
ALWAYS	208	3	3	100.00
ALWAYS	208	3	3	100.00
ALWAYS	208	3	3	100.00
ALWAYS	208	3	3	100.00
ALWAYS	208	3	3	100.00
ALWAYS	227	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
61	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
70	1	1
85	1	1
86	1	1
87	1	1
88	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
114	1	1
115	1	1
116	1	1
124	1	1
126	1	1
127	1	1
124	1	1
126	1	1
127	1	1
124	1	1
126	1	1
127	1	1
124	1	1
126	1	1
127	1	1
124	1	1
126	1	1
127	1	1
140	5	5
144	3	3
146	2	2
154	1	1
156	1	1
157	1	1
173	1	1
174	1	1
175	1	1
177	1	1
178	1	1
179	1	1
			MISSING_ELSE
183	1	1
190	1	1
197	3	3
199	2	2
202	5	5
208	1	1
210	1	1
211	1	1
208	1	1
210	1	1
211	1	1
208	1	1
210	1	1
211	1	1
208	1	1
210	1	1
211	1	1
208	1	1
210	1	1
211	1	1
227	1	1
229	1	1
230	1	1

---

Cond Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[4].dut

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       57
 SUB-EXPRESSION (k0[(DataWidth - 1)] ^ k0[1])
                 ---------1---------   --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[4].dut

	Total	Covered	Percent
Totals	8	8	100.00
Total Bits	522	522	100.00
Total Bits 0->1	261	261	100.00
Total Bits 1->0	261	261	100.00

Ports	8	8	100.00
Port Bits	522	522	100.00
Port Bits 0->1	261	261	100.00
Port Bits 1->0	261	261	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
valid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
key_i[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
dec_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
valid_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

Branch Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[4].dut

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	61	2	2	100.00
IF	85	3	3	100.00
IF	173	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if (dec_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	if ((!rst_ni))
-2-:	90	if (valid_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	173	if ((!rst_ni))
-2-:	178	if (valid_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : prim_prince_tb.gen_new_key_schedule[1].gen_registered_variant[1].gen_duts[4].dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumRounds_A	500	500	0	0
SupportedWidths_A	500	500	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500	500	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500	500	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0