PWM Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	524.231us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	34.211us	5	5	100.00
V1	csr_rw	pwm_csr_rw	4.000s	53.355us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	12.000s	3.282ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	320.683us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	5.000s	28.156us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	4.000s	53.355us	20	20	100.00
		pwm_csr_aliasing	5.000s	320.683us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.450m	41.992ms	49	50	98.00
V2	pulse	pwm_rand_output	1.450m	41.992ms	49	50	98.00
V2	blink	pwm_rand_output	1.450m	41.992ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.450m	41.992ms	49	50	98.00
V2	resolution	pwm_rand_output	1.450m	41.992ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.450m	41.992ms	49	50	98.00
V2	polarity	pwm_rand_output	1.450m	41.992ms	49	50	98.00
V2	phase	pwm_rand_output	1.450m	41.992ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.450m	41.992ms	49	50	98.00
V2	perf	pwm_perf	51.000s	41.991ms	49	50	98.00
V2	stress_all	pwm_stress_all	4.467m	66.841ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	51.525us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	38.700us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	8.000s	146.222us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	8.000s	146.222us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	34.211us	5	5	100.00
		pwm_csr_rw	4.000s	53.355us	20	20	100.00
		pwm_csr_aliasing	5.000s	320.683us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	60.970us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	34.211us	5	5	100.00
		pwm_csr_rw	4.000s	53.355us	20	20	100.00
		pwm_csr_aliasing	5.000s	320.683us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	60.970us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	481.546us	20	20	100.00
		pwm_sec_cm	3.000s	745.039us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	481.546us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			416	420	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.51	99.53	99.14	99.88	94.93	94.92	--	100.00	99.34

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

3.pwm_stress_all.458349003
Line 552, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/3.pwm_stress_all/latest/run.log

  UVM_ERROR @ 32915091828 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 32915091828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.pwm_stress_all.3340432714
Line 191797, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/26.pwm_stress_all/latest/run.log

  UVM_ERROR @ 54170250182 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 54170250182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test pwm_perf has 1 failures.

21.pwm_perf.486199134
Line 280, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/21.pwm_perf/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwm_rand_output has 1 failures.

28.pwm_rand_output.2273258099
Line 166897, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/28.pwm_rand_output/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---