9f20940d49| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 9.000s | 4.241ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 17.655us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 14.953us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 9.000s | 644.550us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 102.666us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 74.302us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 14.953us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 5.000s | 102.666us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 3.117m | 21.878ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 3.117m | 21.878ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 3.117m | 21.878ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 3.117m | 21.878ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 3.117m | 21.878ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 3.117m | 21.878ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 3.117m | 21.878ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 3.117m | 21.878ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 3.117m | 21.878ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 1.717m | 36.206ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 6.267m | 87.503ms | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 4.000s | 12.065us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 34.312us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 442.173us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 442.173us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 17.655us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 14.953us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 102.666us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 134.822us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 17.655us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 14.953us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 102.666us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 134.822us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 4.000s | 175.438us | 20 | 20 | 100.00 |
| pwm_sec_cm | 4.000s | 198.491us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 4.000s | 175.438us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 417 | 420 | 99.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.66 | 99.66 | 99.38 | 100.00 | 95.27 | 94.92 | -- | 100.00 | 99.01 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test pwm_rand_output has 1 failures.
25.pwm_rand_output.112525107507239468054767635972989478906074364524259728913228026403639978374243
Line 212, in log /workspaces/repo/scratch/os_regression/pwm-sim-xcelium/25.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_perf has 1 failures.
48.pwm_perf.49094867459129570423978438177566697965216669317809914798764906965898030062938
Line 142, in log /workspaces/repo/scratch/os_regression/pwm-sim-xcelium/48.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
7.pwm_stress_all.82113294536957204433747663436641099205942489035330915306374179423360160819458
Line 355913, in log /workspaces/repo/scratch/os_regression/pwm-sim-xcelium/7.pwm_stress_all/latest/run.log
UVM_ERROR @ 70078937790 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 70078937790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---