41bc3e0c7f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 6.000s | 1.084ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 17.659us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 53.762us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 883.147us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 185.213us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 94.402us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 53.762us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 185.213us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.050m | 21.436ms | 47 | 50 | 94.00 |
| V2 | pulse | pwm_rand_output | 1.050m | 21.436ms | 47 | 50 | 94.00 |
| V2 | blink | pwm_rand_output | 1.050m | 21.436ms | 47 | 50 | 94.00 |
| V2 | heartbeat | pwm_rand_output | 1.050m | 21.436ms | 47 | 50 | 94.00 |
| V2 | resolution | pwm_rand_output | 1.050m | 21.436ms | 47 | 50 | 94.00 |
| V2 | multi_channel | pwm_rand_output | 1.050m | 21.436ms | 47 | 50 | 94.00 |
| V2 | polarity | pwm_rand_output | 1.050m | 21.436ms | 47 | 50 | 94.00 |
| V2 | phase | pwm_rand_output | 1.050m | 21.436ms | 47 | 50 | 94.00 |
| V2 | lowpower | pwm_rand_output | 1.050m | 21.436ms | 47 | 50 | 94.00 |
| V2 | perf | pwm_perf | 49.000s | 10.827ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 5.017m | 167.966ms | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 16.802us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 44.250us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 5.000s | 355.544us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 5.000s | 355.544us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 17.659us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 53.762us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 185.213us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 59.614us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 17.659us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 53.762us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 185.213us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 59.614us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 546.363us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 76.483us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 546.363us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 415 | 420 | 98.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.31 | 99.31 | 98.77 | 99.72 | 94.83 | 94.92 | -- | 100.00 | 99.01 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test pwm_rand_output has 2 failures.
31.pwm_rand_output.19548337089837495451273154142168240053303598250611176108579147496380130645079
Line 401, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/31.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.pwm_rand_output.51332443619871703671550429940333319958505534785169623113573819317586969309796
Line 2768, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/46.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_perf has 1 failures.
49.pwm_perf.23726445733238767172296879183577360241929774450555888775604416086257624483904
Line 329, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/49.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:
Test pwm_rand_output has 1 failures.
0.pwm_rand_output.100791056447776474717735356484362040811315358124411176788659479058333589770139
Line 886709, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/0.pwm_rand_output/latest/run.log
UVM_ERROR @ 5973287099 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 5973287099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_stress_all has 1 failures.
17.pwm_stress_all.65512795919410800599072032719573763146424090950321031815946233441953464400168
Line 726, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/17.pwm_stress_all/latest/run.log
UVM_ERROR @ 42926889107 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 42926889107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---