PWM Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: XCELIUM

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	1.167m	1.040ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	54.000s	20.125us	5	5	100.00
V1	csr_rw	pwm_csr_rw	54.000s	46.292us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	1.067m	518.968us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	54.000s	82.551us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	53.000s	22.209us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	54.000s	46.292us	20	20	100.00
		pwm_csr_aliasing	54.000s	82.551us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.483m	21.434ms	50	50	100.00
V2	pulse	pwm_rand_output	2.483m	21.434ms	50	50	100.00
V2	blink	pwm_rand_output	2.483m	21.434ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.483m	21.434ms	50	50	100.00
V2	resolution	pwm_rand_output	2.483m	21.434ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.483m	21.434ms	50	50	100.00
V2	polarity	pwm_rand_output	2.483m	21.434ms	50	50	100.00
V2	phase	pwm_rand_output	2.483m	21.434ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.483m	21.434ms	50	50	100.00
V2	perf	pwm_perf	1.583m	10.830ms	50	50	100.00
V2	stress_all	pwm_stress_all	5.983m	76.558ms	45	50	90.00
V2	alert_test	pwm_alert_test	1.250m	15.190us	50	50	100.00
V2	intr_test	pwm_intr_test	1.800m	41.681us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	30.000s	143.139us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	30.000s	143.139us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	54.000s	20.125us	5	5	100.00
		pwm_csr_rw	54.000s	46.292us	20	20	100.00
		pwm_csr_aliasing	54.000s	82.551us	5	5	100.00
		pwm_same_csr_outstanding	1.633m	226.491us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	54.000s	20.125us	5	5	100.00
		pwm_csr_rw	54.000s	46.292us	20	20	100.00
		pwm_csr_aliasing	54.000s	82.551us	5	5	100.00
		pwm_same_csr_outstanding	1.633m	226.491us	20	20	100.00
V2		TOTAL			285	290	98.28
V2S	tl_intg_err	pwm_tl_intg_err	47.000s	541.767us	20	20	100.00
		pwm_sec_cm	1.033m	73.338us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	47.000s	541.767us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			415	420	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.50	99.41	98.95	99.88	95.20	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 5 failures:

Test pwm_stress_all has 5 failures.

5.pwm_stress_all.8945917955808433048017287001840994540561592071447021395451463332343745609395
Line 24808, in log /workspaces/repo/scratch/os_regression_2024_10_14/pwm-sim-xcelium/5.pwm_stress_all/latest/run.log

  UVM_ERROR @ 22693637561 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 22693637561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.pwm_stress_all.66141825884292320325542694039552960174531093078681199018358271903178519233567
Line 24927, in log /workspaces/repo/scratch/os_regression_2024_10_14/pwm-sim-xcelium/10.pwm_stress_all/latest/run.log

  UVM_ERROR @ 175785894375 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 175785894375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.