PWM Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: f8b3c19a2

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1284268927

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 8.000s 1.020ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 4.000s 30.470us 5 5 100.00
V1 csr_rw pwm_csr_rw 6.000s 197.034us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 16.000s 659.246us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 133.578us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 6.000s 32.661us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 6.000s 197.034us 20 20 100.00
pwm_csr_aliasing 5.000s 133.578us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 2.000m 37.497ms 50 50 100.00
V2 pulse pwm_rand_output 2.000m 37.497ms 50 50 100.00
V2 blink pwm_rand_output 2.000m 37.497ms 50 50 100.00
V2 heartbeat pwm_rand_output 2.000m 37.497ms 50 50 100.00
V2 resolution pwm_rand_output 2.000m 37.497ms 50 50 100.00
V2 multi_channel pwm_rand_output 2.000m 37.497ms 50 50 100.00
V2 polarity pwm_rand_output 2.000m 37.497ms 50 50 100.00
V2 phase pwm_rand_output 2.000m 37.497ms 50 50 100.00
V2 lowpower pwm_rand_output 2.000m 37.497ms 50 50 100.00
V2 perf pwm_perf 52.000s 49.991ms 49 50 98.00
V2 stress_all pwm_stress_all 4.467m 53.028ms 48 50 96.00
V2 alert_test pwm_alert_test 5.000s 52.857us 50 50 100.00
V2 intr_test pwm_intr_test 5.000s 14.890us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 8.000s 43.811us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 8.000s 43.811us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 4.000s 30.470us 5 5 100.00
pwm_csr_rw 6.000s 197.034us 20 20 100.00
pwm_csr_aliasing 5.000s 133.578us 5 5 100.00
pwm_same_csr_outstanding 6.000s 99.995us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 4.000s 30.470us 5 5 100.00
pwm_csr_rw 6.000s 197.034us 20 20 100.00
pwm_csr_aliasing 5.000s 133.578us 5 5 100.00
pwm_same_csr_outstanding 6.000s 99.995us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err pwm_tl_intg_err 8.000s 630.431us 20 20 100.00
pwm_sec_cm 4.000s 65.799us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 8.000s 630.431us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 417 420 99.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.64 99.56 99.20 99.88 95.48 94.92 -- 100.00 99.34

Failure Buckets

Past Results