PWM Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	1.339ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	56.311us	5	5	100.00
V1	csr_rw	pwm_csr_rw	7.000s	19.972us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	2.717ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	8.000s	100.466us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	13.000s	128.540us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	7.000s	19.972us	20	20	100.00
		pwm_csr_aliasing	8.000s	100.466us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.017m	42.000ms	50	50	100.00
V2	pulse	pwm_rand_output	2.017m	42.000ms	50	50	100.00
V2	blink	pwm_rand_output	2.017m	42.000ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.017m	42.000ms	50	50	100.00
V2	resolution	pwm_rand_output	2.017m	42.000ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.017m	42.000ms	50	50	100.00
V2	polarity	pwm_rand_output	2.017m	42.000ms	50	50	100.00
V2	phase	pwm_rand_output	2.017m	42.000ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.017m	42.000ms	50	50	100.00
V2	perf	pwm_perf	52.000s	10.502ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.167m	253.993ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	56.471us	50	50	100.00
V2	intr_test	pwm_intr_test	7.000s	12.821us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	11.000s	695.106us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	11.000s	695.106us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	56.311us	5	5	100.00
		pwm_csr_rw	7.000s	19.972us	20	20	100.00
		pwm_csr_aliasing	8.000s	100.466us	5	5	100.00
		pwm_same_csr_outstanding	8.000s	39.909us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	56.311us	5	5	100.00
		pwm_csr_rw	7.000s	19.972us	20	20	100.00
		pwm_csr_aliasing	8.000s	100.466us	5	5	100.00
		pwm_same_csr_outstanding	8.000s	39.909us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	8.000s	180.269us	20	20	100.00
		pwm_sec_cm	3.000s	78.887us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	8.000s	180.269us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.07	99.14	98.46	99.60	94.21	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

15.pwm_stress_all.106707931335015507871508232126487097412525924532481795998740994815142394896971
Line 1429, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/15.pwm_stress_all/latest/run.log

  UVM_ERROR @ 71873483202 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 71873483202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.pwm_stress_all.103127440544412481266639142557379154771329645745380350204052766924600318342923
Line 105179, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/43.pwm_stress_all/latest/run.log

  UVM_ERROR @ 116713469328 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [3] did not MATCH
  UVM_INFO @ 116713469328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---