PWM Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 16.000s 2.546ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 67.391us 5 5 100.00
V1 csr_rw pwm_csr_rw 13.000s 55.241us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 6.000s 1.198ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 3.000s 204.941us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 13.000s 88.091us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 13.000s 55.241us 20 20 100.00
pwm_csr_aliasing 3.000s 204.941us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.067m 52.498ms 50 50 100.00
V2 pulse pwm_rand_output 1.067m 52.498ms 50 50 100.00
V2 blink pwm_rand_output 1.067m 52.498ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.067m 52.498ms 50 50 100.00
V2 resolution pwm_rand_output 1.067m 52.498ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.067m 52.498ms 50 50 100.00
V2 polarity pwm_rand_output 1.067m 52.498ms 50 50 100.00
V2 phase pwm_rand_output 1.067m 52.498ms 50 50 100.00
V2 lowpower pwm_rand_output 1.067m 52.498ms 50 50 100.00
V2 perf pwm_perf 1.000m 52.488ms 50 50 100.00
V2 stress_all pwm_stress_all 1.433m 57.672ms 50 50 100.00
V2 alert_test pwm_alert_test 15.000s 42.841us 50 50 100.00
V2 intr_test pwm_intr_test 13.000s 36.141us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 14.000s 300.191us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 14.000s 300.191us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 67.391us 5 5 100.00
pwm_csr_rw 13.000s 55.241us 20 20 100.00
pwm_csr_aliasing 3.000s 204.941us 5 5 100.00
pwm_same_csr_outstanding 13.000s 136.041us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 67.391us 5 5 100.00
pwm_csr_rw 13.000s 55.241us 20 20 100.00
pwm_csr_aliasing 3.000s 204.941us 5 5 100.00
pwm_same_csr_outstanding 13.000s 136.041us 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err pwm_tl_intg_err 14.000s 297.291us 20 20 100.00
pwm_sec_cm 7.000s 162.741us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 14.000s 297.291us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 420 420 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.66 96.79 94.27 99.20 88.28 91.69 -- 94.34 68.09

Past Results