PWRMGR Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: 50278df8b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.710s	30.785us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	42.594us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	21.768us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.510s	564.473us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	43.638us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.610s	132.045us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	21.768us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	43.638us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.710s	330.542us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.710s	330.542us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.810s	33.223us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	46.796us	50	50	100.00
V2	reset	pwrmgr_reset	1.390s	84.379us	50	50	100.00
		pwrmgr_reset_invalid	1.110s	99.359us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.390s	84.379us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.660s	296.995us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.700s	286.633us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.960s	57.560us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.140s	2.175ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.660s	18.306us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.450s	52.487us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.450s	52.487us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	42.594us	5	5	100.00
		pwrmgr_csr_rw	0.700s	21.768us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	43.638us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	25.212us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	42.594us	5	5	100.00
		pwrmgr_csr_rw	0.700s	21.768us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	43.638us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	25.212us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.900s	1.418ms	20	20	100.00
		pwrmgr_sec_cm	1.710s	668.608us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.710s	668.608us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.710s	668.608us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.900s	1.418ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.110s	839.919us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.260s	866.561us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.050s	75.485us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	29.815us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.710s	668.608us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.710s	668.608us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.710s	668.608us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.740s	85.161us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	42.089us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.630s	231.125us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	21.768us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	21.768us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	54.150s	12.473ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1069	1070	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	98.21	96.58	99.44	96.00	96.27	100.00	99.02

Failure Buckets

• Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])' has 1 failures:
  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 16.pwrmgr_stress_all_with_rand_reset.1146479534
      Line 608, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])'
        UVM_ERROR @ 3656478508 ps: (pwrmgr.sv:155) [ASSERT FAILED] PwrmgrSecCmEscToSlowResetReq_A
        UVM_INFO @ 3656478508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.15_18.45.06
• 2023.05.14_18.13.20
• 2023.05.13_18.57.20
• 2023.05.12_18.48.02
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• 2023.05.11_18.03.33
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