PWRMGR Simulation Results

Sunday October 08 2023 19:02:39 UTC

GitHub Revision: `4e80560e2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3527490040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.840s	62.720us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	222.877us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.740s	62.892us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.360s	357.331us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.990s	148.114us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.550s	56.260us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.740s	62.892us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	148.114us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.710s	320.527us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.710s	320.527us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.970s	40.847us	50	50	100.00
		pwrmgr_lowpower_invalid	0.870s	73.454us	50	50	100.00
V2	reset	pwrmgr_reset	1.380s	73.921us	50	50	100.00
		pwrmgr_reset_invalid	1.110s	110.937us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.380s	73.921us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.880s	331.097us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.620s	274.233us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.920s	55.805us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.210s	1.795ms	49	50	98.00
V2	intr_test	pwrmgr_intr_test	0.670s	21.119us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.320s	556.184us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.320s	556.184us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	222.877us	5	5	100.00
		pwrmgr_csr_rw	0.740s	62.892us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	148.114us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	45.483us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	222.877us	5	5	100.00
		pwrmgr_csr_rw	0.740s	62.892us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	148.114us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	45.483us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.880s	279.266us	20	20	100.00
		pwrmgr_sec_cm	2.350s	655.566us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.350s	655.566us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.350s	655.566us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.880s	279.266us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.080s	788.319us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.400s	899.256us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.150s	167.578us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.800s	37.777us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.350s	655.566us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.350s	655.566us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.350s	655.566us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	43.048us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	48.056us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.840s	283.774us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.740s	62.892us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.740s	62.892us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	40.890s	8.485ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1066	1070	99.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	8	88.89
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	98.22	96.58	99.44	96.00	96.32	100.00	99.02

Failure Buckets

Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 2 failures:

Test pwrmgr_stress_all_with_rand_reset has 2 failures.

14.pwrmgr_stress_all_with_rand_reset.3740756879
Line 623, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest/run.log

      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 2249745175 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 2249745175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.pwrmgr_stress_all_with_rand_reset.2886156439
Line 3682, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest/run.log

      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 26820101723 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 26820101723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: pwrmgr_reg_block.wake_status reset value: * wake_status has 1 failures:
- Test pwrmgr_stress_all has 1 failures.
  - 19.pwrmgr_stress_all.1922031030
    Line 294, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_stress_all/latest/run.log
```
  UVM_ERROR @ 576805498 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: pwrmgr_reg_block.wake_status reset value: 0x0 wake_status
  UVM_INFO @ 576805498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.
  - 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3165761959
    Line 667, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
```
  UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```