e9ba8b38f
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwrmgr_smoke | 0.710s | 31.502us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.670s | 31.568us | 5 | 5 | 100.00 |
V1 | csr_rw | pwrmgr_csr_rw | 0.670s | 35.748us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.490s | 325.401us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwrmgr_csr_aliasing | 0.930s | 25.323us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.360s | 368.828us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.670s | 35.748us | 20 | 20 | 100.00 |
pwrmgr_csr_aliasing | 0.930s | 25.323us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | wakeup | pwrmgr_wakeup | 1.520s | 238.114us | 50 | 50 | 100.00 |
V2 | control_clks | pwrmgr_wakeup | 1.520s | 238.114us | 50 | 50 | 100.00 |
V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.860s | 38.951us | 50 | 50 | 100.00 |
pwrmgr_lowpower_invalid | 0.750s | 44.601us | 50 | 50 | 100.00 | ||
V2 | reset | pwrmgr_reset | 1.380s | 73.538us | 50 | 50 | 100.00 |
pwrmgr_reset_invalid | 1.010s | 76.239us | 0 | 50 | 0.00 | ||
V2 | main_power_glitch_reset | pwrmgr_reset | 1.380s | 73.538us | 50 | 50 | 100.00 |
V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.800s | 281.787us | 50 | 50 | 100.00 |
V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.520s | 250.213us | 50 | 50 | 100.00 |
V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.990s | 66.524us | 50 | 50 | 100.00 |
V2 | stress_all | pwrmgr_stress_all | 7.860s | 2.101ms | 50 | 50 | 100.00 |
V2 | intr_test | pwrmgr_intr_test | 0.670s | 48.696us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.710s | 156.615us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.710s | 156.615us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.670s | 31.568us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.670s | 35.748us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.930s | 25.323us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.890s | 598.899us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.670s | 31.568us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.670s | 35.748us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.930s | 25.323us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.890s | 598.899us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 490 | 540 | 90.74 | |||
V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.730s | 200.665us | 20 | 20 | 100.00 |
pwrmgr_sec_cm | 2.260s | 687.292us | 5 | 5 | 100.00 | ||
V2S | prim_count_check | pwrmgr_sec_cm | 2.260s | 687.292us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | pwrmgr_sec_cm | 2.260s | 687.292us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.730s | 200.665us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 4.120s | 847.552us | 50 | 50 | 100.00 |
V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 4.270s | 935.870us | 50 | 50 | 100.00 |
V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.970s | 76.370us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.680s | 28.758us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.260s | 687.292us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.260s | 687.292us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.260s | 687.292us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.660s | 141.847us | 50 | 50 | 100.00 |
V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.710s | 45.221us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.770s | 294.763us | 50 | 50 | 100.00 |
V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.670s | 35.748us | 20 | 20 | 100.00 |
V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.670s | 35.748us | 20 | 20 | 100.00 |
V2S | TOTAL | 375 | 375 | 100.00 | |||
V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 36.100s | 9.846ms | 50 | 50 | 100.00 |
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 1020 | 1070 | 95.33 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 12 | 12 | 11 | 91.67 |
V2S | 9 | 9 | 9 | 100.00 |
V3 | 1 | 1 | 1 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
94.80 | 98.22 | 96.58 | 99.44 | 74.00 | 96.32 | 100.00 | 99.02 |
Offending '(fast_state == FastPwrStateRomCheckGood)'
has 50 failures:
0.pwrmgr_reset_invalid.223176696
Line 300, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log
Offending '(fast_state == FastPwrStateRomCheckGood)'
UVM_ERROR @ 67646888 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
UVM_INFO @ 67646888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_reset_invalid.2222078392
Line 241, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log
Offending '(fast_state == FastPwrStateRomCheckGood)'
UVM_ERROR @ 156634989 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
UVM_INFO @ 156634989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.