Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31645 1 T1 360 T2 4 T3 7
auto[1] 30633 1 T1 322 T2 4 T3 10


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32160 1 T1 336 T2 6 T3 8
auto[1] 30118 1 T1 346 T2 2 T3 9


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30403 1 T1 310 T2 4 T3 10
auto[1] 31875 1 T1 372 T2 4 T3 7


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35314 1 T1 390 T2 4 T3 17
auto[1] 26964 1 T1 292 T2 4 T4 1


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30846 1 T1 337 T2 4 T3 7
auto[1] 31432 1 T1 345 T2 4 T3 10


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31960 1 T1 347 T2 4 T3 8
auto[1] 30318 1 T1 335 T2 4 T3 9


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1095 1 T1 11 T3 1 T10 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 821 1 T1 8 T10 2 T55 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1104 1 T1 11 T10 8 T54 4
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 821 1 T1 10 T10 5 T54 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1095 1 T1 12 T3 1 T54 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 844 1 T1 8 T54 1 T24 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1728 1 T1 15 T4 1 T6 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1487 1 T1 14 T4 1 T6 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1050 1 T1 13 T6 1 T10 3
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 801 1 T1 10 T6 1 T10 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1068 1 T1 17 T6 1 T10 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 823 1 T1 11 T6 1 T10 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1064 1 T1 10 T6 1 T10 3
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 792 1 T1 9 T6 1 T10 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1099 1 T1 11 T2 1 T3 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 848 1 T1 8 T2 1 T10 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1127 1 T1 15 T10 4 T54 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 873 1 T1 11 T10 3 T37 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1102 1 T1 12 T10 3 T54 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 830 1 T1 9 T10 3 T37 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1034 1 T1 15 T3 1 T7 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 782 1 T1 10 T7 1 T10 4
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1073 1 T1 13 T2 1 T3 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 822 1 T1 9 T2 1 T6 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1049 1 T1 12 T3 1 T10 6
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 802 1 T1 7 T10 3 T24 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1072 1 T1 12 T6 1 T7 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 815 1 T1 7 T6 1 T7 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1035 1 T1 8 T7 1 T10 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 791 1 T1 7 T7 1 T55 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1108 1 T1 21 T3 1 T6 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 790 1 T1 14 T6 1 T7 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1174 1 T1 7 T2 1 T10 7
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 896 1 T1 6 T2 1 T10 3
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1100 1 T1 17 T3 1 T6 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 837 1 T1 11 T6 2 T55 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1065 1 T1 10 T3 1 T10 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 826 1 T1 8 T10 1 T54 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1087 1 T1 11 T7 1 T10 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 824 1 T1 8 T7 1 T10 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1119 1 T1 11 T2 1 T6 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 857 1 T1 9 T2 1 T6 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1165 1 T1 14 T3 1 T10 7
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 888 1 T1 12 T10 5 T55 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1069 1 T1 9 T3 2 T6 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 812 1 T1 9 T6 2 T10 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1076 1 T1 9 T10 4 T54 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 825 1 T1 7 T10 3 T55 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1080 1 T1 14 T6 1 T54 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 832 1 T1 11 T6 1 T24 3
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1097 1 T1 11 T3 1 T10 5
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 829 1 T1 8 T10 1 T54 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1067 1 T1 8 T3 1 T6 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 810 1 T1 7 T6 1 T10 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1023 1 T1 16 T6 1 T55 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 775 1 T1 11 T6 1 T24 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1069 1 T1 7 T3 1 T10 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 785 1 T1 4 T10 1 T54 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1058 1 T1 12 T3 1 T10 3
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 807 1 T1 7 T10 3 T24 2
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1087 1 T1 13 T3 1 T10 6
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 800 1 T1 11 T10 3 T24 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1075 1 T1 13 T6 1 T10 3
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 819 1 T1 11 T6 1 T10 2

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