Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16489 |
1 |
|
|
T1 |
138 |
|
T5 |
2 |
|
T8 |
6 |
auto[1] |
25866 |
1 |
|
|
T1 |
225 |
|
T4 |
1 |
|
T5 |
3 |
Summary for Variable reset_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for reset_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
35576 |
1 |
|
|
T1 |
327 |
|
T2 |
4 |
|
T4 |
1 |
auto[1] |
9311 |
1 |
|
|
T1 |
37 |
|
T4 |
1 |
|
T5 |
4 |
Summary for Variable sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sleep_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
18035 |
1 |
|
|
T1 |
72 |
|
T4 |
1 |
|
T5 |
5 |
auto[1] |
26852 |
1 |
|
|
T1 |
292 |
|
T2 |
4 |
|
T4 |
1 |
Summary for Cross reset_cross
Samples crossed: reset_cp enable_cp sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for reset_cross
Bins
reset_cp | enable_cp | sleep_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
4144 |
1 |
|
|
T1 |
21 |
|
T8 |
4 |
|
T10 |
7 |
auto[0] |
auto[0] |
auto[1] |
9245 |
1 |
|
|
T1 |
108 |
|
T10 |
11 |
|
T24 |
18 |
auto[0] |
auto[1] |
auto[0] |
4368 |
1 |
|
|
T1 |
14 |
|
T5 |
1 |
|
T8 |
2 |
auto[0] |
auto[1] |
auto[1] |
15287 |
1 |
|
|
T1 |
183 |
|
T10 |
47 |
|
T24 |
32 |
auto[1] |
auto[0] |
auto[0] |
3100 |
1 |
|
|
T1 |
9 |
|
T5 |
2 |
|
T8 |
2 |
auto[1] |
auto[1] |
auto[0] |
6211 |
1 |
|
|
T1 |
28 |
|
T4 |
1 |
|
T5 |
2 |
User Defined Cross Bins for reset_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
illegal |
0 |
Illegal |