ROM_CTRL Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	36.120s	5.356ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.660s	4.589ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.640s	2.175ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.180s	2.673ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.130s	6.960ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.220s	8.130ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.640s	2.175ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.130s	6.960ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.550s	2.106ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.350s	6.376ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.970s	9.281ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.407m	40.401ms	47	50	94.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	29.630s	3.934ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.830s	8.171ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.940s	2.187ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.940s	2.187ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.660s	4.589ms	5	5	100.00
		rom_ctrl_csr_rw	14.640s	2.175ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.130s	6.960ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.230s	2.916ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.660s	4.589ms	5	5	100.00
		rom_ctrl_csr_rw	14.640s	2.175ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.130s	6.960ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.230s	2.916ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	6.440m	45.220ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.725m	4.561ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.226m	2.319ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.725m	4.561ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.725m	4.561ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.725m	4.561ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	36.120s	5.356ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	36.120s	5.356ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	36.120s	5.356ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.226m	2.319ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
		rom_ctrl_kmac_err_chk	29.630s	3.934ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.926m	31.647ms	47	50	94.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	6.440m	45.220ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.725m	4.561ms	5	5	100.00
V2S		TOTAL			91	95	95.79
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.739h	67.206ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			474	500	94.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.73	97.16	93.12	97.88	86.67	98.68	98.19	98.38

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 14 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.3289505188
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d05a1061-efcc-4f97-911f-393a7f5be2a5
```
  - 3.rom_ctrl_stress_all_with_rand_reset.2343263879
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a84dfd6d-aed8-4c12-aa9d-2fed46bf9cdd
```
  - ... and 12 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 6 failures:

Test rom_ctrl_stress_all has 3 failures.

11.rom_ctrl_stress_all.1521456792
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10018363936 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x94ad8396
  UVM_INFO @ 10018363936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.rom_ctrl_stress_all.1771108232
Line 220, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/36.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10079449840 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x2b67118d
  UVM_INFO @ 10079449840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

11.rom_ctrl_stress_all_with_rand_reset.3172619751
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10004954435 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x3b8943d0
  UVM_INFO @ 10004954435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_smoke has 2 failures.

29.rom_ctrl_smoke.2817109561
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/29.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10006043185 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf6045418
  UVM_INFO @ 10006043185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.rom_ctrl_smoke.1772645542
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/37.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10010104332 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x67c4d40a
  UVM_INFO @ 10010104332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.

3.rom_ctrl_corrupt_sig_fatal_chk.480135445
Line 233, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.rom_ctrl_corrupt_sig_fatal_chk.1717542185
Line 231, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:

Test rom_ctrl_stress_all_with_rand_reset has 2 failures.

29.rom_ctrl_stress_all_with_rand_reset.404415790
Line 683, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 892336334932 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 892336334932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.rom_ctrl_stress_all_with_rand_reset.796906231
Line 426, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 425384107231 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 425384107231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 14.rom_ctrl_passthru_mem_tl_intg_err.1113061360
    Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10017218862 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe00f8008
  UVM_INFO @ 10017218862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 45.rom_ctrl_corrupt_sig_fatal_chk.3346014126
    Line 232, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 819540634 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 819540634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```